Ferroelectric memory and manufacturing method thereof

Abstract

The invention discloses a ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises a semiconductor substrate; the switching transistor comprises a grid electrode located on the semiconductor substrate, and a source electrode and a drain electrode which are located in the semiconductor substrate; the first interlayer dielectric layer covers the switching transistor, and the upper surface of the first interlayer dielectric layer is provided with a plurality of discrete fin structures; and the ferroelectric capacitor is formed on the fin structure, the ferroelectric capacitor comprises a first polar plate, a second polar plate and a ferroelectric film located between the first polar plate and the second polar plate, and the first polar plate is electrically connected with the switching transistor. According to the invention, the ferroelectric capacitor is formed on the fin structure, the fin-type ferroelectric capacitor is formed, the area of the ferroelectric capacitor is increased, and the capacitance value of the ferroelectric capacitor is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a ferroelectric memory and a manufacturing method thereof. Background Art

[0002] Ferroelectric RAM (FRAM) is a new type of memory that combines the non-volatility of read-only memory (ROM) and the non-volatility of random access memory (RAM), strong durability, high-speed reading and writing, and low power consumption.

[0003] The core part of ferroelectric memory is ferroelectric capacitor. The structure of ferroelectric capacitor is generally metal-insulator-metal (MIM) type. The upper and lower metal layers are capacitor electrodes, and the middle is ferroelectric thin film material. Ferroelectric thin film material has ferroelectric effect. Under the external electric field of the upper and lower electrodes of the dielectric, the iron domain of the ferroelectric thin film material presents different polarization states with the electric field in different directions. The capacitance will change with the change of polarization state, so that the amount and polarity of the charge stored in the capacitor will change with the change of the polarization direction and size of the capacitor. At the same time, because the polarization strength of the material can still be maintained when the external electric field is removed, the capacitor has non-volatile charge storage capacity and realizes data storage.

[0004] The 1T1C structure is a common storage unit of ferroelectric memory, which is a transistor and a capacitor. However, as the key dimensions of integrated circuits are getting smaller and smaller along Moore's Law, the corresponding storage unit area also needs to be scaled down in proportion, resulting in the problem of insufficient effective area of ​​ferroelectric capacitors. Since the capacitance value of ferroelectric capacitors decreases as the effective area decreases, too small a capacitance makes it impossible for ferroelectric capacitors to provide sufficient surface charge during the reading and writing process, which ultimately leads to reading and writing difficulties or even errors. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In view of the existing problems, an embodiment of the present invention provides a ferroelectric memory, wherein the ferroelectric memory comprises:

[0007] Semiconductor substrate;

[0008] a switching transistor, the switching transistor comprising a gate located on the semiconductor substrate, and a source and a drain located in the semiconductor substrate;

[0009] A first interlayer dielectric layer covers the switch transistor, wherein the upper surface of the first interlayer dielectric layer has a plurality of discrete fin structures;

[0010] A ferroelectric capacitor is formed on the fin structure, and includes a first plate, a second plate, and a ferroelectric film located between the first plate and the second plate, wherein the first plate is electrically connected to the switch transistor.

[0011] In some embodiments, the top and bottom of the fin structure are arc-shaped.

[0012] In some embodiments, the ferroelectric memory further includes a first contact hole, wherein the first contact hole penetrates the first interlayer dielectric layer, and the first contact hole connects the first electrode plate and the drain of the switch transistor.

[0013] In some embodiments, the ferroelectric memory further includes a cap layer formed on an upper surface of the ferroelectric capacitor.

[0014] In some embodiments, the ferroelectric memory further comprises:

[0015] a second interlayer dielectric layer, wherein the second interlayer dielectric layer covers the ferroelectric capacitor;

[0016] a second contact hole, wherein the second contact hole penetrates the first interlayer dielectric layer and the second interlayer dielectric layer and is connected to the source electrode;

[0017] A third contact hole penetrates the second interlayer dielectric layer and is connected to the second electrode plate.

[0018] Another aspect of the present invention provides a method for manufacturing a ferroelectric memory, the method comprising:

[0019] providing a semiconductor substrate;

[0020] forming a gate of a switching transistor on the semiconductor substrate, and forming a source and a drain of the switching transistor in the semiconductor substrate;

[0021] Forming a first interlayer dielectric layer covering the semiconductor substrate and the switch transistor, and forming a plurality of fin structures on a surface of the first interlayer dielectric layer;

[0022] A ferroelectric capacitor is formed on the fin structure. The ferroelectric capacitor includes a first plate, a second plate, and a ferroelectric film located between the first plate and the second plate. The first plate is electrically connected to the switch transistor.

[0023] In some embodiments, forming a plurality of fin structures on the surface of the first interlayer dielectric layer includes:

[0024] forming a plurality of photoresist patterns arranged at intervals on the first interlayer dielectric layer;

[0025] Using the photoresist pattern as a mask, dry-etching the first interlayer dielectric layer to form a groove between each two adjacent photoresist patterns, wherein the groove is used to divide the fin structure;

[0026] During the dry etching process, a polymer layer is gradually formed on the sidewalls of the trench, so that the bottom of the trench is in an arc shape.

[0027] Furthermore, during the dry etching process, the top of the photoresist pattern gradually changes into an arc shape, so that the top of the fin structure is in an arc shape.

[0028] In some embodiments, after forming the trench, the method further includes:

[0029] The polymer layer is removed.

[0030] In some embodiments, the forming of a first interlayer dielectric layer covering the switch transistor includes:

[0031] Forming a first portion of the first interlayer dielectric layer covering the switch transistor, and forming a second portion of the first interlayer dielectric layer above the first portion of the first interlayer dielectric layer, wherein the second portion of the first interlayer dielectric layer is used to form the fin structure;

[0032] After forming the first portion of the first interlayer dielectric layer and before forming the second portion of the first interlayer dielectric layer, the method further includes: forming a first contact hole penetrating the first interlayer dielectric layer, the first contact hole connecting the first electrode plate and the drain of the switching transistor.

[0033] In some embodiments, after forming the ferroelectric capacitor, the method further includes:

[0034] forming a second interlayer dielectric layer covering the ferroelectric capacitor;

[0035] forming a second contact hole penetrating the second interlayer dielectric layer and the first interlayer dielectric layer, wherein the second contact hole is connected to the source electrode;

[0036] A third contact hole is formed penetrating the second interlayer dielectric layer, wherein the third contact hole is connected to the second electrode plate.

[0037] According to the ferroelectric memory and the manufacturing method thereof provided by the embodiments of the present invention, the ferroelectric capacitor is formed on the fin structure, the actual area of ​​the ferroelectric capacitor is increased under the condition that the projected area remains unchanged, and thus the capacitance value thereof is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0039] In the attached figure:

[0040] Figure 1 A cross-sectional schematic diagram of an existing ferroelectric memory is shown;

[0041] Figure 2 A schematic flow chart showing a method for manufacturing a ferroelectric memory according to a specific embodiment of the present invention;

[0042] FIG. 3A to FIG. 3I A cross-sectional schematic diagram of a ferroelectric memory obtained by sequentially implementing each step of a method for manufacturing a ferroelectric memory according to an embodiment of the present invention is shown;

[0043] Figure 4 A circuit netlist of a ferroelectric memory according to an embodiment of the present invention is shown;

[0044] Figure 5 FIG. 4 shows an array layout of a ferroelectric memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0046] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0047] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0048] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0049] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] like Figure 1 As shown, the current ferroelectric memory includes a semiconductor substrate 101, a switch transistor 102 and a ferroelectric capacitor 103, wherein the ferroelectric capacitor 103 is a planar structure, and is composed of an upper plate, a lower plate and a ferroelectric film located between the upper and lower plates. Figure 1The ferroelectric memory shown has the problem of insufficient effective capacitor area. Since the capacitance of the ferroelectric capacitor decreases as the effective area decreases, an excessively small capacitance value makes the ferroelectric capacitor unable to provide sufficient surface charge during the reading and writing process, ultimately leading to reading and writing difficulties or even errors.

[0051] In view of the above problems, an embodiment of the present invention provides a method for manufacturing a ferroelectric memory, such as Figure 2 As shown, the manufacturing method comprises the following steps:

[0052] Step S210: providing a semiconductor substrate;

[0053] Step S220: forming a gate of a switch transistor on the semiconductor substrate, and forming a source and a drain of the switch transistor in the semiconductor substrate;

[0054] Step S230: forming a first interlayer dielectric layer covering the semiconductor substrate and the switch transistor, and forming a plurality of discrete fin structures on an upper surface of the first interlayer dielectric layer;

[0055] Step S240: forming a ferroelectric capacitor on the fin structure, wherein the ferroelectric capacitor comprises a first electrode plate, a second electrode plate and a ferroelectric film located between the first electrode plate and the second electrode plate, and the first electrode plate is electrically connected to the switch transistor.

[0056] like Fig. 3I As shown, an embodiment of the present invention further proposes a ferroelectric memory, comprising: a semiconductor substrate 301; a switching transistor, the switching transistor comprising a gate 302 located on the semiconductor substrate 301, and a drain 303 and a source 304 located in the semiconductor substrate; a first interlayer dielectric layer 305, covering the switching transistor, the upper surface of the first interlayer dielectric layer 305 having a plurality of discrete fin structures; a ferroelectric capacitor 309, formed on the fin structure, the ferroelectric capacitor comprising a first plate 309A, a second plate 309C and a ferroelectric film 309B located between the first plate 309A and the second plate 309C, the first plate 309A being electrically connected to the switching transistor.

[0057] The ferroelectric memory and the manufacturing method thereof of the embodiment of the present invention form a ferroelectric capacitor on a fin structure, thereby increasing the actual area of ​​the ferroelectric capacitor while keeping the projected area unchanged, thereby improving its capacitance value.

[0058] In order to fully understand the present invention, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0059] Combine the following Figure 2and Figure 3A to Figure 3I The implementation process of the method for manufacturing a ferroelectric memory according to an embodiment of the present invention is described exemplarily. Figure 2 A schematic flow chart showing a method for manufacturing a ferroelectric memory according to an embodiment of the present invention is shown. Figure 3A to Figure 3I The cross-sectional schematic diagram of a ferroelectric memory obtained by sequentially implementing each step of a method for manufacturing a ferroelectric memory according to an embodiment of the present invention is shown.

[0060] First, if Figure 3A As shown, a semiconductor substrate is provided.

[0061] Exemplarily, the semiconductor substrate 301 may be at least one of the following materials: silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, the constituent material of the semiconductor substrate 301 may be single crystal silicon. Various well structures are also formed in the semiconductor substrate 301, which are omitted in the figure for simplicity.

[0062] Next, a gate 302 of a switching transistor is formed on a semiconductor substrate 301, and a source 304 and a drain 303 located on both sides of the gate 302 are formed in the semiconductor substrate 301. Exemplarily, the gate 302 is a word line (WordLine, WL) of a ferroelectric memory, the source 304 is used to connect a bit line (Bit Line, BL), and the drain 303 is used to connect a ferroelectric capacitor.

[0063] Exemplarily, the gate includes a gate dielectric layer, a gate electrode layer and a gate sidewall. The gate dielectric layer includes an oxide layer, such as a silicon dioxide (SiO2) layer. The gate electrode layer includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer and a metal silicide layer. The gate sidewall may be composed of an oxide, a nitride or a combination of the two. The gate dielectric layer, the gate electrode layer and the gate sidewall may be formed by any prior art familiar to those skilled in the art, including but not limited to chemical vapor deposition (CVD), such as low temperature chemical vapor deposition (LTCVD), low pressure chemical vapor deposition (LPCVD), rapid thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD), etc.

[0064] Next, source / drain ion implantation is performed to form a source 304 and a drain 303 in the semiconductor substrate 301 on both sides of the gate 302. The type of implanted ions and the doping concentration of the source / drain ion implantation can be selected from the commonly used ranges in the art. After the ion implantation is performed, annealing treatment can be performed to activate the implanted ions in the source / drain, and the annealing treatment can be a spike annealing process.

[0065] After forming the source 304 and the drain 303, a metal silicide process is performed to form a metal silicide layer. Specifically, a metal layer is deposited on the surface of the semiconductor substrate 301 and the gate 302, and then a rapid annealing process (RTA) is performed. Since the metal can react with silicon, but will not react with silicon oxides such as silicon dioxide, the metal will only react with the exposed surface of the semiconductor substrate or the surface of the gate to form a metal silicide. The deposited metal can be any metal such as nickel (Ni), titanium (Ti) or cobalt (Co), and accordingly, the formed metal silicide can be nickel-based silicide, titanium-based silicide or cobalt-based silicide. The metal that has not reacted can be removed later, for example, an acidic solution can be used to remove the metal that has not reacted on the metal silicide barrier layer. In the subsequent process flow, contact holes will be formed on the metal silicide.

[0066] Next, a first interlayer dielectric layer 305 is formed to cover the switch transistor, and a plurality of fin structures are formed on the surface of the first interlayer dielectric layer 305 .

[0067] Exemplarily, the material of the first interlayer dielectric layer 305 may be a silicon oxide layer, including a doped or undoped silicon oxide material layer formed by a chemical vapor deposition (CVD) manufacturing process or a high density plasma (HDP) manufacturing process, such as undoped silicon glass (USG), phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG). Exemplarily, the first interlayer dielectric layer 305 may also be spin-on glass (SOG) doped with boron or phosphorus, tetraethoxysilane doped with phosphorus (PTEOS) or tetraethoxysilane doped with boron (BTEOS), etc.

[0068] For example, in order to facilitate the formation of contact holes, the first interlayer dielectric layer 305 can be formed in two steps. Figure 3A and Figure 3B As shown, the first interlayer dielectric layer 305 of the first part is formed. For example, a silicon oxide layer with a thickness of about 6000 angstroms to 7000 angstroms is first deposited, and then the silicon oxide layer is polished to 3000 angstroms to 3500 angstroms using a planarization process to make its upper surface flat. The planarization process includes a conventional planarization method in the field of semiconductor manufacturing, such as a chemical mechanical polishing (CMP) process.

[0069] Next, the first part of the interlayer dielectric layer is etched to form a first contact hole 306, and the first contact hole 306 is used to electrically connect the drain 303 to the ferroelectric capacitor 309. The first contact hole 306 is located above the drain 303, and the etching of the first contact hole can stop at the metal silicide layer. Exemplarily, a patterned photoresist layer is first formed on the first part of the first interlayer dielectric layer 305, and then the first part of the first interlayer dielectric layer 305 is etched using the photoresist layer as a mask to form the first contact hole 306, and finally the first contact hole 306 is filled with a conductive material, such as tungsten or aluminum, wherein a chemical vapor deposition process can be used in the first contact hole 306 to form adhesion, and then the conductive material is filled to improve the adhesion between the conductive material and the silicon oxide layer. Finally, a chemical mechanical polishing process can be performed to remove the conductive material outside the first contact hole 306.

[0070] Exemplarily, during, before or after forming the first contact hole 306, a first portion of the second contact hole 307 may be formed, the first portion of the second contact hole 307 is located above the source 304, and the etching of the first portion of the second contact hole 307 stops at the metal silicide layer. The first portion of the second contact hole 307 is used to lead out the source 304 so as to electrically connect the source 304 to the bit line.

[0071] Then, if Figure 3C As shown, a second portion of the first interlayer dielectric layer 305 is deposited, and the second portion of the first interlayer dielectric layer 305 is used to form a plurality of discrete fin structures. Exemplarily, each two adjacent fin structures are isolated by a trench formed by etching, and the bottom of the trench exposes the first portion of the first interlayer dielectric layer, so as to expose the top of the first contact hole 306 and the first portion of the second contact hole 307.

[0072] Exemplarily, a silicon oxide layer with a thickness of about 12k angstroms to 13k angstroms is first deposited on the first part of the first interlayer dielectric layer 305, and then the silicon oxide layer is polished to 5000 angstroms to 5500 angstroms using a planarization process, and its upper surface is flattened, thereby forming the second part of the first interlayer dielectric layer 305. Finally, the second part of the first interlayer dielectric layer 305 is photolithographically and etched to form a plurality of discrete fin structures, that is, each adjacent two fin structures are isolated by the grooves formed by etching. The number of fin structures can be set according to the demand for the capacitance value of the ferroelectric capacitor.

[0073] Considering that if the top and bottom of the fin structure are at right angles, the top and bottom of the ferroelectric capacitor formed subsequently will also be at right angles, thereby causing the ferroelectric capacitor to have contact problems, prone to tip discharge, and the capacitor structure to be easily broken down, causing the breakdown voltage of the entire ferroelectric capacitor to decrease, ultimately reducing the reliability and life of the capacitor. For this reason, the top and bottom of the fin structure of the embodiment of the present invention are in an arc shape, so the top and bottom of each ferroelectric capacitor unit are also in an arc shape, thereby being able to increase the contact area, avoid tip discharge, improve the breakdown voltage on both sides of the top and bottom, and ultimately improve the reliability and life of the ferroelectric capacitor.

[0074] Specifically, first refer to Figure 3C , a plurality of photoresist patterns 308 arranged at intervals are formed on the first interlayer dielectric layer 305, and the photoresist patterns correspond to the positions of the fin structures. Specifically, the photoresist layer can be spin-coated, and the photoresist layer is exposed and developed, and the photoresist layer corresponding to the groove position is dissolved and removed in a developer, and a plurality of photoresist patterns 308 arranged at intervals remain.

[0075] Next, the first interlayer dielectric layer 305 is dry-etched using the photoresist pattern 308 as a mask to form grooves between every two adjacent photoresist patterns 308 . The grooves are used to divide the fin structure.

[0076] Exemplarily, in order to form an arc-shaped fin structure, process parameters such as chamber pressure, RF power (RF_Upper / RF_Lower), plasma gas Ar, and main etching gas can be adjusted during the etching process. Among them, after adding radio frequency to the plasma argon gas, it will bombard the etching gas to produce ionization, thereby etching the required structure. The main etching gas includes fluorocarbon gases such as C4F6, CH2F2, and CF4, which can produce a polymer layer during the etching process to obtain the required fin structure morphology. The polymer layer is a by-product produced by the etching gas bombarding the photoresist pattern during the etching process. The polymer layer produced at the same time will also cover the top and side walls of the photoresist pattern and the side walls of the groove, thereby preventing excessive etching.

[0077] In one embodiment, the first interlayer dielectric layer 305 can be dry-etched in two stages. First, in the first stage, the chamber pressure and RF power are set appropriately, C4F6 and CH2F2 are selected as the main etching gas, argon is used as the plasma carrier gas, and an appropriate flow ratio is set, such as Figure 3DAs shown, as the etching time increases, grooves are gradually formed in the area not covered by the photoresist pattern 308. Since the polymer layer is deposited on the top and sidewalls of the photoresist layer and the sidewalls of the groove during the etching process, the bottom of the groove is etched from a right angle to an arc shape, and the photoresist pattern 308 is gradually consumed from the top and then from the two shoulders, gradually making the top of the photoresist pattern 308 also become an arc shape.

[0078] Then, in the second stage, Figure 3E As shown, the main etching gas is adjusted to C4F6 and CF4, and the chamber pressure, RF power, gas flow and other parameters are adjusted again to continue etching the groove. In the second stage, the parameters are adjusted so that the polymer produced by etching is less than the polymer produced by etching in the first stage, and the photoresist pattern is further consumed from the top and both sides until a very small amount of photoresist remains on the top. At this time, the top of the fin structure under the photoresist pattern is also gradually etched into an arc shape as the photoresist is reduced. In the second stage, the bottom of the groove is further modified by etching, becoming smoother, and finally forming a shape as shown in FIG. Figure 3F The fin structure shown.

[0079] Exemplarily, after the etching is completed, the polymer layer generated during the etching process needs to be removed. Exemplarily, the main etching gas is removed in the etching chamber, and oxygen is used for plasma treatment to remove the possible remaining polymer layer and the very little photoresist on the top of the fin structure. In addition, oxygen can also be added as needed during the etching process to adjust the thickness of the polymer layer.

[0080] After forming the fin structure, Figure 3G As shown, a ferroelectric capacitor 309 is formed on the fin structure, and the ferroelectric capacitor 309 includes a first plate 309A, a second plate 309C and a ferroelectric film 309B between the first plate 309A and the second plate 309C, and the first plate 309A is electrically connected to the switch transistor. Since the ferroelectric capacitor is formed on the first interlayer dielectric layer 305 with the fin structure, its shape is basically consistent with the shape of the first interlayer dielectric layer 305 surface, that is, the ferroelectric capacitor is composed of a plurality of bent capacitor units. The area of ​​the ferroelectric capacitor can be increased by increasing the number of fin structures according to actual needs, thereby solving the problem of insufficient capacitance when the ferroelectric memory cell is reduced, and improving the safety performance of the memory cell.

[0081] Furthermore, by setting the top and bottom of the fin structure to be arc-shaped, the contact area between the ferroelectric film 309B and the electrode on both sides of the top and bottom can be further increased, thereby solving the problem of tip discharge on both sides of the top and bottom of the ordinary right-angle capacitor structure that reduces the breakdown voltage, and improving the breakdown voltage of the entire ferroelectric capacitor 309, thereby improving the reliability and service life of the ferroelectric capacitor and improving the safety performance of the storage unit.

[0082] Exemplarily, a deposition process is first used to form a first electrode 309A on the first interlayer dielectric layer 305. Exemplarily, the material of the first electrode includes TiN, the thickness of the first electrode is about 45nm-55nm, specifically 50nm, and the deposition process of the first electrode can be an atomic layer deposition process.

[0083] Next, a ferroelectric film 309B is formed on the first electrode 309A. Exemplarily, the material of the ferroelectric film 309B includes hafnium oxide (HZO), which can be specifically hafnium oxide doped with zirconium, wherein the doping ratio of zirconium, hafnium and oxygen is about 0.5 / 0.5 / 2. The HZO ferroelectric film has a spontaneous polarization characteristic, and can undergo spontaneous polarization reversal under the action of an external electric field applied by the upper and lower electrodes. At the same time, the capacitance and current of the ferroelectric film 309B will also change with the change of the polarization state. After removing the external electric field, a certain polarization intensity, namely the ±Pr state, can still be retained in the ferroelectric film 309B, which can be used to represent "1" and "0" in a binary digital system according to its direction, thereby realizing data storage capability with non-volatile characteristics. Exemplarily, the thickness of the ferroelectric film 309B is about 6nm-10nm, and the deposition process of the ferroelectric film 309B can be an atomic layer deposition process.

[0084] Afterwards, a second electrode 309C is formed on the ferroelectric film 309B. Exemplarily, the material of the second electrode 309C includes TiN, the thickness of the second electrode 309C is about 45nm-55nm, specifically 50nm, and the deposition process of the second electrode can be an atomic layer deposition process. Finally, a furnace annealing process is performed to activate the ferroelectricity of the ferroelectric film 309B.

[0085] Exemplarily, after forming the ferroelectric capacitor 309, a cap layer 310, such as a SiN layer, may be formed to cover the ferroelectric capacitor. Afterwards, the ferroelectric capacitor 309 is patterned to remove the first plate 309A, the second plate 309C and the ferroelectric film 309B outside the fin structure, and expose the first portion of the second contact hole below, so as to facilitate the extraction of the source 304 of the switch transistor.

[0086] Then, if Figure 3HAs shown, a second interlayer dielectric layer 311 is formed to cover the ferroelectric capacitor 309, and the upper surface of the second interlayer dielectric layer 311 is higher than the top of the ferroelectric capacitor 309. The material of the second interlayer dielectric layer 311 and the material of the first interlayer dielectric layer 305 can be the same or different.

[0087] Afterwards, if Fig. 3I As shown, a third contact hole 312 is formed through the second interlayer dielectric layer 311, and the third contact hole 312 is connected to the second electrode plate 309C. Specifically, the bottom of the third contact hole 312 is connected to the second electrode plate, and the top is connected to the plate line (PL). Afterwards, a second partial second contact hole 307 can also be formed through the second interlayer dielectric layer 311, and the second partial second contact hole 307 is connected to the first partial second contact hole 307 to form a complete second contact hole 307. The second contact hole 307 is connected to the source 304. Specifically, the bottom of the second contact hole 307 is connected to the source 304, and the top is connected to the bit line (BL).

[0088] In such Figure 1 In the ferroelectric memory shown, since the ferroelectric capacitor is a planar structure and is parallel to the metal layer of the plate line or the bit line, the bit line and the plate line need to select a fixed metal wiring layer to reduce the parasitic capacitance effect of the adjacent metal layer on the ferroelectric capacitor, and the process flexibility is poor. In contrast, the plate of the ferroelectric capacitor of the embodiment of the present invention is an uneven structure, and the parasitic capacitance and interconnection resistance with the metal layer are reduced, so the bit line and the plate line can freely select a suitable metal layer without generating additional parasitic capacitance.

[0089] Figure 4 and Figure 5 The circuit netlist and layout of the ferroelectric memory of the embodiment of the present invention are respectively shown. Similar to the working mode of the conventional DRAM 1T1C unit, the plate line (PL) and the word line (WL) are routed in the Y direction, and the bit line (BL) is routed in the X direction. The ferroelectric capacitor is selected by controlling the word line (WL). The bit line and the plate line apply positive and negative voltages to the two plates of the ferroelectric capacitor respectively. Since the ferroelectric film in the middle of the ferroelectric capacitor has ferroelectric properties, different iron domains (i.e., polarization occurs) will be formed under the action of positive and negative electric fields. Such iron domains will not disappear with the removal of the external electric field, so that the capacitor structure can store different charges and realize the storage function. The ferroelectric memory according to the embodiment of the present invention can ensure that the ferroelectric capacitor has sufficient area while greatly reducing the storage unit structure. Figure 5 In the memory cell array layout shown, the spacing in both the X and Y directions can be reduced synchronously with the technology node.

[0090] At this point, the process steps implemented in the manufacturing method of a ferroelectric memory according to an embodiment of the present invention have been completed. It can be understood that the manufacturing method of a ferroelectric memory according to an embodiment of the present invention not only includes the above steps, but may also include other necessary steps before, during or after the above steps, which are all included in the scope of the manufacturing method of the embodiment of the present invention.

[0091] According to the manufacturing method of the ferroelectric memory provided by the present invention, the longitudinal capacitance and the planar capacitance are increased by forming a ferroelectric capacitor on the fin structure without increasing the area of ​​the storage unit of the ferroelectric memory. Figure 1 The planar ferroelectric capacitor of the embodiment of the present invention can increase the capacitor area by increasing the number of fin structures according to actual needs, thereby optimizing the unit storage performance. In addition, the ferroelectric capacitor has a simple process, low cost, and is well compatible with the standard CMOS manufacturing process.

[0092] like Fig. 3I As shown, an embodiment of the present invention further provides a ferroelectric memory. Exemplarily, the ferroelectric memory can be manufactured by the manufacturing method of the ferroelectric memory as described above. Specifically, the ferroelectric memory of the embodiment of the present invention includes:

[0093] A semiconductor substrate 301; a switching transistor, the switching transistor comprising a gate 302 located on the semiconductor substrate 301, and a source 304 and a drain 303 located in the semiconductor substrate 301; a first interlayer dielectric layer 305, covering the switching transistor, the upper surface of the first interlayer dielectric layer 305 having a plurality of discrete fin structures; a ferroelectric capacitor 309, formed on the fin structure, the ferroelectric capacitor 309 comprising a first plate 309A, a second plate 309C and a ferroelectric film 309B located between the first plate 309A and the second plate 309C, the first plate 309A being electrically connected to the switching transistor.

[0094] In some embodiments, the top and bottom of the fin structure are arc-shaped, so the top and bottom of the capacitor unit above each fin structure are also arc-shaped, thereby increasing the contact area between the ferroelectric film 309B and the first electrode 309A and the second electrode 309C at the corner, avoiding tip discharge, and increasing the breakdown voltage on both sides of the top and bottom, ultimately improving the reliability and life of the ferroelectric capacitor 309.

[0095] In some embodiments, the ferroelectric memory further includes a first contact hole 306, which penetrates the first interlayer dielectric layer 305 and respectively connects the first electrode 309A and the drain 303 of the switch transistor to achieve electrical connection between the switch transistor and the ferroelectric capacitor 309. The gate 302 of the switch transistor is a word line, and the ferroelectric capacitor can be selected by controlling the word line (WL).

[0096] The ferroelectric capacitor 309 is also covered with a second interlayer dielectric layer 311. The third contact hole 312 runs through the second interlayer dielectric layer 311 and is connected to the second pole plate 309C. Specifically, one end of the third contact hole 312 is connected to the second pole plate 309C, and the other end is connected to the plate line. The second contact hole 307 runs through the first interlayer dielectric layer 305 and the second interlayer dielectric layer 311, and is connected to the source electrode 304. Specifically, one end of the second contact hole 307 is connected to the source electrode 304, and the other end is connected to the bit line. The bit line and the plate line apply positive and negative direction voltages to the two pole plates of the ferroelectric capacitor respectively. Since the ferroelectric film in the middle of the ferroelectric capacitor has ferroelectric properties, different iron domains (i.e., polarization) will be formed under the action of the positive and negative electric fields, and this iron domain will not disappear with the cancellation of the external electric field, so that the capacitor structure can store different charges and realize the storage function.

[0097] Exemplarily, a cap layer 310 is further formed on the upper surface of the ferroelectric capacitor 309 to isolate the second electrode 309C from the second interlayer dielectric layer 311 .

[0098] The ferroelectric memory and manufacturing method of the embodiment of the present invention increase the longitudinal capacitance and planar capacitance by forming a ferroelectric capacitor on the fin structure without increasing the area of ​​the switch transistor. The ferroelectric memory includes at least one 1T1C storage unit, each of which includes a switch transistor and a ferroelectric capacitor. As the key size of the integrated circuit decreases, the size of the switch transistor decreases, and the area of ​​the ferroelectric capacitor decreases in the same proportion, and the ferroelectric capacitor becomes smaller accordingly, resulting in read and write errors in the ferroelectric memory. In order to overcome read and write errors, the capacitance value of the ferroelectric capacitor must be increased. At this time, for Figure 1 If the capacitance value of a planar ferroelectric capacitor structure is to be increased, the capacitor area in the horizontal direction must be increased, which ultimately results in a larger storage unit area, reduced integration, and increased costs. However, the embodiment of the present invention forms a fin structure by making grooves in the vertical direction, thereby forming a fin-type ferroelectric capacitor structure, so that the ferroelectric capacitor extends in both the horizontal and vertical directions. While increasing the capacitance value, the horizontal area of ​​the ferroelectric capacitor will not be increased, and therefore the storage unit area will not be increased. Moreover, relative to Figure 1 The planar ferroelectric capacitor of the embodiment of the present invention can also increase the number of fin structures to increase the capacitance area according to actual needs, thereby optimizing the unit storage performance. For more specific details of the ferroelectric memory, please refer to the relevant description of its manufacturing method, which will not be repeated here.

[0099] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A ferroelectric memory, characterized in that: The ferroelectric memory comprises: Semiconductor substrate; a switching transistor, the switching transistor comprising a gate located on the semiconductor substrate, and a source and a drain located in the semiconductor substrate; A first interlayer dielectric layer covers the switch transistor, wherein the upper surface of the first interlayer dielectric layer has a plurality of discrete fin structures; A ferroelectric capacitor is formed on the fin structure, and includes a first plate, a second plate, and a ferroelectric film located between the first plate and the second plate, wherein the first plate is electrically connected to the switch transistor.

2. The ferroelectric memory according to claim 1, wherein: The top and bottom of the fin structure are in arc shape.

3. The ferroelectric memory according to claim 1, wherein: The device also includes a first contact hole, wherein the first contact hole penetrates the first interlayer dielectric layer, and the first contact hole connects the first electrode plate and the drain of the switch transistor.

4. The ferroelectric memory according to claim 1, wherein: The invention also includes a cap layer formed on the upper surface of the ferroelectric capacitor.

5. The ferroelectric memory according to claim 1, wherein: Also includes: a second interlayer dielectric layer, wherein the second interlayer dielectric layer covers the ferroelectric capacitor; a second contact hole, wherein the second contact hole penetrates the first interlayer dielectric layer and the second interlayer dielectric layer and is connected to the source electrode; A third contact hole penetrates the second interlayer dielectric layer and is connected to the second electrode plate.

6. A method for manufacturing a ferroelectric memory, characterized in that: The method comprises: providing a semiconductor substrate; forming a gate of a switching transistor on the semiconductor substrate, and forming a source and a drain of the switching transistor in the semiconductor substrate; forming a first interlayer dielectric layer covering the semiconductor substrate and the switch transistor, and forming a plurality of discrete fin structures on an upper surface of the first interlayer dielectric layer; A ferroelectric capacitor is formed on the fin structure. The ferroelectric capacitor includes a first plate, a second plate, and a ferroelectric film located between the first plate and the second plate. The first plate is electrically connected to the switch transistor.

7. The manufacturing method according to claim 6, characterized in that: The forming of a plurality of fin structures on the surface of the first interlayer dielectric layer comprises: forming a plurality of photoresist patterns arranged at intervals on the first interlayer dielectric layer; Using the photoresist pattern as a mask, dry-etching the first interlayer dielectric layer to form grooves between every two adjacent photoresist patterns, wherein the grooves are used to divide the fin structure; During the dry etching process, a polymer layer is gradually formed on the sidewalls of the trench, so that the bottom of the trench is in an arc shape. Furthermore, during the dry etching process, the top of the photoresist pattern gradually changes into an arc shape, so that the top of the fin structure is in an arc shape.

8. The manufacturing method according to claim 7, characterized in that: After forming the trench, the method further comprises: The polymer layer is removed.

9. The manufacturing method according to claim 6, characterized in that: The forming of a first interlayer dielectric layer covering the switch transistor comprises: Forming a first portion of the first interlayer dielectric layer covering the switch transistor, and forming a second portion of the first interlayer dielectric layer above the first portion of the first interlayer dielectric layer, wherein the second portion of the first interlayer dielectric layer is used to form the fin structure; After forming the first portion of the first interlayer dielectric layer and before forming the second portion of the first interlayer dielectric layer, the method further includes: forming a first contact hole penetrating the first interlayer dielectric layer, the first contact hole connecting the first electrode plate and the drain of the switching transistor.

10. The manufacturing method according to claim 6, characterized in that: After forming the ferroelectric capacitor, the method further includes: forming a second interlayer dielectric layer covering the ferroelectric capacitor; forming a second contact hole penetrating the second interlayer dielectric layer and the first interlayer dielectric layer, wherein the second contact hole is connected to the source electrode; A third contact hole is formed penetrating the second interlayer dielectric layer, wherein the third contact hole is connected to the second electrode plate.

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