High-capacity ferroelectric capacitor, storage array and preparation method of high-capacity ferroelectric capacitor

Abstract

The invention discloses a preparation method of a high-capacity ferroelectric capacitor and a high-capacity ferroelectric capacitor storage array. The high-capacity ferroelectric capacitor comprises a metal via hole and a cavity area formed in the tail end of the metal via hole; a barrier layer is laid on the inner wall of the cavity area; capacitance materials are sequentially deposited on the barrier layer and the inner wall of the metal through hole. And the top layers of the copper pad windings are in contact with the metal through holes. Arranging a semiconductor connected with a copper pad winding on the wafer, and preparing a capacitor hole at the tail end of the winding; and etching the copper in the last-layer copper pad of the winding, and reserving the external barrier layer. Under the condition that the depth-to-width ratio of a capacitor preparation deep hole is not increased, the area of the ferroelectric capacitor is enlarged by 15-50%, the problem that in the prior art, due to the fact that a landing pad cavity is caused by a reaction source, a circuit is possibly broken is solved, and the structural state that the capacitor exerts efficiency is perfected.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a large-capacity ferroelectric capacitor, a storage array and a preparation method thereof. Background Art

[0002] There are three main structures of traditional ferroelectric memory, namely 2T2C, 1T2C and 1T1C. Each bit of 2T2C has two opposite capacitors as reference, which has good reliability, but occupies too much area and has low storage density; 1T1C structure has high integration density, but poor reliability; 1T2C structure has a compromise between density and reliability. Due to the limitation of the materials used (PZT perovskite material), traditional ferroelectric memory can only make planar capacitors, and its chip capacity is mostly in the Kb level. By using HfO2 (hafnium oxide) based ferroelectric materials in ferroelectric memory, the capacity of ferroelectric memory has finally broken through to the Mb or even Gb level. However, whether it is traditional ferroelectric memory or hafnium oxide based new ferroelectric memory, its core development direction is to increase its ferroelectric capacitor area and ferroelectric capacitor density. The present invention is a new ferroelectric memory based on hafnium oxide based ferroelectric material.

[0003] Based on the main structure combining complementary metal oxide semiconductor structure and ferroelectric capacitor, in order to maximize the capacitor area and ensure the storage density, it is necessary to prepare a deep hole structure with a high aspect ratio for subsequent filling of the ferroelectric capacitor film. We know that the higher the aspect ratio, the more difficult the process preparation is, and the worse the stability of the structure. In addition, the higher the aspect ratio of the hole, the worse the step coverage is when the barrier layer is deposited, especially at the bottom of the deep hole, where there is no barrier layer in some areas. This causes the copper pad of the lower layer to be damaged by the source gas when the lower electrode of the capacitor is deposited, thereby causing the copper pad to leak and affecting the direct connection between the semiconductor and the ferroelectric capacitor. Summary of the invention

[0004] The purpose of this section is to summarize some aspects of the embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the abstract of the specification and the title of the invention of this application to avoid blurring the purpose of this section, the abstract of the specification and the title of the invention, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0005] In view of the fact that the area of ​​the memory capacitor existing in the above and / or prior art is the core development direction for enhancing its performance, the present invention is proposed.

[0006] Therefore, the technical problem to be solved by the present invention is to obtain a larger capacitor area without increasing the aspect ratio of the capacitor structure hole.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions: A large-capacity ferroelectric capacitor, comprising a metal via and a hollow area opened at the end thereof;

[0008] The inner wall of the cavity area is provided with a barrier layer;

[0009] Capacitor materials are deposited in sequence on the barrier layer and the inner wall of the metal via.

[0010] As a preferred solution of the large-capacity ferroelectric capacitor described in the present invention, wherein: the capacitor material includes a lower electrode layer, a ferroelectric film layer, and an upper electrode layer;

[0011] The outer side of the barrier layer is in contact with a lower copper pad;

[0012] The copper pad has at least two layers;

[0013] The overall height of each layer of copper pad is 140 to 300 nm, and is composed of holes and grooves, with a height ratio of holes to grooves of 1:2.

[0014] As a preferred solution of the large-capacity ferroelectric capacitor described in the present invention, the barrier layer is the outer wall of the etched copper pad.

[0015] The beneficial effects of the present invention are as follows: a winding with etched internal copper material is added as a cavity area, thereby increasing the capacitance area without increasing the deposition difficulty caused by the aspect ratio.

[0016] Since a single capacitor needs to exist on a complete wafer after semiconductor fabrication.

[0017] Therefore, the technical problem to be solved by the present invention is to enable a single capacitor to form a structured storage array.

[0018] In order to solve the above technical problems, the present invention also provides the following technical solutions: a storage array, comprising the large-capacity ferroelectric capacitor and field effect transistor, which are uniformly prepared on a substrate;

[0019] Copper pad windings are deposited and etched in sequence at the source and drain of the field effect tube;

[0020] The top layers of the copper pad windings all contact the metal vias.

[0021] As a preferred solution of the storage array described in the present invention, the copper pad winding is sequentially deposited and etched in the peripheral circuit area on the substrate, and a guide copper pad flush with the height of the metal via is deposited on the top layer.

[0022] The beneficial effects of the present invention are as follows: the structural state in which the capacitor can exert its effectiveness is improved.

[0023] Considering that the higher the aspect ratio of the hole, the worse the step coverage is when the barrier layer is deposited, especially at the bottom of the deep hole, some areas have no barrier layer. This causes the copper pad of the lower layer to be damaged by the source gas when the lower electrode of the capacitor is deposited, thereby causing the copper pad to leak and affecting the direct connection between the semiconductor and the ferroelectric capacitor.

[0024] Therefore, the technical problem to be solved by the present invention is to solve the problem of leakage of the lower copper pad caused by insufficient coverage of the barrier layer.

[0025] To solve the above technical problems, the present invention also provides the following technical solutions: a method for preparing a large-capacity ferroelectric capacitor storage array, comprising the above-mentioned storage array, and, opening a semiconductor connected to a copper pad winding on a wafer, and preparing a capacitor hole at the end of the winding;

[0026] Etch the Cu inside the last copper pad of the winding and keep the external barrier layer.

[0027] As a preferred solution of the method for preparing a large-capacity ferroelectric capacitor storage array of the present invention, wherein: the barrier layer forms a hollow region and is placed in the capacitor hole;

[0028] Capacitor materials are deposited in sequence in the capacitor holes to form a ferroelectric capacitor storage array.

[0029] As a preferred solution of the method for preparing a large-capacity ferroelectric capacitor storage array of the present invention, wherein: the semiconductor preparation adopts a 14-45nm process node;

[0030] A copper pad winding formed by a hole-groove structure is respectively prepared on the source and drain of the semiconductor;

[0031] The height of each layer of the copper pad winding is 140nm-300nm, and is composed of holes and grooves with a height ratio of 1:2.

[0032] As a preferred solution of the method for preparing a large-capacity ferroelectric capacitor storage array of the present invention, wherein: the hole in the copper pad winding has a height of 40 to 100 nm;

[0033] The groove in the copper pad winding has a height of 100 to 200 nm.

[0034] As a preferred solution of the method for preparing a large-capacity ferroelectric capacitor storage array of the present invention, wherein: the hole in the copper pad winding has a height of 400nm;

[0035] The groove in the copper pad winding has a height of 600 nm.

[0036] As a preferred solution of the method for preparing a large-capacity ferroelectric capacitor storage array of the present invention, a top metal is deposited at the end of the copper pad winding, and the capacitor hole, ie, the metal via and the cavity area, is etched therefrom.

[0037] As a preferred solution of the method for preparing a large-capacity ferroelectric capacitor storage array of the present invention, wherein: the guide copper pad winding is made by a tungsten chemical vapor deposition process;

[0038] The other copper pad windings are all made by dual damascene process, that is, copper-containing grooves are made after multiple photolithography and dry etching.

[0039] As a preferred solution of the method for preparing the large-capacity ferroelectric capacitor storage array of the present invention, wherein: the capacitor hole has a hole diameter of 100-200nm and a hole depth of 1500nm-2000nm;

[0040] A lower electrode layer, a ferroelectric thin film layer, and an upper electrode layer are deposited inside the capacitor hole;

[0041] The thickness of the lower electrode layer is 10 to 15 nm;

[0042] The thickness of the ferroelectric thin film layer is 8 to 10 nm;

[0043] The thickness of the upper electrode layer is 10-15 nm.

[0044] As a preferred solution of the method for preparing a large-capacity ferroelectric capacitor storage array of the present invention, wherein: the lower electrode layer, the ferroelectric thin film layer, and the upper electrode layer are all formed by atomic layer deposition and by maskless etching;

[0045] The lower electrode layer is composed of titanium nitride;

[0046] The ferroelectric thin film layer is composed of zirconium-containing hafnium oxide;

[0047] The upper electrode layer is composed of titanium nitride.

[0048] As a preferred solution of the method for preparing the large-capacity ferroelectric capacitor storage array of the present invention, wherein: the capacitor holes containing the capacitor material are subjected to a high-temperature annealing process, and the heating temperature is 500-600° C.;

[0049] Depositing 100-200 nm of titanium or aluminum onto the surface of the upper electrode layer, and dry-etching a plate line layer;

[0050] Use polyimide post insulation layer to make PI vias for RDL Pad external connection.

[0051] The beneficial effects of the present invention are as follows: without increasing the aspect ratio of the deep hole for capacitor preparation, the area of ​​the ferroelectric capacitor is expanded by 15-50%, and the circuit breaking problem that may be caused by the landing pad void caused by the reaction source in the existing process is solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. Among them:

[0053] Figure 1 A schematic diagram of the structure of a prior art large-capacity ferroelectric capacitor according to an embodiment of the present invention;

[0054] Figure 2 A schematic diagram of the structure of a large-capacity ferroelectric capacitor and a schematic diagram of capacitance area calculation according to an embodiment of the present invention;

[0055] Figure 3 A schematic structural diagram of a semiconductor portion of a memory array according to an embodiment of the present invention;

[0056] Figure 4 A schematic diagram of the structure of a storage array copper pad wiring according to an embodiment of the present invention;

[0057] Figure 5 A schematic structural diagram of a top metal of a large-capacity ferroelectric capacitor according to an embodiment of the present invention;

[0058] Figure 6 A schematic diagram of the initial state structure of a wafer in a method for preparing a large-capacity ferroelectric capacitor storage array according to an embodiment of the present invention;

[0059] Figure 7 A schematic diagram of a state after etching away Cu in a copper pad (Cu Pad) in a method for preparing a large-capacity ferroelectric capacitor storage array according to an embodiment of the present invention;

[0060] Figure 8 A schematic diagram of the structure of depositing a lower electrode in a method for preparing a large-capacity ferroelectric capacitor storage array according to an embodiment of the present invention;

[0061] Fig. 9 A schematic structural diagram of a ferroelectric thin film deposited in a method for preparing a large-capacity ferroelectric capacitor storage array according to an embodiment of the present invention;

[0062] Fig.10A schematic diagram of the structure of depositing an upper electrode in a method for preparing a large-capacity ferroelectric capacitor storage array according to an embodiment of the present invention;

[0063] Fig.11 A schematic diagram of a state of preparing a plate line layer in a method for preparing a large-capacity ferroelectric capacitor storage array according to an embodiment of the present invention;

[0064] Fig.12 A schematic diagram of the structure of a method for preparing a large-capacity ferroelectric capacitor storage array according to an embodiment of the present invention after capacitor preparation is completed;

[0065] Fig.13 A schematic structural diagram of a method for preparing a large-capacity ferroelectric capacitor storage array according to an embodiment of the present invention;

[0066] Fig.14 A schematic diagram of an initial hole engraving structure for further enlarging the capacitor area in a method for preparing a large-capacity ferroelectric capacitor storage array according to an embodiment of the present invention;

[0067] Fig.15 A schematic diagram of the structure after etching away the Cu in the copper pad when further expanding the capacitor area in the method for preparing a large-capacity ferroelectric capacitor storage array according to an embodiment of the present invention;

[0068] Fig.16 A schematic diagram of a complete capacitor state after the capacitor area is further enlarged in the method for preparing a large-capacity ferroelectric capacitor storage array according to an embodiment of the present invention;

[0069] Fig.17 A schematic diagram of the dual Damascene process flow mentioned in a method for preparing a large-capacity ferroelectric capacitor storage array according to an embodiment of the present invention.

[0070] In the figure: metal via 100; void area 100a; barrier layer 100a-1; lower electrode 200; ferroelectric thin film layer 300; upper electrode 400; field effect transistor 500; copper pad winding Cu Pads; copper pad Cu Pad; guide copper pad G-Cu Pad; top layer of copper pad winding Cu Pads; top metal Top Metal; hole part; groove part; semiconductor; tungsten chemical vapor deposition process; titanium nitride TiN; zirconium-containing hafnium oxide Hf 0.5 Zr 0.5 O2; PI; RDL Pad; barrier layer. DETAILED DESCRIPTION

[0071] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0072] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0073] Secondly, the present invention is described in detail with reference to schematic diagrams. When describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0074] Furthermore, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0075] Example 1

[0076] Reference Figures 1-2 This embodiment provides a large-capacity ferroelectric capacitor, including a metal via 100 and a hollow area opened at the end thereof. The metal via 100 is a cylindrical hole punched in an array area by yellow light + dry etching, which is used to make an embedded ferroelectric capacitor. The aperture of the entire hole affects the capacitance density. The larger the aperture, the lower the capacitance hole density; the smaller the aperture, the greater the aspect ratio, and the higher the difficulty of process implementation;

[0077] The void area is the topmost part of the copper winding below, that is, the copper pad Cu Pad in contact with the metal via 100. After removing the internal copper material, the remaining tantalum nitride part for wrapping effect is called the void area.

[0078] The inner wall of the cavity area is coated with a barrier layer, which is actually the tantalum nitride part, that is, the residue after removing Cu from the copper pad.

[0079] Capacitor materials are deposited on the barrier layer and the inner wall of the metal via 100 in sequence. The capacitor materials are the basic components for forming ferroelectric capacitors. Depositing and etching the capacitor materials are also necessary steps in the process.

[0080] And from Figure 1 It can be seen that this solution for expanding the capacitance area also meets the variable requirements of the calculation formula in terms of logic and structural characteristics, that is, calculating the capacitance area, S = T*L(R+r)+π*r2.

[0081] Example 2

[0082] Reference Figures 1 to 4 , which is the second embodiment of the present invention, is based on the previous embodiment, and is different from the previous embodiment in that: the capacitor material includes a lower electrode layer 200, a ferroelectric thin film layer 300, and an upper electrode layer 400; the deposition material is deposited and etched layer by layer to form a complete capacitor structure, thereby achieving the effect of storing and transferring electrical signals on the wafer.

[0083] Furthermore, the barrier layer contacts the lower copper pad Cu Pad on the outside, and the barrier layer here is the original top copper pad Cu Pad. After the Cu is hollowed out, this layer of copper pad Cu Pad becomes the barrier layer, so naturally the barrier layer contacts the original second copper pad Cu Pad below.

[0084] There are at least two layers of copper pads Cu Pad. The copper pads Cu Pads in the storage array area are stacked one by one from the third layer, and there is no winding problem. The reason for designing so many layers of metal windings is to meet the winding requirements of the peripheral circuit area. Therefore, starting from the third layer of copper pads Cu Pad, the number of layers will not affect signal transmission. Therefore, in the complete capacitor structure, the copper pads Cu Pads below must have at least two layers, that is, the entire copper pad winding Cu Pads must have at least three layers, leaving the top layer as a barrier layer;

[0085] In detail, in order to reduce the difficulty of the process, the overall height of each layer of copper pad Cu Pad is 140-300nm, and is composed of holes and grooves. The height ratio of holes to grooves is 1:2. This hole-groove ratio can ensure that the etching process of each layer of copper pad Cu Pad will not affect the lower layer of copper pad Cu Pad, and the etching depth can also be completed efficiently in half.

[0086] It should be noted that the blank space between the semiconductor part and the top copper pad Cu Pad in the accompanying drawings is to illustrate that the middle part on the copper pad winding Cu Pads is skipped here and the top copper pad Cu Pad is directly displayed to facilitate understanding of the technical solution.

[0087] Example 3

[0088] Reference Figures 1 to 7, which is the third embodiment of the present invention, and this embodiment provides a storage array. This embodiment is based on the previous embodiment, and is different from the previous embodiment in that: the field effect tube is uniformly prepared on the substrate; the field effect tube 500 is actually a component unit of the semiconductor part, and it can also be understood that the field effect tube 500 is a semiconductor. The semiconductor here refers to CMOS, that is, complementary metal oxide, and its low power consumption and responsiveness are required by the solution. As the first step of wafer preparation, the source and drain of the field effect tube are sequentially deposited and etched with copper pad windings Cu Pads. The copper pad windings Cu Pads provide a transmission path for electronic signals. The copper pad windings Cu Pads also need to be deposited and etched to form a complete and effective "roadbed";

[0089] In detail, the top layers of the copper pad windings Cu Pads all contact the metal vias 100, that is, the basic structure of the ferroelectric capacitor mentioned above. There must be a layer of copper pads Cu Pads with the internal copper material etched away to exist as a capacitor barrier layer.

[0090] In detail, from the structure of ferroelectric memory chip, ferroelectric capacitors are connected to semiconductors through copper pads Cu Pad landing pads. In the array memory cell array area, the lower copper pad Cu Pad is mainly used for connection transition and has no winding function.

[0091] The copper pad Cu Pad etching in the present invention uses plasma + gas in a manner similar to dry etching, generally a chlorine-containing gas. The present invention uses titanium chloride TiCl4 to etch away all the copper pad Cu Pad of the landing pad, so that only tantalum nitride is retained as a barrier layer. In this way, the entire landing pad copper pad Cu Pad area forms a ferroelectric capacitor cavity area, which is the above-mentioned cavity area.

[0092] Example 4

[0093] Reference Figures 1 to 7 , which is the fourth embodiment of the present invention, and this embodiment provides a method for preparing a large-capacity ferroelectric capacitor storage array. This embodiment is based on the previous embodiment, and is different from the previous embodiment in that:

[0094] A semiconductor connected to a copper pad winding Cu Pads is opened on the wafer, and a capacitor hole is prepared at the end of the winding;

[0095] The Cu inside the last copper pad of the winding is etched to retain the external barrier layer.

[0096] The barrier layer forms a cavity region which is placed in the capacitor hole;

[0097] Capacitor materials are deposited in sequence in the capacitor holes to form a ferroelectric capacitor storage array.

[0098] Example 5

[0099] Reference Figures 1 to 7 , which is the fifth embodiment of the present invention, is based on the previous embodiment, and is different from the previous embodiment in that: the semiconductor is prepared using a 14-45 nm process node;

[0100] Copper pad windings Cu Pads formed by hole-groove structures are respectively prepared on the source and drain of the semiconductor;

[0101] Each layer of copper pad winding Cu Pads has a height of 140nm to 300nm and is composed of holes and grooves with a height ratio of 1:2.

[0102] Example 6

[0103] Reference Figures 1 to 7 and Fig.17 , which is the sixth embodiment of the present invention, is based on the previous embodiment, and is different from the previous embodiment in that: a top metal is deposited at the end of the copper pad winding Cu Pads, and a capacitor hole, namely a metal via 100 and a cavity area 100a, is etched thereon. The peripheral circuit area on the substrate is sequentially deposited and etched with copper pad windings Cu Pads, and a guide copper pad G-Cu Pad is deposited on the top layer that is flush with the metal via 100.

[0104] The holes in the top layer of the copper pad winding Cu Pads have a height of 40 to 10 nm;

[0105] The groove in the top layer of the copper pad winding Cu Pads has a height of 100 to 200nm. The specific height of this part is determined by the height of the subsequent top metal. The top metal in the array storage array area and the peri peripheral circuit area is not treated uniformly. The top metal in the peri peripheral circuit, that is, the guide copper pad G-Cu Pad, will be higher. The peripheral circuit also includes boost circuits, amplifiers, semiconductors, resistors and other devices.

[0106] The main steps of preparing the top metal are to sequentially deposit silicon nitride + silicon oxide + silicon nitride + silicon oxide + silicon nitride structure on the wafer with semiconductor field effect transistors and windings, where the thickness of silicon nitride is 30-50nm, and the thickness of silicon oxide determines the capacitor area, and its thickness is 500-1000nm. In terms of the process flow, the guide copper pad G-Cu Pad can actually be regarded as a part of the formation of the top metal.

[0107] The guiding copper pad G-Cu Pad is responsible for leading out the lower metal winding in the periphery circuit area, while the array storage array area remains unchanged.

[0108] In detail, the guide copper pad winding Cu Pads are made by tungsten chemical vapor deposition process, and the other copper pad winding Cu Pads are made by dual damascene process, that is, copper-containing grooves are made after multiple photolithography and dry etching.

[0109] The detailed steps of the dual Damascus process can be seen from the attached drawings. At the same time, this is also a major process that is indispensable for forming the technical solution of the present invention. The main process is as follows, where V1 refers to the photoresist layer, which is used to define the shape of the metal wire. In this step, the pattern is transferred to the photoresist through photolithography technology, and then the pattern is used as a mask for the subsequent etching process. M2 refers to the metal interconnection line of the second layer. In the Damascus process, multiple metal layers are used to build complex integrated circuit structures. M2 represents the process of second-layer metal deposition and processing, including the preparation of the seed layer, copper electroplating filling, and final chemical mechanical polishing to achieve flattening. The M1 in the figure is naturally the first-layer metal interconnection line. Step ①: V1 SiO2+SiN Dep

[0110] SiO2: Silicon dioxide, usually used as an insulating layer.

[0111] SiN: Silicon nitride, used as a support layer and etch stop layer.

[0112] Step 2: V1 Photo

[0113] Photo: Photolithography or photoresist coating and exposure process. This step uses photoresist to define the area for subsequent processing.

[0114] Step 3: V1 Etch (Dry EH)

[0115] Etch: Etching process, removing unwanted material.

[0116] Dry EH: Dry etching uses plasma and other technologies to precisely control the etching depth and shape.

[0117] Step 4: M2 Photo

[0118] Similar to step ②, photolithography is performed again to define the structure of the M2 layer.

[0119] Step ⑤: M2 Etch (Dry EH)

[0120] Dry etching is performed again to form a groove of the M2 layer.

[0121] Step ⑥: M2 Ta+TaN+Cu seed (PVD)

[0122] Ta: Tantalum metal, used as a barrier layer to prevent copper diffusion.

[0123] TaN: Tantalum nitride, increases barrier effect and provides better adhesion.

[0124] Cu: Copper, used as a conductive material to fill the trench.

[0125] seed: Seed layer that provides an initial conductive path for electroplating.

[0126] PVD: Physical vapor deposition, depositing the above materials onto a substrate.

[0127] Step 7: M2 Cu ECP&Anneal

[0128] ECP: Electrochemical copper plating, filling the trench.

[0129] Anneal: Heat treatment to improve the crystallinity and stability of the material.

[0130] Step ⑧: M2 CMP (CMP will remove the surface barrier layer and stop on SiO2)

[0131] CMP: Chemical Mechanical Polishing, which flattens the surface and removes excess material until a predetermined stop layer such as SiO2 is reached.

[0132] The “PR” in the figure stands for photoresist, which is used to protect the non-etched area.

[0133] Example 7

[0134] Reference Figures 1 to 12 and Fig.17 , which is the seventh embodiment of the present invention, and is based on the previous embodiment, and is different from the previous embodiment in that: the capacitor hole has a hole diameter of 100-200nm and a hole depth of 1500nm-2000nm;

[0135] As mentioned above, the aperture affects the capacitance density. The larger the aperture, the lower the capacitance hole density. The smaller the aperture, the larger its aspect ratio and the more difficult the process is to achieve. Therefore, a reasonable aperture-to-depth ratio is selected to ensure that the capacitance density and capacitance aspect ratio are in the optimal process coupling area.

[0136] A lower electrode layer 200, a ferroelectric thin film layer 300, and an upper electrode layer 400 are deposited inside the capacitor hole;

[0137] The thickness of the lower electrode layer 200 is 10-15 nm;

[0138] The thickness of the ferroelectric thin film layer 300 is 8 to 10 nm;

[0139] The thickness of the upper electrode layer 400 is 10-15 nm.

[0140] The lower electrode layer 200, the ferroelectric thin film layer 300, and the upper electrode layer 400 are all formed by atomic layer deposition and by maskless etching;

[0141] The lower electrode layer 200 is composed of titanium nitride, and its reaction source is generally ammonia and titanium chloride NH3+TiCl4. The etching method adopts a plasma gas etching method, and uses the difference in etching speed between the wafer surface and the capacitor hole caused by the etching load effect to perform maskless etching to remove the titanium nitride TiN on the wafer surface and the metal tantalum nitride of the barrier layer, while retaining the thin film in the deep hole for capacitor preparation;

[0142] The ferroelectric thin film layer 300 is composed of zirconium-containing hafnium oxide. Based on the new hafnium oxide-based ferroelectric memory, the ferroelectric material is doped with Zr, which is usually Hf0.5Zr0.5O2, so as to improve the operating efficiency of the capacitor.

[0143] The upper electrode layer 400 and the lower electrode layer 200 are constructed in the same manner and are composed of titanium nitride.

[0144] It is worth mentioning that the upper electrodes in an array are actually driven by the same plate line. Each array contains several ferroelectric capacitors, which are represented as 3 in this scheme, so there is no need to etch other stacked capacitor materials in the same array except the lower electrode.

[0145] In detail, during the patterning process of the board lines between different arrays, there is an etching step that etches the dielectric layer and the upper electrode apart.

[0146] Example 8

[0147] Reference Figures 1 to 16 , which is the eighth embodiment of the present invention, and is based on the previous embodiment, and is different from the previous embodiment in that: a high temperature annealing process is adopted for the capacitor hole containing the capacitor material, and the heating temperature is 500-600° C.;

[0148] The so-called high-temperature annealing process uses a high-temperature furnace to heat to 500-600 degrees Celsius. Through annealing, the M phase in the hafnium oxide ferroelectric material is transformed into the O phase ferroelectric phase. The hafnium oxide base is divided into the M phase stable state, O phase and T phase. Among them, the O phase ferroelectric phase needs to convert the most distributed M phase and T phase into the O phase to improve the residual polarity and obtain a stable ferroelectric capacitor structure.

[0149] Depositing 100-200nm of titanium or aluminum onto the surface of the upper electrode layer 400, and dry-etching the plate line layer, the plate line thin film deposition, that is, using the PVD physical vapor deposition process, depositing 100-200nm of Ti titanium or Al aluminum metal film to fill the capacitor hole;

[0150] Using polyimide mail insulation layer to make PI vias (a custom rule in PCB design) and externalizing RDL Pad (rewiring layer) is a common process in the packaging process. The subsequent externalization of RDL Pad transfers the original external pad to a position more suitable for packaging. It is also a conventional board line distribution technology used to change the contact position of the wiring process and the bump process. The main processes include: seed Cu deposition → yellow light thick retaining wall → electroplating copper → retaining wall removal → seed Cu etching. The specific process can be seen from the attached figure.

[0151] After the ferroelectric capacitors are completely arranged, the capacitance area of ​​the storage array thus formed can be increased by 15-20%.

[0152] Example 9

[0153] Reference Figures 1 to 17 , which is the ninth embodiment of the present invention, and is based on the previous embodiment, and is different from the previous embodiment in that: the height of the hole in the copper pad winding Cu Pads can be changed to 400nm;

[0154] The height of the grooves in the copper pad windings Cu Pads was changed to 600nm.

[0155] Based on this change, the last layer of the copper pad winding Cu Pads is thickened from the original overall film thickness of less than 200nm to 1000nm.

[0156] In this scheme, the size of the top layer of the copper pad winding Cu Pads is also affected by the thickness of the silicon dioxide film.

[0157] This solution is to thicken the silicon dioxide film. For example, the thickness of the top two layers of silicon dioxide film is adjusted. The thickness of the silicon dioxide film used to form the "hole" is thickened from 40-100nm to 300nm, and the thickness of the silicon dioxide film used to form the "groove" is thickened from 100-200nm to 600nm. In this way, the overall thickness of the top layer of the copper pad winding Cu Pads will reach 1000nm, and other subsequent process flows remain unchanged.

[0158] After the adjustment, the capacitance area will increase by 40-50% compared to the current level.

[0159] Furthermore, the overall thickness of the top layer of the copper pad winding Cu Pads will reach 1000nm, and the aperture formed by the silicon dioxide used to form the "hole" will naturally increase accordingly. From the perspective of the dual Damascene process, the etching aspect ratio requirement is actually the highest in the etching part that forms the "hole". When the aperture increases, the aspect ratio will decrease accordingly. From the perspective of specific technical implementation, the aspect ratio is generally controlled to be less than 5:1. This adjustment will further reduce the aspect ratio, so the process difficulty will not increase. For example, the existing aperture is 45nm, and the aperture will be adjusted to 90-100nm after the depth increases.

[0160] Importantly, it should be noted that the construction and arrangement of the present application shown in a number of different exemplary embodiments are only exemplary. Although only a few embodiments are described in detail in this disclosure, it should be readily understood by those who refer to this disclosure that many modifications are possible, for example, the size, scale, structure, shape and proportion of various elements, and parameter values ​​such as temperature, pressure, etc., mounting arrangements, use of materials, color, directional changes, etc., without substantially departing from the novel teachings and advantages of the subject matter described in the application. For example, the element shown as integrally formed can be composed of multiple parts or elements, the position of the element can be inverted or otherwise changed, and the nature or number or position of the discrete element can be changed or changed. Therefore, all such modifications are intended to be included in the scope of the present invention. The order or sequence of any process or method steps can be changed or reordered according to alternative embodiments. In the claims, any "device plus function" clause is intended to cover the structure described herein that performs the function, and is not only structurally equivalent but also equivalent structure. Without departing from the scope of the present invention, other replacements, modifications, changes and omissions can be made in the design, operating conditions and arrangement of the exemplary embodiments. Therefore, the invention is not limited to a specific embodiment, but extends to numerous modifications still falling within the scope of the appended claims.

[0161] Additionally, in order to provide a concise description of exemplary embodiments, all features of an actual embodiment (ie, those features that are not relevant to the best mode presently contemplated for carrying out the invention or those that are not relevant to implementing the invention) may not be described.

[0162] It will be appreciated that in the development of any actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort may be complex and time-consuming, but will be a routine task of design, fabrication, and production for those of ordinary skill having the benefit of this disclosure without undue experimentation.

[0163] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A large-capacity ferroelectric capacitor, characterized in that: include, A metal via (100), and a hollow area (100a) opened at the end thereof; The inner wall of the hollow area (100a) is provided with a barrier layer (100a-1); Capacitor materials are deposited in sequence on the barrier layer (100a-1) and on the inner wall of the metal via (100).

2. The large-capacity ferroelectric capacitor according to claim 1, characterized in that: The capacitor material comprises a lower electrode layer (200), a ferroelectric thin film layer (300), and an upper electrode layer (400); The outer side of the barrier layer (100a-1) contacts with a copper pad (Cu Pad) of a lower layer; The copper pad (Cu Pad) has at least two layers; The overall height of each layer of copper pad (Cu Pad) is 140 to 300 nm, and is composed of holes and grooves, with a height ratio of holes to grooves of 1:

2.

3. The large-capacity ferroelectric capacitor according to claim 1 or 2, characterized in that: The barrier layer (100a-1) is an outer wall formed by the etched copper pad (Cu Pad).

4. A storage array, characterized in that: comprising a large-capacity ferroelectric capacitor as claimed in any one of claims 1 to 3, and The field effect tube (500) is uniformly prepared on the substrate; Copper pad windings (Cu Pads) are deposited and etched in sequence at the source and drain of the field effect tube (500); The top layers of the copper pad windings (Cu Pads) all contact the metal vias (100).

5. The storage array according to claim 4, characterized in that: The copper pad windings (Cu Pads) are sequentially deposited and etched in the peripheral circuit area on the substrate, and a guide copper pad (G-Cu Pad) which is highly flush with the metal via (100) is deposited on the top layer.

6. A method for preparing a large-capacity ferroelectric capacitor storage array, characterized in that: comprising the large-capacity ferroelectric capacitor as claimed in claim 5, and A semiconductor is opened on the wafer, the semiconductor is connected to the copper pad winding (Cu Pads), and a capacitor hole is prepared at the end of the winding; The copper Cu in the copper pad (Cu Pad) of the last layer of the winding is partially etched, and the outer barrier layer (100a-1) is retained.

7. The method for preparing a large-capacity ferroelectric capacitor storage array according to claim 6, characterized in that: The barrier layer (100a-1) forms a hollow area and is placed in the capacitor hole; Capacitor materials are deposited in sequence in the capacitor holes to form a ferroelectric capacitor storage array.

8. The method for preparing a large-capacity ferroelectric capacitor storage array according to claim 7, characterized in that: The semiconductor is prepared using a 14-45nm process node; Preparing copper pad windings (Cu Pads) formed by hole-groove structures on the source and drain of the semiconductor respectively; The height of each layer of the copper pad (Cu Pad) is 140nm-300nm, and is composed of holes and grooves with a height ratio of 1:

2.

9. The method for preparing a large-capacity ferroelectric capacitor storage array according to claim 8, characterized in that: The holes in the top layer of the copper pad winding (Cu Pads) have a height of 40 to 100 nm; The groove in the top layer of the copper pad winding (Cu Pads) has a height of 100-200 nm.

10. The method for preparing a large-capacity ferroelectric capacitor storage array according to claim 8, characterized in that: The hole in the topmost layer of the copper pad winding (Cu Pads) has a height of 400nm; The groove in the topmost layer of the copper pad winding (Cu Pads) has a height of 600 nm.

11. The method for preparing a large-capacity ferroelectric capacitor storage array according to claim 9 or 10, characterized in that: A top metal is deposited at the end of the copper pad winding (Cu Pads), and the capacitor hole, namely the metal via (100) and the cavity area (100a) are etched thereon.

12. The method for preparing a large-capacity ferroelectric capacitor storage array according to claim 11, characterized in that: The guide copper pad (G-Cu Pad) is made by a tungsten chemical vapor deposition process; The copper pad windings (Cu Pads) are all made by dual damascene process, that is, copper-containing grooves are made by multiple photolithography and dry etching.

13. The method for preparing a large-capacity ferroelectric capacitor storage array according to claim 7, 8 or 12, characterized in that: The capacitor hole has a hole diameter of 100-200 nm and a hole depth of 1500-2000 nm; The lower electrode layer (200), the ferroelectric thin film layer (300), and the upper electrode layer (400) are deposited inside the capacitor hole; The thickness of the lower electrode layer (200) is 10-15 nm; The ferroelectric thin film layer (300) has a thickness of 8 to 10 nm; The thickness of the upper electrode layer (400) is 10-15 nm.

14. The method for preparing a large-capacity ferroelectric capacitor storage array according to claim 13, characterized in that: The lower electrode layer (200), the ferroelectric thin film layer (300), and the upper electrode layer (400) are all formed by atomic layer deposition and by maskless etching; The lower electrode layer (200) is composed of titanium nitride; The ferroelectric thin film layer (300) is composed of zirconium-containing hafnium oxide; The upper electrode layer (400) is made of titanium nitride.

15. The method for preparing a large-capacity ferroelectric capacitor storage array according to claim 14, characterized in that: The capacitor hole containing the capacitor material is subjected to a high temperature annealing process at a heating temperature of 500-600° C.; Depositing 100-200 nm of titanium or aluminum onto the surface of the upper electrode layer, and dry-etching a plate line layer; Use polyimide organic insulating layer to make PI vias for external connection of RDL Pad.

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