Semiconductor storage structure and array

Abstract

The invention relates to the technical field of semiconductors, and discloses a semiconductor storage structure and an array, and the semiconductor storage structure at least comprises a plurality of semiconductor storage units, a top electrode, and gating devices corresponding to the semiconductor storage units. Each semiconductor storage unit at least comprises a spin orbit moment layer and a magnetic tunnel junction arranged above the spin orbit moment layer; the top electrode is located above the plurality of magnetic tunnel junctions, the plurality of magnetic tunnel junctions share the same top electrode, and a corresponding interconnection through hole is formed between the top electrode and each semiconductor storage unit; each gating device is arranged in the corresponding interconnection through hole, and the two ends of each gating device are electrically connected with the corresponding magnetic tunnel junction and the top electrode respectively. The number of transistors and wires can be reduced, the layout area occupied by the transistors and the wires is saved, and therefore the storage density is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, for example, to a semiconductor storage structure and array. Background Art

[0002] In recent years, magnetic random access memory (MRAM) has undergone a major development change from spin-transfer torque magnetic memory (STT-MRAM) to spin-orbit torque magnetic memory (SOT-MRAM). Compared with STT-MRAM, SOT-MRAM has the characteristics of high speed and low power consumption when reading and writing data.

[0003] A circuit structure of SOT-MRAM is disclosed in the related art, including a semiconductor memory cell, at least one read transistor, and at least one write transistor. The semiconductor memory cell includes a spin-orbit moment layer and a magnetic tunnel junction disposed above the spin-orbit moment layer. At least one read transistor is electrically connected to the magnetic tunnel junction to control the on-off of the read path of the semiconductor memory cell; at least one write transistor is electrically connected to the spin-orbit moment layer to control the on-off of the write path of the semiconductor memory cell.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art: The large number of transistors and wirings occupies too much layout area, resulting in reduced storage density. Summary of the invention

[0005] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0006] The embodiments of the present disclosure provide a semiconductor storage structure and array to reduce the number of transistors and wirings, save the layout area occupied by transistors and wirings, and thus improve storage density.

[0007] In some embodiments, the semiconductor storage structure includes at least: multiple semiconductor storage units, a top electrode and a gating device corresponding to each semiconductor storage unit; each semiconductor storage unit includes at least a spin-orbit moment layer and a magnetic tunnel junction arranged above the spin-orbit moment layer; the top electrode is located above the multiple magnetic tunnel junctions, and the multiple magnetic tunnel junctions share the same top electrode, and corresponding interconnection through holes are arranged between the top electrode and each semiconductor storage unit; each gating device is respectively arranged in the corresponding interconnection through hole, and the two ends of the gating device are respectively electrically connected to the corresponding magnetic tunnel junction and the top electrode.

[0008] The semiconductor storage structure provided by the embodiment of the present disclosure can achieve the following technical effects: compared with the traditional solution that the semiconductor storage unit uses the top electrode independently, the embodiment of the present disclosure adopts a method in which multiple semiconductor storage units share the same top electrode. On the one hand, each semiconductor storage unit can set the same wiring between the common top electrode and the substrate layer (for example, set the same top electrode interconnection through hole). Compared with the traditional solution of setting corresponding wiring between each top electrode and the substrate layer, the embodiment of the present disclosure can reduce the number of wirings between the top electrode and the substrate layer, thereby saving the layout area; on the other hand, only one wiring is set between the common top electrode and the substrate layer. Compared with the traditional solution of setting wiring between each top electrode and the substrate layer, the embodiment of the present disclosure does not need to wire in multiple places, which is conducive to simplifying the design process. The disclosed embodiment sets a gating device (such as a diode or a selector) in the interconnection through hole between the top electrode and the magnetic tunnel junction, so that the gating device is electrically connected to the top electrode and the magnetic tunnel junction respectively. On the one hand, in the conventional solution, the read channel and the write channel are each connected to a transistor. The disclosed embodiment replaces the conventional transistor connected to the read channel with a gating device, so that the number of transistors equipped in each semiconductor storage unit is reduced from two to one, which is conducive to saving the layout area of ​​the transistor layout area, thereby further saving the layout area; on the other hand, no wiring is required in the interconnection through hole between the top electrode and the magnetic tunnel junction, which is not only conducive to further saving the layout area, but also saves a wiring process. The disclosed embodiment sets the volume of the gating device in the interconnection through hole between the top electrode and the magnetic tunnel junction, which is much smaller than the volume of the conventional transistor connected to the read channel, thereby further saving the layout area. By reducing the number of transistors and the number of wirings, and reducing the volume of the device electrically connected to the read channel, the layout area is saved, which is conducive to improving the storage density.

[0009] In some embodiments, the semiconductor storage array includes at least: at least one top electrode interconnection through hole and multiple semiconductor storage structures as described above; wherein one end of the top electrode in each semiconductor storage structure is electrically connected to the top electrode interconnection through hole, so that multiple semiconductor storage structures share the same top electrode interconnection through hole.

[0010] The semiconductor storage array provided by the embodiment of the present disclosure can achieve the following technical effects: compared with the traditional solution of respectively setting corresponding top electrode interconnection through holes between the top electrode above each semiconductor storage unit and the substrate layer, first, multiple semiconductor storage structures share the same top electrode interconnection through hole, and the semiconductor storage units in each semiconductor storage structure can be used as a row or a column in the array. The semiconductor storage units in each row or column share the same top electrode interconnection through hole, that is, each semiconductor storage unit in the semiconductor storage array can share the same top electrode interconnection through hole. The embodiment of the present disclosure can reduce the number of top electrode interconnection through holes between the top electrode and the substrate layer of the entire array. The number of holes is increased, thereby further reducing the number of wirings, thereby further saving the layout area; second, only one top electrode interconnection through hole is made between the top electrodes of multiple semiconductor storage structures and the substrate layer. Compared with the traditional method of making one top electrode interconnection through hole between each top electrode and the substrate layer, the embodiment of the present disclosure does not need to make multiple top electrode interconnection through holes, which is conducive to further simplifying the design process; third, through the same top electrode interconnection through hole, the read path and the write path of each row or column of semiconductor storage units share a signal line, which is conducive to reducing the number of signal lines, thereby further reducing the number of wirings to save layout area and further simplifying the design process. In addition, the embodiment of the present disclosure can also reduce the number of transistors in the array and reduce the volume of the device electrically connected to the read channel, thereby further saving the layout area to further improve the storage density and further simplify the design process.

[0011] In some embodiments, the semiconductor storage array includes at least a plurality of the semiconductor storage structures described above; wherein the semiconductor storage cells in each semiconductor storage structure serve as a column; and through the top electrode interconnection vias of each semiconductor storage structure, the write path and the read path corresponding to each column of semiconductor storage cells share the same signal line.

[0012] The semiconductor storage array provided by the embodiment of the present disclosure can achieve the following technical effects: when the semiconductor storage units in each semiconductor storage structure are used as a column, each column of semiconductor storage units shares a top electrode interconnection through hole, thereby reducing the number of top electrode interconnection through holes between the top electrode corresponding to each column of semiconductor storage units and the substrate layer, thereby saving the layout area. The read path of each column of semiconductor storage units passes through the corresponding top electrode interconnection through hole and shares the same signal line with the write path, which is conducive to reducing the number of signal line wirings, thereby further saving the layout area. Since each signal line is electrically connected to the same external read-write unit, each column of semiconductor storage units shares the same external read-write unit through the same signal line, thereby reducing the number of external read-write units, thereby further saving the layout area. The storage density can be improved by saving the layout area. In addition, by sharing the signal line and the external read-write unit in each column of semiconductor storage units, it is also conducive to simplifying the design process.

[0013] In some embodiments, the semiconductor storage array includes at least a plurality of the above-mentioned semiconductor storage structures; wherein the semiconductor storage cells in each semiconductor storage structure serve as a column, and each row of semiconductor storage cells shares the same spin-orbit moment layer; the write paths corresponding to each semiconductor storage cell share the same write signal line; and the read paths corresponding to each column of semiconductor storage cells share the same read signal line.

[0014] The semiconductor storage array provided by the embodiment of the present disclosure can achieve the following technical effects: each column of semiconductor storage units shares the same top electrode, and each row of semiconductor storage units shares the same spin-orbit layer, which is conducive to further improving the integration density. The top electrode of each column is electrically connected to a read signal line, and each signal line is electrically connected to an external read unit, so that the read path corresponding to each column of semiconductor storage units shares the same external read unit, thereby reducing the number of external read units and the number of read signal lines. Each row of spin-orbit moment layers is electrically connected to the same write signal line, and is electrically connected to an external write unit through the write signal line, so that each semiconductor storage unit shares the same external write unit, thereby reducing the number of external write units and the number of write signal lines. By reducing the number of external read units, external write units, read signal lines, and write signal lines, it is conducive to further saving layout area and further simplifying the design process. By making the write path and the read path not share the signal line, the purpose of not setting the top electrode interconnection through hole is achieved, which is beneficial to further save the layout area and further simplify the process flow; preventing the write current from flowing through the read path is beneficial to reduce the signal interference between the read and write operations to improve the accuracy and reliability of data reading; the read and write operations can be performed independently, avoiding the conflicts and delays that may occur when the read and write share the signal line, thereby improving the read and write speed.

[0015] In some embodiments, the semiconductor storage array includes at least a plurality of the above-mentioned semiconductor storage structures; wherein the semiconductor storage cells in each semiconductor storage structure are arranged in a row; the write paths corresponding to each semiconductor storage cell share the same write signal line; and the read paths corresponding to each semiconductor storage cell share the same read signal line.

[0016] The semiconductor storage array provided by the embodiment of the present disclosure can achieve the following technical effects: each row of semiconductor storage cells shares the same top electrode, and each top electrode is electrically connected to a read signal line, and the read signal line is electrically connected to an external read unit, so that the read path of each semiconductor storage cell shares the same external read unit, thereby reducing the number of external read units and the number of read signal lines. The second end of the spin-orbit moment layer of each semiconductor storage cell is electrically connected to a write signal line, and the write signal line is electrically connected to an external write unit, so that the write path of each semiconductor storage cell shares the same external write unit, thereby reducing the number of external write units and the number of write signal lines. By reducing the number of external read units, external write units, read signal lines, and write signal lines, it is beneficial to further save layout area and further simplify the design process. By not sharing signal lines between the write path and the read path, the purpose of not setting up top electrode interconnection through holes is achieved, which is beneficial to further save layout area and further simplify the process flow; preventing the write current from flowing through the read path is beneficial to reduce signal interference between read and write operations to improve the accuracy and reliability of data reading; read and write operations can be performed independently, avoiding conflicts and delays that may occur when reading and writing share signal lines, thereby improving read and write speeds.

[0017] In some embodiments, the semiconductor storage array includes at least a plurality of the above-mentioned semiconductor storage structures; wherein the semiconductor storage cells in each semiconductor storage structure serve as a column; the write paths corresponding to each column of semiconductor storage cells share the same write signal line; and the read paths corresponding to each column of semiconductor storage cells share the same read signal line.

[0018] The semiconductor storage array provided by the embodiments of the present disclosure can achieve the following technical effects: Each column of semiconductor memory cells shares the same top electrode, and each top electrode is electrically connected to a corresponding read signal line, and each read signal line is electrically connected to a corresponding external read unit, so that the read path of each column of semiconductor memory cells shares the same external read unit, thereby reducing the number of external read units and the number of read signal lines. The second end of the spin-orbit moment layer of each column of semiconductor memory cells is electrically connected to a corresponding write signal line, and each write signal line is electrically connected to a corresponding external write unit, so that the write path of each column of semiconductor memory cells shares the same external write unit, thereby reducing the number of external write units and the number of write signal lines. By reducing the number of external read units, external write units, read signal lines, and write signal lines, it is beneficial to further save the layout area and further simplify the design process. By making the write path and the read path not share the signal line, the purpose of not setting the top electrode interconnection through hole is achieved, which is conducive to further saving the layout area and further simplifying the process flow; preventing the write current from flowing through the read path is conducive to reducing the signal interference between the read and write operations to improve the accuracy and reliability of data reading; the read and write operations can be performed independently, avoiding the conflicts and delays that may occur when the read and write share the signal line, thereby improving the read and write speed. In addition, when the read signal line is controlled by an external control circuit (such as a multiplexer), the current crosstalk between adjacent storage cells can be avoided, further improving reliability.

[0019] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily described by corresponding drawings, and these exemplary descriptions and drawings do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute proportional limitations.

[0021] Figure 1 It is a cross-sectional structural diagram of a semiconductor storage structure with a common top electrode interconnection through hole provided by an embodiment of the present disclosure.

[0022] Figure 2 It is a top view of a semiconductor storage structure with a common top electrode interconnection through hole provided by an embodiment of the present disclosure.

[0023] Figure 3 It is a cross-sectional structural diagram of a semiconductor storage structure with separated read and write paths provided by an embodiment of the present disclosure.

[0024] Figure 4 It is a cross-sectional structural diagram of another semiconductor storage structure with a common top electrode interconnection through hole provided by an embodiment of the present disclosure.

[0025] Figure 5It is a cross-sectional structural diagram of another semiconductor storage structure with separated read and write paths provided by an embodiment of the present disclosure.

[0026] Figure 6 The diagram is a top view of the structure of a semiconductor storage array in which multiple rows of semiconductor storage cells share top electrode interconnection vias, provided by an embodiment of the present disclosure.

[0027] Figure 7 This is an example provided by the embodiment of the present disclosure. Figure 6 The circuit structure and reading and writing method diagram of the semiconductor memory array shown.

[0028] Figure 8 Another example provided by the present disclosure is Figure 6 The circuit structure and reading and writing method diagram of the semiconductor memory array shown.

[0029] Fig. 9 The embodiment of the present disclosure provides a plurality of Figure 1 The circuit structure and reading and writing method schematic diagram of the semiconductor storage array of the semiconductor storage structure shown.

[0030] Fig.10 The embodiment of the present disclosure provides a plurality of Figure 4 The circuit structure and reading and writing method schematic diagram of the semiconductor storage array of the semiconductor storage structure shown.

[0031] Fig.11 The embodiment of the present disclosure provides a plurality of Figure 3 The circuit structure and reading and writing method schematic diagram of the semiconductor storage array of the semiconductor storage structure shown.

[0032] Fig.12 Another embodiment of the present disclosure provides a plurality of Figure 3 The circuit structure and reading and writing method schematic diagram of the semiconductor storage array of the semiconductor storage structure shown.

[0033] Fig.13 Another embodiment of the present disclosure provides a plurality of Figure 3 The circuit structure and reading and writing method schematic diagram of the semiconductor storage array of the semiconductor storage structure shown.

[0034] Figure numerals: 1: semiconductor memory cell; 11: spin-orbit moment layer; 12: magnetic tunnel junction; 121: free layer; 122: barrier layer; 123: reference layer; 2: top electrode; 31: unidirectional diode; 32: selector; 4: top electrode interconnection through hole; 5: write switch tube; BL: bit line; BL1: first bit line; BL2: second bit line; RBL: read bit line; RBL1: first read bit line; RBL2: second read bit line; RBL3: third read bit line; WBL: write bit line; WBL1: first write bit line; WBL2: second write bit line; SL: source line; SL1: first source line; SL2: second source line; SL3: third source line; SL4: fourth source line; WWL: write word line; WWL1: first write word line; WWL2: second write word line. DETAILED DESCRIPTION

[0035] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0036] The terms "first", "second", etc. in the description of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0037] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated devices, elements or components to have a specific direction, or to be constructed and operated in a specific direction. Moreover, in addition to being used to indicate directions or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0038] Unless otherwise stated, the term "plurality" means two or more.

[0039] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0040] In the related art, SOT-MRAM includes multiple semiconductor storage units, each of which includes at least a spin-orbit moment layer and a magnetic tunnel junction disposed on the spin-orbit moment layer; the magnetic tunnel junction includes at least a free layer, a tunnel layer, and a reference layer stacked in sequence from bottom to top, the free layer has a variable magnetic moment, the reference layer has a fixed magnetic moment, when the magnetic moments of the free layer and the reference layer are parallel, the resistance state of the magnetic tunnel junction is a low resistance state; when the magnetic moments of the free layer and the reference layer are antiparallel, the resistance state of the magnetic tunnel junction is a high resistance state. The high and low resistance states represent the stored binary data "0" or "1".

[0041] During the read operation, a read voltage is applied to one end of the magnetic tunnel junction and the spin-orbit moment layer, and the resistance state of the magnetic tunnel junction is determined by the magnitude of the read current flowing through the magnetic tunnel junction, thereby determining the stored data. During the write operation, when a write current is applied to the spin-orbit moment layer, a spin polarization current is generated, thereby generating a spin-orbit moment, causing the magnetic moment of the free layer to flip. By controlling the magnitude and direction of the write current, the direction of the magnetic moment flipping of the free layer can be controlled, thereby achieving high and low resistance state writing to achieve data writing.

[0042] The related art also discloses a circuit structure of SOT-MRAM, including a semiconductor memory cell, at least one read transistor, and at least one write transistor. The semiconductor memory cell includes a spin-orbit moment layer and a magnetic tunnel junction disposed above the spin-orbit moment layer. At least one read transistor is electrically connected to the magnetic tunnel junction to control the on-off of the read path of the semiconductor memory cell; at least one write transistor is electrically connected to the spin-orbit moment layer to control the on-off of the write path of the semiconductor memory cell.

[0043] However, there are at least the following problems in the related technology: the circuit structure corresponding to each semiconductor storage unit adopts two transistors for each magnetic tunnel junction, which are used for data writing and data reading respectively. The structure of "2 transistors + 1 magnetic tunnel junction" has a large number of transistors and wirings, and occupies too large a layout area, resulting in a decrease in storage density.

[0044] Combination Figures 1 to 5As shown, an embodiment of the present disclosure provides a semiconductor storage structure, comprising at least: a plurality of semiconductor storage units 1, a top electrode 2 and a gating device corresponding to each semiconductor storage unit 1; each semiconductor storage unit 1 comprises at least a spin-orbit moment layer 11 and a magnetic tunnel junction 12 arranged above the spin-orbit moment layer 11; the top electrode 2 is located above the plurality of magnetic tunnel junctions 12, and the plurality of magnetic tunnel junctions 12 share the same top electrode 2, and corresponding interconnection through holes are arranged between the top electrode 2 and each semiconductor storage unit 1; each gating device is respectively arranged in the corresponding interconnection through hole, and the two ends of the gating device are respectively electrically connected to the corresponding magnetic tunnel junction 12 and the top electrode 2.

[0045] By adopting the semiconductor storage structure provided by the embodiment of the present disclosure, compared with the traditional solution that the semiconductor storage unit independently uses the top electrode, the embodiment of the present disclosure adopts a method in which multiple semiconductor storage units 1 share the same top electrode 2. On the one hand, each semiconductor storage unit 1 can set the same wiring between the common top electrode 2 and the substrate layer (for example, set the same top electrode interconnection through hole 4). Compared with the traditional solution of setting corresponding wiring between each top electrode 2 and the substrate layer, the embodiment of the present disclosure can reduce the number of wirings between the top electrode 2 and the substrate layer, thereby saving the layout area; on the other hand, only one wiring is set between the common top electrode 2 and the substrate layer. Compared with the traditional solution of setting wiring between each top electrode 2 and the substrate layer, the embodiment of the present disclosure does not need to wire in multiple places, which is conducive to simplifying the design process. In the embodiment of the present disclosure, a gating device (such as a unidirectional diode 31 or a selector 32) is arranged in the interconnection through hole between the top electrode 2 and the magnetic tunnel junction 12, so that the gating device is electrically connected to the top electrode 2 and the magnetic tunnel junction 12 respectively. On the one hand, in the conventional scheme, the read channel and the write channel are each connected to a transistor. In the embodiment of the present disclosure, the conventional transistor connected to the read channel is replaced by a gating device, so that the number of transistors equipped in each semiconductor storage unit 1 is reduced from two to one, which is conducive to saving the layout area of ​​the transistor layout area, thereby further saving the layout area; on the other hand, no wiring is required in the interconnection through hole between the top electrode 2 and the magnetic tunnel junction 12, which is not only conducive to further saving the layout area, but also saves a wiring process. In the embodiment of the present disclosure, the volume of the gating device arranged in the interconnection through hole between the top electrode 2 and the magnetic tunnel junction 12 is much smaller than the volume of the conventional transistor connected to the read channel, thereby further saving the layout area. By reducing the number of transistors and the number of wirings, and reducing the volume of the device electrically connected to the read channel, the layout area is saved, which is conducive to improving the storage density.

[0046] It should be noted that the magnetic tunnel junction 12 includes a free layer 121, a barrier layer 122, and a reference layer 123 stacked in sequence from bottom to top. The material of the free layer 121 includes but is not limited to one or more combinations of Co, Fe, B, Ni, Ru, Ir, and Pt. The material of the barrier layer 122 includes but is not limited to one or more combinations of MgO, Al2O3, and SiO2. The reference layer 123 can be set as one or more layers, and when it is set as multiple layers, it at least includes a ferromagnetic layer and a pinned layer. The pinned layer can be set as an antiferromagnetic layer. The material of the antiferromagnetic layer can be a collinear antiferromagnetic material and a non-collinear antiferromagnetic material, including but not limited to IrMn, PtMn, IrMn3, and Mn3Sn.

[0047] The material of the spin-orbit moment layer 11 includes at least: a conductive layer with a strong coupling orbital coupling effect, one or more combinations of topological insulators. When the spin Hall angle of the conductive layer is positive, its materials include but are not limited to: one or more combinations of Pt, Pd, Hf, Au, AuPt, PtHf, PtCr, PtMn, FeMn, NiMn. When the spin Hall angle of the conductive layer is negative, its materials include but are not limited to Ta, W, Hf, Ir, IrMn, W, WO x , WN, W(O,N), TaN, TaB. Topological insulator materials include but are not limited to Bi x Se 1-x 、Bi x Sb 1-x , (Bi,Sb)2Te3 or one or more combinations thereof.

[0048] Optional, combined Figure 1 , Figures 3 to 5 As shown, a corresponding write path is formed between the first end and the second end of the spin-orbit moment layer 11 in each semiconductor memory unit 1; a corresponding read path is formed between one end of the top electrode 2, the gating device corresponding to each semiconductor memory unit 1, the corresponding magnetic tunnel junction 12, and the first end of the corresponding spin-orbit moment layer 11.

[0049] In this way, compared with the traditional solution in which the top electrode is used independently in the semiconductor memory cell, during the reading operation, the reading path of each semiconductor memory cell 1 can share the same top electrode 2, which is beneficial to saving layout area and simplifying the process on the one hand; on the other hand, it reduces the parasitic effects between the top electrodes 2 (such as parasitic resistance, parasitic capacitance, etc.), thereby reducing signal delay and reducing power consumption; on the other hand, it improves the consistency of the path and conditions of the read signal during the transmission process, thereby improving the accuracy and reliability of the read signal.

[0050] Optional, combined Figure 1 , Figures 3 to 5As shown, the gating device at least includes: one or more combinations of a unidirectional diode 31 and a selector 32. Specifically, when the gating device is a unidirectional diode 31, if the reading current of the reading path flows from one end of the top electrode 2 to the first end of the spin-orbit moment layer 11, the anode of the unidirectional diode 31 is electrically connected to the top electrode 2, and the cathode is electrically connected to the magnetic tunnel junction 12; if the reading current of the reading path flows from the first end of the top electrode 2 spin-orbit moment layer 11 to one end of the top electrode 2, the anode of the unidirectional diode 31 is electrically connected to the magnetic tunnel junction 12, and the cathode is electrically connected to the top electrode 2. When the gating device is a selector 32, one end of the selector 32 is electrically connected to the top electrode 2, and the other end is electrically connected to the magnetic tunnel junction 12.

[0051] In this way, since the volume of the unidirectional diode 31 and the selector 32 is smaller than that of the transistor, the read transistor in the traditional solution is replaced by the unidirectional diode 31 or the selector 32, which is conducive to reducing the number of transistors and thus saving the layout area. In addition, since the volume of the unidirectional diode 31 or the selector 32 is small, it can be better integrated in the interconnection through hole between the top electrode 2 and the magnetic tunnel junction 12, so that the top electrode 2, the gating device, and the magnetic tunnel junction 12 are no longer wired, thereby reducing the number of wiring and the process, thereby achieving the effect of further saving the layout area and simplifying the process. When the type of the gating device is a unidirectional diode 31, it can be cut off in one direction, and data reading and writing can be realized under the premise of saving the layout area. When the type of the gating device is a selector 32, since the selector 32 can be cut off in both directions, it can not only save the layout area and realize data reading and writing, but also effectively avoid the leakage current on the reading path caused by the reading and writing paths sharing the same bit line BL from entering the writing path, thereby improving the accuracy and reliability of the reading and writing data.

[0052] Optional, combined Figure 1 and Figure 4 As shown, the corresponding write path is electrically connected to the signal line through the second end of the spin-orbit moment layer 11 in each semiconductor memory unit 1; the semiconductor memory structure also includes at least one top electrode interconnection through hole 4; wherein one end of the top electrode 2 is electrically connected to the top electrode interconnection through hole 4, so that multiple semiconductor memory units 1 share the same top electrode interconnection through hole 4; the corresponding read path of each semiconductor memory unit 1 is electrically connected to the signal line through the top electrode interconnection through hole 4, so that the corresponding read path and the corresponding write path share the signal line.

[0053] In this way, each semiconductor storage unit 1 is provided with the same top electrode interconnection through hole 4 between the common top electrode 2 and the substrate layer. Compared with the conventional solution of providing corresponding top electrode interconnection through holes 4 between each top electrode 2 and the substrate layer, the embodiment of the present disclosure can reduce the number of top electrode interconnection through holes 4 between the top electrode 2 and the substrate layer, thereby saving the layout area and simplifying the design process. One end of the top electrode interconnection through hole 4 is electrically connected to one end of the top electrode 2, and the other end is electrically connected to the signal line provided in the substrate layer. Through the same top electrode interconnection through hole 4, the corresponding read path and write path of each semiconductor storage unit 1 share the signal line, which is conducive to reducing the number of wiring of the signal line, thereby further saving the layout area and simplifying the design process.

[0054] It should be noted that the top electrode interconnection through hole 4 is a structure formed by filling a conductive material in the interconnection through hole between the top electrode 2 and the substrate layer, one end of which is electrically connected to the top electrode 2, and the other end of which is electrically connected to the conductive structure provided in the substrate layer, thereby achieving electrical connection between the top electrode 2 and the conductive structure in the substrate layer. In the embodiment of the present disclosure, the conductive structure provided in the substrate layer may be a signal line.

[0055] Specifically, the signal lines include but are not limited to bit lines, source lines, and word lines. Figure 4 Only the case where the signal line is a bit line BL is shown in the figure, and other types of signal lines can be adjusted and set according to actual needs, and are not listed here one by one. This is conducive to improving the flexibility of wiring.

[0056] Specific, combined Figure 1 and Figure 4 As shown, when one end of the top electrode 2 is electrically connected to the bit line BL set in the substrate layer, the second end of the spin-orbit moment layer 11 is electrically connected to the bit line BL, so that the read path and the write path corresponding to each semiconductor storage unit 1 in the semiconductor storage structure share the bit line. The first end of the spin-orbit moment layer 11 is electrically connected to the source line, so that each semiconductor storage unit 1 in the semiconductor storage structure shares the source line SL. By reducing the number of wirings of the source line SL and the bit line BL, it is beneficial to further save the layout area, thereby improving the storage density.

[0057] Optional, combined Figure 3 and Figure 5 As shown, the corresponding write path is electrically connected to the write signal line through the second end of the spin-track moment layer 11 corresponding to each semiconductor memory unit 1; the read path corresponding to each semiconductor memory unit 1 is directly electrically connected to the read signal line through one end of the top electrode 2.

[0058] Thus, compared with the conventional solution of setting corresponding top electrode interconnection through-holes 4 between each top electrode 2 and the substrate layer, the disclosed embodiment realizes that the write path and the read path do not share signal lines by using multiple semiconductor storage units 1 to share the top electrode 2, and connecting one end of the top electrode 2 to the read signal line, and connecting the second end of the spin orbit moment layer 11 to the write signal line. By not sharing signal lines between the read and write paths, the purpose of not setting the top electrode interconnection through-holes 4 between the top electrode 2 and the substrate layer is achieved, and the layout area is further saved and the design process is further simplified by reducing the top electrode interconnection through-holes 4. By not sharing signal lines between the read and write paths, it is beneficial to avoid the write current from flowing into the read path through the shared signal line, thereby preventing the write current from flowing through the read path and the read current from flowing through the write path, which is beneficial to reducing the signal interference between the read and write operations to improve the accuracy and reliability of data reading; the read and write operations can be performed independently, avoiding conflicts and delays that may occur when the read and write share signal lines, thereby improving the read and write speeds.

[0059] Specifically, the write signal line includes but is not limited to a write bit line, a write source line, and a write word line. The read signal line includes but is not limited to a read bit line, a read source line, and a read word line. Figure 3 and Figure 5 Only the case where the read signal line is the read bit line RBL and the write signal line is the write bit line WBL is shown in the figure. Other types of read signal lines and write signal lines can be adjusted and set according to actual needs, and are not listed here one by one. This is conducive to improving the flexibility of wiring.

[0060] Specific, combined Figure 3 and Figure 5 As shown, when one end of the top electrode 2 is electrically connected to the read bit line RBL, the second end of the spin-orbit moment layer 11 is electrically connected to the write bit line WBL, so that the read path and the write path corresponding to each semiconductor storage unit 1 in the semiconductor storage structure do not share the bit line, which can improve the accuracy and reliability of the read and write operations. The read path of each semiconductor storage unit 1 shares the same read bit line RBL, and the write path uses the same write bit line WBL, which is conducive to reducing the number of top electrode interconnection through holes 4, read bit lines RBL and write bit lines WBL, thereby saving layout area and simplifying the design process. The first end of the spin-orbit moment layer 11 is electrically connected to the source line SL, so that each semiconductor storage unit 1 in the semiconductor storage structure shares the source line SL. By reducing the number of wiring of the source line SL and the bit line, it is conducive to further saving the layout area, thereby improving the storage density.

[0061] Optional, combined Figures 7 to 13As shown, the semiconductor storage structure at least includes a write switch tube 5 corresponding to each semiconductor storage unit 1. The second end of the spin-orbit moment layer 11 of the corresponding semiconductor storage unit 1 is electrically connected to the bit line (or write bit line) through the controlled end of the write switch tube 5. The main control end of the write switch tube 5 is electrically connected to the write word line to control the on-off of the controlled end of the switch tube. By controlling the on-off of the controlled end of the write switch tube 5, the on-off between the second end of the spin-orbit moment layer 11 of the corresponding semiconductor storage unit 1 and the bit line (or write bit line) is achieved, thereby realizing the switching of the corresponding write path and the read path.

[0062] Specifically, the write switch tube 5 includes but is not limited to a bipolar transistor, a thyristor, and a field effect transistor. When the write switch tube 5 is a field effect transistor, the main control end is the gate, and the controlled end is the source and the drain.

[0063] Specifically, when the main control end of the write switch tube 5 is turned on, the controlled end of the write switch tube 5 is turned on to connect the second end of the spin-orbit moment layer 11 of the corresponding semiconductor storage unit 1 to the bit line (or write bit line), thereby turning on the write path and disconnecting the read path; when the main control end of the write switch tube 5 is turned off, the controlled end of the write switch tube 5 is turned off to disconnect the second end of the spin-orbit moment layer 11 of the corresponding semiconductor storage unit 1 from the bit line (or write bit line), thereby disconnecting the write path and connecting the read path.

[0064] In this way, by controlling the on and off of the main control end of the write switch tube 5, the bit line (or write bit line) is electrically connected to the second end of the spin-track moment layer 11, thereby realizing selective writing of the semiconductor storage unit 1.

[0065] Combination Figures 6 to 8 As shown, an embodiment of the present disclosure provides a semiconductor storage array, comprising at least: at least one top electrode interconnection through hole 4 and a plurality of the above-mentioned semiconductor storage structures; wherein one end of the top electrode 2 in each semiconductor storage structure is electrically connected to the top electrode interconnection through hole 4, so that a plurality of semiconductor storage structures share the same top electrode interconnection through hole 4.

[0066] It should be noted that the semiconductor memory cell 1 in each semiconductor memory structure can be used as a row or a column of semiconductor memory cells 1 in a semiconductor memory array, thereby forming a semiconductor memory array.

[0067] Compared with the conventional solution of respectively setting corresponding top electrode interconnection through holes 4 between the top electrode 2 above each semiconductor storage unit 1 and the substrate layer, the semiconductor storage array provided by the embodiment of the present disclosure has the following advantages: first, multiple semiconductor storage structures share the same top electrode interconnection through hole 4, and the semiconductor storage units 1 in each semiconductor storage structure can be used as a row or a column in the array. The semiconductor storage units 1 in each row or column share the same top electrode interconnection through hole 4, that is, each semiconductor storage unit 1 in the semiconductor storage array can share the same top electrode interconnection through hole 4. The embodiment of the present disclosure can reduce the number of top electrode interconnection through holes 4 between the top electrode 2 and the substrate layer of the entire array. The amount of wiring is further reduced, thereby further saving the layout area; secondly, only one top electrode interconnection through hole 4 is made between the top electrodes 2 of the multiple semiconductor storage structures and the substrate layer. Compared with the traditional method of making one top electrode interconnection through hole 4 between each top electrode 2 and the substrate layer, the embodiment of the present disclosure does not need to make multiple top electrode interconnection through holes 4, which is conducive to further simplifying the design process; thirdly, through the same top electrode interconnection through hole 4, the read path and the write path of the semiconductor storage unit 1 in each row or column share a signal line, which is conducive to reducing the number of signal lines, thereby further reducing the number of wiring to save layout area and further simplifying the design process. In addition, the embodiment of the present disclosure can also reduce the number of transistors in the array and reduce the volume of the device electrically connected to the read channel, thereby further saving the layout area to further improve the storage density and further simplify the design process. It should be noted that the embodiment of the present disclosure especially saves the layout area of ​​the semiconductor storage array to improve the storage density of the semiconductor storage array.

[0068] Optionally, the through-holes 4 are interconnected through the same top electrode, so that the read path and the write path corresponding to each semiconductor memory cell 1 share the same signal line.

[0069] Specifically, each top electrode 2 is electrically connected to the same signal line through the same top electrode interconnection through hole 4, so that the read path corresponding to each semiconductor storage unit 1 is electrically connected to the same signal line. The second end of the spin-track moment layer 11 of each semiconductor storage unit 1 is electrically connected to the same signal line, so that the write path corresponding to each semiconductor storage unit 1 is electrically connected to the same signal line.

[0070] Specifically, the signal lines include but are not limited to bit lines BL arranged in the substrate layer.

[0071] In this way, the read path is electrically connected to the same signal line through the same top electrode interconnection through-hole 4, and the write path is electrically connected to the same signal line through the second end of the spin-track moment layer 11, so that the read path and the write path of each row and column of the semiconductor storage unit 1 share the same signal line, greatly reducing the number of signal lines, thereby further saving layout area and simplifying the design process.

[0072] Optionally, the first end of the spin-orbit moment layer 11 of each semiconductor storage unit 1 is electrically connected to the corresponding source line, so that each semiconductor storage unit 1 uses the corresponding source line independently, such as the first source line SL1 corresponding to the first semiconductor storage unit, the second source line SL2 corresponding to the second semiconductor storage unit, the third source line SL3 corresponding to the third semiconductor storage unit, and the fourth source line SL4 corresponding to the fourth semiconductor storage unit, etc., which are not listed one by one here. The second end of the spin-orbit moment layer 11 of each semiconductor storage unit is electrically connected to the same bit line BL through the corresponding write switch tube 5 controlled end, so that the write path of each semiconductor storage unit 1 shares the same bit line BL. The main control end of each write switch tube 5 is electrically connected to the same write word line WWL, so that each semiconductor storage unit 1 shares the same write word line WWL.

[0073] In this way, the write path of each semiconductor memory cell 1 shares the same bit line BL, and the number of wirings in the write circuit design is reduced by reducing the number of bit lines BL, thereby saving layout area and simplifying the process. Each semiconductor memory cell 1 shares the same write word line WWL, and the write path and read path of multiple semiconductor memory cells 1 can be switched at the same time, thereby realizing the simultaneous switching of the write mode and the read mode of multiple semiconductor memory cells 1, which is conducive to simplifying the control logic on the basis of saving layout area and simplifying the process. Each semiconductor memory cell 1 independently uses the corresponding source line, so each semiconductor memory cell 1 corresponds to an independent external read-write unit, which is conducive to selective reading and writing.

[0074] Optional, combined Figure 7 and Figure 8As shown, the write mode of the semiconductor storage array includes at least: single write and multiple write. It should be noted that single write refers to the realization of single data write of each semiconductor storage unit 1, and multiple write refers to the realization of simultaneous data write of multiple semiconductor storage units 1, which will not be repeated in the following text. When the write mode is single write, its write method at least includes: connecting the source line (for example, the first source line SL1) corresponding to the selected semiconductor storage unit 1 (for example, the first row and the first column) to the external write unit, and the source lines (for example, the second source line SL2 to the fourth source line SL4) corresponding to the unselected semiconductor storage unit 1 are suspended; when the write word line WWL controls the main control end of the write switch tube 5 to be turned on, the bit line BL is turned on with the second end of the spin-orbit moment layer 11, and different write voltages are applied to the bit line BL and the source line (for example, the first source line SL1) corresponding to the selected semiconductor storage unit 1, thereby adjusting the amplitude and direction of the write current of the write path corresponding to the selected semiconductor storage unit 1, and then realizing the writing of the magnetic tunnel junction 12 of the selected semiconductor storage unit 1 in different directions. When the write mode is multiple write, it is only necessary to connect the source lines corresponding to the multiple selected semiconductor storage units 1 (for example, the first source line SL1 and the second source line SL2) to the external write unit, and the other control logic is the same as the control logic of the single write, which will not be repeated here. It should be noted that the writing mode of the semiconductor storage array and the setting of the external write unit can be adjusted according to the needs in the actual application process, and will not be listed one by one here.

[0075] In this way, single writing and multiple writing of the semiconductor memory array can be realized, thereby improving the flexibility of the writing method.

[0076] The read mode of the semiconductor memory array includes at least: single read and multiple read. It should be noted that single read refers to realizing the single data read of each semiconductor memory cell 1, and multiple read refers to realizing the simultaneous data read of multiple semiconductor memory cells 1, which will not be repeated in the following text. When the read mode is single read, the number of external read units can be set to one, so that each semiconductor memory cell 1 shares the same external read unit. Its reading method at least includes: grounding the source line (for example, the first source line SL1) corresponding to the selected semiconductor memory cell 1 (for example, the first row and the first column), and its read path is turned on, and the source lines corresponding to the unselected semiconductor memory cells 1 are suspended (for example, the second source line SL2 to the fourth source line SL4); when the write word line WWL controls the write switch tube 5 to turn off the main control end, the bit line BL and the second end of the spin-orbit moment layer 11 in all semiconductor memory cells 1 are turned off, so that the write paths corresponding to all semiconductor memory cells 1 are turned off; thereby realizing the data reading of the selected semiconductor memory cell 1. When the read mode is multiple reads, each semiconductor storage unit 1 can use an external read unit separately, and the read method at least includes: grounding the source lines (such as the first source line SL1 and the second source line SL2) corresponding to the selected multiple semiconductor storage units 1, so that the selected semiconductor storage unit 1 is connected to the corresponding external read unit, and other control logic is the same as the control logic of the single read, which will not be repeated here. It should be noted that the reading method of the semiconductor storage array and the setting of the external read unit can be adjusted according to the needs in the actual application process, and will not be listed one by one here.

[0077] In this way, single reading and multiple reading of the semiconductor memory array can be realized, thereby improving the flexibility of the reading method. Among them, since the same external reading unit can be shared during single reading, the layout area can be further optimized.

[0078] It should be noted that, combined with Figure 7 As shown, when the selection device is a unidirectional diode 31, since the unidirectional diode 31 is provided in the reading path, the writing current can be prevented from flowing into the reading path through the magnetic tunnel junction 12 during writing, thereby improving the accuracy and reliability of the reading and writing operations. Figure 8 As shown, when the type of device to be selected is the selector 32, since the selector 32 can be bidirectionally cut off, it can not only save layout area, realize data reading and writing, and avoid the write current from flowing into the read path through the magnetic tunnel junction 12, but also effectively avoid the leakage current during writing caused by the read and write paths sharing the same bit line BL from flowing into the read path through the bit line BL, thereby further improving the accuracy and reliability of the read and write operations.

[0079] Combination Fig. 9 and Fig.10As shown, an embodiment of the present disclosure provides a semiconductor storage array, comprising at least a plurality of the above-mentioned semiconductor storage structures; wherein the semiconductor storage units 1 in each semiconductor storage structure serve as a column; and through the top electrode interconnection through-holes 4 of each semiconductor storage structure, the write path and the read path corresponding to each column of semiconductor storage units 1 share the same signal line.

[0080] Specifically, the signal line includes but is not limited to a bit line arranged in the substrate layer. For example, a first bit line BL1 corresponding to the first column semiconductor memory cell 1, a second bit line BL2 corresponding to the second column semiconductor memory cell 1, etc., are not listed one by one here. Each column of semiconductor memory cells 1 is electrically connected to a corresponding bit line through a corresponding top electrode interconnection through hole 4, for example, the first column semiconductor memory cell 1 is electrically connected to the first bit line BL1 through a corresponding top electrode interconnection through hole 4, and the second column semiconductor memory cell 1 is electrically connected to the second bit line BL2 through a corresponding top electrode interconnection through hole 4, etc., which are not listed one by one here.

[0081] Using the semiconductor storage array provided by the embodiment of the present disclosure, when the semiconductor storage unit 1 in each semiconductor storage structure is used as a column, each column of semiconductor storage units 1 shares a top electrode interconnection through hole 4, thereby reducing the number of top electrode interconnection through holes 4 between the top electrode 2 and the substrate layer corresponding to each column of semiconductor storage units 1, thereby saving the layout area. The read path of each column of semiconductor storage units 1 passes through the corresponding top electrode interconnection through hole 4, and shares the same signal line with the write path, which is conducive to reducing the number of signal line wiring, thereby further saving the layout area. Since each signal line is electrically connected to the same external read-write unit, each column of semiconductor storage units 1 shares the same external read-write unit through the same signal line, thereby reducing the number of external read-write units, thereby further saving the layout area. The storage density can be improved by saving the layout area. In addition, by sharing the signal line and the external read-write unit in each column of semiconductor storage units 1, it is also conducive to simplifying the design process. It should be noted that the embodiment of the present disclosure particularly saves the layout area of ​​the semiconductor storage array to improve the storage density of the semiconductor storage array.

[0082] Optionally, the first ends of the spin-orbit moment layers 11 of each row of semiconductor memory cells 1 are respectively electrically connected to the corresponding source lines, so that each row of semiconductor memory cells 1 shares the same corresponding source line, for example, the first row of semiconductor memory cells 1 shares the first source line SL1, the second row of semiconductor memory cells 1 shares the second source line SL2, etc., which are not listed one by one here. The second ends of the spin-orbit moment layers 11 of each column of semiconductor memory cells 1 are respectively electrically connected to the same corresponding bit line through the corresponding controlled ends of the write switch tubes 5, so that the corresponding write paths of each column of semiconductor memory cells 1 share the same corresponding bit line, for example, the first column of semiconductor memory cells 1 share the first bit line BL1, the second column of semiconductor memory cells 1 share the second bit line BL2, etc., which are not listed one by one here. The main control ends of the write switch tubes 5 of each column of semiconductor memory cells 1 are respectively electrically connected to the same corresponding write word line, so that each column of semiconductor memory cells 1 shares the same write word line, for example, the first column of semiconductor memory cells 1 share the first write word line WWL1, and the second column of semiconductor memory cells 1 share the second write word line WWL2, which are not listed one by one here.

[0083] In this way, the read path and the write path of each column of semiconductor memory cells 1 share the same bit line, which is conducive to reducing the number of bit lines, so as to save the number of wiring when designing the write circuit, thereby saving the layout area and simplifying the process. Each column of semiconductor memory cells 1 shares the same write word line WWL, which can simultaneously realize the switching of the write path and the read path of multiple semiconductor memory cells 1, thereby realizing the simultaneous switching of the write mode and the read mode of multiple semiconductor memory cells 1, and realizing the simplification of control logic on the basis of saving layout area and simplifying the process. Each row of semiconductor memory cells 1 shares the same corresponding source line, so that each row of semiconductor memory cells 1 corresponds to the same external read-write unit, which is conducive to reducing the number of external read-write units and further saving layout area. By sharing the source line in each row and the write word line and bit line in each column, it is conducive to selective reading and writing.

[0084] Optional, combined Fig. 9 and Fig.10As shown, the write mode of the semiconductor storage array includes at least: single write and multiple write. When the write mode is single write, the write method includes at least: determining the source line (e.g., the first source line SL1) corresponding to the row where the selected semiconductor storage unit 1 (e.g., the first row and the first column) is located, the bit line (e.g., the first bit line BL1) corresponding to the column where it is located, and the write word line (e.g., the first write word line WWL1); connecting the corresponding source line (e.g., the first source line SL1) to the external write unit, and the other source lines (e.g., the second source line SL2 to the fourth source line SL4) are suspended; when the corresponding write word line (e.g., the first write word line WWL1) controls the main control end of the write switch tube 5 to be turned on, the corresponding bit line (e.g., the first bit line BL1) is turned on with the second end of the corresponding spin-orbit moment layer 11, and different write voltages are applied to the bit line (e.g., the first bit line BL1) and the source line (e.g., the first source line SL1), thereby adjusting the amplitude and direction of the write current of the write path corresponding to the selected semiconductor storage unit 1, and then realizing the writing of the magnetic tunnel junction 12 of the selected semiconductor storage unit 1 in different directions. When the write mode is multiple writes, the source line (for example, the first source line SL1) corresponding to the row, the bit line (for example, the first bit line BL1 and the second bit line BL2) corresponding to the column and the write word line (for example, the first write word line WWL1 and the second write word line WWL2) corresponding to the selected multiple semiconductor storage units 1 (for example, the first row and first column, the first row and second column semiconductor storage units 1) are determined; other control logic is the same as the control logic for single writing and will not be repeated here.

[0085] In this way, single writing and multiple writing of the semiconductor memory array can be realized, thereby improving the flexibility of the writing method.

[0086] The read mode of the semiconductor storage array includes at least: single read and multiple read. When the read mode is single read, the read method includes at least: determining the source line (e.g., the first source line SL1) corresponding to the row where the selected semiconductor storage unit 1 (e.g., the first row and the first column) is located, the bit line (e.g., the first bit line BL1) corresponding to the column where it is located, and the write word line (e.g., the first write word line WWL1); grounding the corresponding source line (e.g., the first source line SL1), and its read path is turned on, and other source lines (e.g., the second source line SL2 to the fourth source line SL4) are suspended, and their read paths are turned off; when the corresponding write word line (e.g., the first write word line WWL1) controls the main control end of the write switch tube 5 to turn off, the corresponding bit line (e.g., the first bit line BL1) and the second end of the corresponding spin-orbit moment layer 11 are turned off, and its write path is turned off; thereby realizing the data reading of the selected semiconductor storage unit 1. When the read mode is multiple reads, each row of semiconductor storage cells 1 can share the same corresponding external read unit, and the reading method is: the source line (for example, the first source line SL1) corresponding to the row where the selected multiple semiconductor storage cells 1 are located is grounded, so that the selected semiconductor storage cells 1 are connected to the corresponding external read unit; the write word line (for example, the first write word line WWL1 and the second write word line WWL2) corresponding to the column where the selected multiple semiconductor storage cells 1 are located controls the corresponding write switch tube 5 main control end to turn off, and other control logic is the same as the control logic of single reading, which will not be repeated here. It should be noted that the reading method of the semiconductor storage array and the setting of the external read unit can be adjusted according to needs during actual application, and will not be listed one by one here.

[0087] In this way, single reading and multiple reading of the semiconductor memory array can be realized, thereby improving the flexibility of the reading method. In particular, since each row of semiconductor memory cells 1 can share the same external reading unit during single reading, the layout area can be further optimized.

[0088] It should be noted that, combined with Fig. 9 As shown, when the selection device is a unidirectional diode 31, since the unidirectional diode 31 is provided in the reading path, the writing current can be prevented from flowing into the reading path through the magnetic tunnel junction 12 during writing, thereby improving the accuracy and reliability of the reading and writing operations. Fig.10 As shown, when the type of the selection device is the selector 32, since the selector 32 can be bidirectionally cut off, it can not only save layout area, realize data reading and writing, and avoid the write current from flowing into the read path through the magnetic tunnel junction 12, but also effectively avoid the leakage current during writing caused by the read and write paths sharing the same bit line from flowing into the read path through the bit line, thereby further improving the accuracy and reliability of the read and write operations.

[0089] Combination Fig.11As shown, an embodiment of the present disclosure provides a semiconductor storage array, comprising at least a plurality of the above-mentioned semiconductor storage structures; wherein the semiconductor storage units 1 in each semiconductor storage structure serve as a column, and each row of semiconductor storage units 1 shares the same spin-orbit moment layer 11; the write paths corresponding to each semiconductor storage unit 1 share the same write signal line; and the read paths corresponding to each column of semiconductor storage units 1 share the same read signal line.

[0090] Specifically, the write signal line includes but is not limited to the write bit line WBL. Each row of semiconductor memory cells 1 is electrically connected to the same write bit line WBL through the second end of the common spin-track moment layer 11. The read signal line includes but is not limited to the read bit line, such as the first read bit line RBL1 corresponding to the first column of semiconductor memory cells 1, the second read bit line RBL2 corresponding to the second column of semiconductor memory cells 1, etc., which are not listed one by one here. Each column of semiconductor memory cells 1 is electrically connected to the corresponding read bit line through one end of the common top electrode 2.

[0091] With the semiconductor storage array provided by the embodiment of the present disclosure, each column of semiconductor storage units 1 shares the same top electrode 2, and each row of semiconductor storage units 1 shares the same spin-orbit layer, which is conducive to further improving the integration density. The top electrode 2 of each column is electrically connected to a read signal line, and each signal line is electrically connected to an external read unit, so that the read path corresponding to each column of semiconductor storage units 1 shares the same external read unit, thereby reducing the number of external read units and the number of read signal lines. Each row of spin-orbit moment layers 11 is electrically connected to the same write signal line, and is electrically connected to an external write unit through the write signal line, so that each semiconductor storage unit 1 shares the same external write unit, thereby reducing the number of external write units and the number of write signal lines. By reducing the number of external read units, external write units, read signal lines, and write signal lines, it is conducive to further saving layout area and further simplifying the design process. By making the write path and the read path not share the signal line, the purpose of not setting the top electrode interconnection through hole 4 is achieved, which is conducive to further saving the layout area and further simplifying the process flow; preventing the write current from flowing through the read path is conducive to reducing the signal interference between the read and write operations to improve the accuracy and reliability of data reading; the read and write operations can be performed independently, avoiding the conflicts and delays that may occur when the read and write share the signal line, thereby improving the read and write speed. It should be noted that the embodiment of the present disclosure especially saves the layout area of ​​the semiconductor storage array to improve the storage density of the semiconductor storage array.

[0092] Optionally, the first end of the common spin-orbit moment layer 11 of each row of semiconductor memory cells 1 is electrically connected to the corresponding source line, so that each row of semiconductor memory cells 1 shares the same corresponding source line, for example, the first row of semiconductor memory cells 1 shares the first source line SL1, the second row of semiconductor memory cells 1 shares the second source line SL2, the third row of semiconductor memory cells 1 shares the third source line SL3, etc., which are not listed one by one here. The second end of the spin-orbit moment layer 11 of each row of semiconductor memory cells 1 is electrically connected to the same write bit line WBL through the corresponding write switch tube 5 controlled end, so that the corresponding write path of each semiconductor memory cell 1 shares the same write bit line WBL. The main control end of the write switch tube 5 of each row of semiconductor memory cells 1 is electrically connected to the same write word line WWL, so that each semiconductor memory cell 1 shares the same write word line WWL.

[0093] In this way, each semiconductor memory cell 1 shares the same write bit line WBL and write word line WWL, which is conducive to further reducing the number of write bit lines and write word lines, thereby further saving layout area and simplifying the process. Each semiconductor memory cell 1 shares the same write word line WWL, which is conducive to simultaneously switching the write path and the read path of multiple semiconductor memory cells 1, thereby realizing the simultaneous switching of the write mode and the read mode of multiple semiconductor memory cells 1, thereby simplifying the control logic. By sharing the source line for each row and the read bit line for each column, it is conducive to selective reading and writing.

[0094] Optional, combined Fig.11 As shown, the write mode of the semiconductor storage array includes at least: single write and multiple write. When the write mode is single write, its write method includes: determining the source line (e.g., the first source line SL1) of the row where the selected semiconductor storage unit 1 (e.g., the first row and the first column) is located, and the read bit line (e.g., the first read bit line RBL1) of the column where the selected semiconductor storage unit 1 (e.g., the first row and the first column) is located; connecting the corresponding source line (e.g., the first source line SL1) to the external write unit, and other source lines (e.g., the second source line SL2 to the fourth source line SL4) are suspended; the write word line WWL controls the main control end of the write switch tube 5 to turn on, and applies a voltage to the corresponding read bit line (e.g., the first read bit line RBL1), and through voltage-controlled magnetic anisotropy (VCMA), the flip voltage threshold of the magnetic tunnel junction 12 in the corresponding semiconductor storage unit 1 (e.g., the first row and the first column semiconductor storage unit 1) is reduced, thereby realizing the data writing of the corresponding semiconductor storage unit 1 (e.g., the first row and the first column semiconductor storage unit 1). When the write mode is multiple write, its write method is the same as the control logic when writing alone, and it will not be repeated here.

[0095] In this way, on the one hand, single writing and multiple writing of the semiconductor storage array can be realized, thereby improving the flexibility of the writing method. On the other hand, the writing voltage threshold of the selected semiconductor storage unit 1 is reduced by voltage-controlled magnetic anisotropy, thereby reducing the writing current when writing data, thereby reducing the writing power consumption.

[0096] Optionally, the read mode of the semiconductor storage array includes at least: single read and multiple read. When the read mode is single read, the read method includes: determining the source line (e.g., the first source line SL1) of the row and the read bit line (e.g., the first read bit line RBL1) of the selected semiconductor storage unit 1 (e.g., the first row and the first column); connecting the corresponding read bit line (e.g., the first read bit line RBL1) to the external read unit, and the corresponding source line (e.g., the first source line SL1) to the ground, so that the read path of the corresponding semiconductor storage unit 1 (e.g., the first row and the first column) is turned on, and other read bit lines (e.g., the second read bit line RBL2 and the third read bit line RBL3) and source lines (e.g., the second source line SL2 and the third source line SL3) are suspended, that is, the read paths of other semiconductor storage units 1 are turned off; when the write word line controls the write switch tube 5 to turn off the main control end, the write bit line WBL and the second end of the spin-orbit moment layer 11 in all semiconductor storage units 1 are turned off, and the write paths corresponding to all semiconductor storage units 1 are turned off; thereby realizing the data reading of the selected semiconductor storage unit 1. When the reading mode is multiple reading, the reading method is the same as the control logic of single reading, which will not be repeated here.

[0097] In this way, single reading and multiple reading of the semiconductor memory array can be realized, thereby improving the flexibility of the reading method.

[0098] Combination Fig.12 As shown, an embodiment of the present disclosure provides a semiconductor storage array, comprising at least a plurality of the above-mentioned semiconductor storage structures; wherein the semiconductor storage units 1 in each semiconductor storage structure serve as a row; the write paths corresponding to each semiconductor storage unit 1 share the same write signal line; and the read paths corresponding to each semiconductor storage unit 1 share the same read signal line.

[0099] Specifically, the write signal line includes but is not limited to the write bit line WBL. The second end of the spin-track moment layer 11 in each semiconductor memory cell 1 is electrically connected to the same write bit line WBL. The read signal line includes but is not limited to the read bit line RBL. Each column of semiconductor memory cells 1 is electrically connected to the same read bit line RBL through one end of the common top electrode 2.

[0100] In the semiconductor storage array provided by the embodiment of the present disclosure, each row of semiconductor storage cells 1 shares the same top electrode 2, and each top electrode 2 is electrically connected to a read signal line, and the read signal line is electrically connected to an external read unit, so that the read path of each semiconductor storage cell 1 shares the same external read unit, thereby reducing the number of external read units and the number of read signal lines. The second end of the spin-orbit moment layer 11 of each semiconductor storage cell 1 is electrically connected to a write signal line, and the write signal line is electrically connected to an external write unit, so that the write path of each semiconductor storage cell 1 shares the same external write unit, thereby reducing the number of external write units and the number of write signal lines. By reducing the number of external read units, external write units, read signal lines, and write signal lines, it is beneficial to further save the layout area and further simplify the design process. By not sharing the signal line between the write path and the read path, the purpose of not setting the top electrode interconnection through hole 4 is achieved, which is conducive to further saving the layout area and further simplifying the process flow; preventing the write current from flowing through the read path is conducive to reducing the signal interference between the read and write operations to improve the accuracy and reliability of data reading; the read and write operations can be performed independently, avoiding the conflicts and delays that may occur when the read and write share the signal line, thereby improving the read and write speed. Figures 6 to 8 For a semiconductor memory array in a semiconductor memory array, the disclosed embodiment can greatly save the layout area and can prevent leakage current during writing from flowing into the read path through the bit line. It should be noted that the disclosed embodiment especially saves the layout area of ​​the semiconductor memory array to improve the storage density of the semiconductor memory array.

[0101] Optionally, the first end of the spin-orbit moment layer 11 of each semiconductor storage unit 1 is electrically connected to the corresponding source line, so that each semiconductor storage unit 1 uses a source line, for example, the first semiconductor storage unit uses the first source line SL1, the second semiconductor storage unit uses the second source line SL2, the third semiconductor storage unit uses the third source line SL3, the fourth semiconductor storage unit uses the fourth source line SL4, etc., which are not listed one by one here. The controlled end of the write switch tube 5 corresponding to the second end of the spin-orbit moment layer 11 of each semiconductor storage unit 1 is electrically connected to the same write bit line WBL, so that the write path of each semiconductor storage unit 1 shares the same write bit line WBL. The main control end of the write switch tube 5 of each semiconductor storage unit 1 is electrically connected to the same write word line WWL, so that each semiconductor storage unit 1 shares the same write word line WWL.

[0102] In this way, each semiconductor memory cell 1 shares the same write bit line WBL and write word line WWL, which is conducive to further reducing the number of write bit lines WBL and write word lines WWL, thereby further saving layout area and simplifying the process. Each semiconductor memory cell 1 shares the same write word line, which is conducive to simultaneously switching the write path and the read path of multiple semiconductor memory cells 1, thereby realizing the simultaneous switching of the write mode and the read mode of multiple semiconductor memory cells 1, thereby simplifying the control logic. By sharing the source line for each row and the read bit line for each column, it is conducive to selective reading and writing.

[0103] Optional, combined Fig.12 As shown, the reading and writing methods of semiconductor memory arrays are similar to Figures 6 to 8 The write logic of the semiconductor storage array in is the same. The write mode of the semiconductor storage array includes at least single write and multiple write. When the write mode is single write, its write method at least includes: the source line (for example, the first source line SL1) corresponding to the selected semiconductor storage unit 1 (for example, the first row and the first column) is connected to the external write unit, and the source lines (for example, the second source line SL2 to the fourth source line SL4) corresponding to the unselected semiconductor storage unit 1 are suspended; when the write word line WWL controls the main control end of the write switch tube 5 to be turned on, the write bit line WBL is turned on with the second end of the spin-orbit moment layer 11 of all semiconductor storage units 1, so that the write paths corresponding to all semiconductor storage units 1 are turned on; thereby realizing the data writing of the corresponding semiconductor storage unit 1. When the write mode is multiple write, it is only necessary to connect the source lines (for example, the first source line SL1 and the second source line SL2) corresponding to the multiple selected semiconductor storage units 1 to the external write unit, and the other control logic is the same as the control logic of single write, which will not be repeated here.

[0104] In this way, single writing and multiple writing of the semiconductor memory array can be realized, thereby improving the flexibility of the writing method.

[0105] Optionally, the read mode of the semiconductor storage array includes at least single read and multiple read. When the read mode is single read, the number of external read units can be set to one, so that each semiconductor storage unit 1 shares the same external read unit. Its reading method at least includes: grounding the source line (e.g., the first source line SL1) corresponding to the selected semiconductor storage unit 1 (e.g., the first row and the first column), and its read path is turned on, and the source lines corresponding to the unselected semiconductor storage units 1 are suspended (e.g., the second source line SL2 to the fourth source line SL4); when the write word line WWL controls the write switch tube 5 to turn off the main control end, the write bit line WBL and the second end of the spin-orbit moment layer 11 in all semiconductor storage units 1 are turned off, so that the write paths corresponding to all semiconductor storage units 1 are turned off; thereby realizing the data reading of the selected semiconductor storage unit 1. When the read mode is multiple reads, each semiconductor storage unit 1 can use an external read unit separately, and the read method at least includes: grounding the source lines (such as the first source line SL1 and the second source line SL2) corresponding to the selected multiple semiconductor storage units 1, so that the selected semiconductor storage unit 1 is connected to the corresponding external read unit, and other control logic is the same as the control logic of the single read, which will not be repeated here. It should be noted that the reading method of the semiconductor storage array and the setting of the external read unit can be adjusted according to the needs in the actual application process, and will not be listed one by one here.

[0106] In this way, single reading and multiple reading of the semiconductor memory array can be realized, thereby improving the flexibility of the reading method. Among them, since the same external reading unit can be shared during single reading, the layout area can be further optimized.

[0107] Combination Fig.13 As shown, an embodiment of the present disclosure provides a semiconductor storage array, comprising at least a plurality of the above-mentioned semiconductor storage structures; wherein the semiconductor storage units 1 in each semiconductor storage structure serve as a column; the write paths corresponding to each column of semiconductor storage units 1 share the same write signal line; and the read paths corresponding to each column of semiconductor storage units 1 share the same read signal line.

[0108] Specifically, the write signal line includes but is not limited to the write bit line. The second end of the spin-orbit moment layer 11 in each column of semiconductor memory cells 1 is respectively electrically connected to the corresponding same write bit line, so that each column of semiconductor memory cells 1 shares the corresponding same write bit line, for example, the first column of semiconductor memory cells 1 shares the first write bit line WBL1, the second column of semiconductor memory cells 1 shares the second write bit line WBL2, etc., which are not listed one by one here. The read signal line includes but is not limited to the read bit line. Each column of semiconductor memory cells 1 is respectively electrically connected to the corresponding same read bit line through one end of the shared top electrode 2, so that each column of semiconductor memory cells 1 shares the corresponding same read bit line, for example, the first column of semiconductor memory cells 1 shares the first read bit line RBL1, the second column of semiconductor memory cells 1 shares the second read bit line RBL2, etc., which are not listed one by one here.

[0109] In the semiconductor storage array provided by the embodiment of the present disclosure, each column of semiconductor storage units 1 shares the same top electrode 2, and each top electrode 2 is electrically connected to a corresponding read signal line, and each read signal line is electrically connected to a corresponding external read unit, so that the read path of each column of semiconductor storage units 1 shares the same external read unit, thereby reducing the number of external read units and the number of read signal lines. The second end of the spin-orbit moment layer 11 of each column of semiconductor storage units 1 is electrically connected to a corresponding write signal line, and each write signal line is electrically connected to a corresponding external write unit, so that the write path of each column of semiconductor storage units 1 shares the same external write unit, thereby reducing the number of external write units and the number of write signal lines. By reducing the number of external read units, external write units, read signal lines, and write signal lines, it is beneficial to further save the layout area and further simplify the design process. By making the write path and the read path not share the signal line, the purpose of not setting the top electrode interconnection through hole 4 is achieved, which is conducive to further saving the layout area and further simplifying the process flow; preventing the write current from flowing through the read path is conducive to reducing the signal interference between the read and write operations to improve the accuracy and reliability of data reading; the read and write operations can be performed independently, avoiding the conflicts and delays that may occur when the read and write share the signal line, thereby improving the read and write speed. In addition, when the read signal line is controlled by an external control circuit (such as a multiplexer), the current crosstalk between adjacent storage cells can be avoided, further improving the reliability. It should be noted that the embodiment of the present disclosure particularly saves the layout area of ​​the semiconductor storage array to improve the storage density of the semiconductor storage array.

[0110] Optionally, the first ends of the spin-orbit moment layers 11 of each row of semiconductor memory cells 1 are respectively electrically connected to corresponding source lines, so that each row of semiconductor memory cells 1 shares the same corresponding source line, for example, the first row of semiconductor memory cells 1 shares the first source line SL1, the second row of semiconductor memory cells 1 shares the second source line SL2, etc., which are not listed one by one here. The second ends of the spin-orbit moment layers 11 of each column of semiconductor memory cells 1 are respectively electrically connected to the same corresponding write bit line through the corresponding controlled ends of the write switch tubes 5, so that the corresponding write paths of each column of semiconductor memory cells 1 share the same corresponding write bit line, for example, the first column of semiconductor memory cells 1 shares the first write bit line WBL1, the second column of semiconductor memory cells 1 shares the second write bit line WBL2, etc., which are not listed one by one here. The main control end of the write switch tube 5 of each column of semiconductor memory cells 1 is electrically connected to the same corresponding write word line, so that each column of semiconductor memory cells 1 shares the same write word line. For example, the first column of semiconductor memory cells 1 shares the first write word line WWL1, and the second column of semiconductor memory cells 1 shares the second write word line WWL2. The examples are not listed one by one here.

[0111] In this way, the read path and the write path of each column of semiconductor memory cells 1 share the same bit line, which is conducive to reducing the number of bit lines, so as to save the number of wiring when designing the write circuit, thereby saving the layout area and simplifying the process. Each column of semiconductor memory cells 1 shares the same write word line WWL, which can simultaneously realize the switching of the write path and the read path of multiple semiconductor memory cells 1, thereby realizing the simultaneous switching of the write mode and the read mode of multiple semiconductor memory cells 1, and realizing the simplification of control logic on the basis of saving layout area and simplifying the process. Each row of semiconductor memory cells 1 shares the same corresponding source line, so that each row of semiconductor memory cells 1 corresponds to the same external read-write unit, which is conducive to reducing the number of external read-write units and further saving layout area. By sharing the source line in each row and the write word line and bit line in each column, it is conducive to selective reading and writing.

[0112] Optional, combined Fig.13 As shown, the reading and writing methods of semiconductor memory arrays are similar to Fig. 9 and Fig.10The write logic of the semiconductor storage array in is the same. The write mode of the semiconductor storage array includes at least: single write and multiple write. When the write mode is single write, its write method includes at least: determining the source line (for example, the first source line SL1) corresponding to the row where the selected semiconductor storage unit 1 (for example, the first row and the first column) is located, the write bit line (for example, the first write bit line WBL1) and the write word line (for example, the first write word line WWL1) corresponding to the column; connecting the corresponding write bit line (for example, the first write bit line WBL1) and the corresponding source line (for example, the first source line SL1) to the external write unit, and connecting other write bit lines (for example, the second write bit line WBL2) and other source lines (for example, the second source line SL2 to the fourth source line WWL1) to the external write unit. The source line SL4 is suspended; when the corresponding write word line (e.g., the first write word line WWL1) controls the main control end of the write switch tube 5 to be turned on, the corresponding write bit line (e.g., the first write bit line WBL1) is turned on with the second end of the corresponding spin-orbit moment layer 11, and different write voltages are applied to the write bit line (e.g., the first write bit line WBL1) and the source line (e.g., the first source line SL1), thereby adjusting the amplitude and direction of the write current of the write path corresponding to the selected semiconductor storage unit 1, thereby realizing the writing of the magnetic tunnel junction 12 of the selected semiconductor storage unit 1 in different directions. When the write mode is multiple write, the control logic is the same as the control logic of single write, and will not be repeated here.

[0113] In this way, single writing and multiple writing of the semiconductor storage array can be realized, thereby improving the flexibility of the writing method. Figure 7 The semiconductor memory array shown in the figure can avoid leakage current flowing into the read path through the bit line during writing because the read and write bit lines are separated in the embodiment of the present disclosure, thereby greatly improving the writing accuracy and reliability of the semiconductor memory array.

[0114] Optionally, the read bit lines of the semiconductor memory array are electrically connected to the same external read unit through a multiplexer. The read modes of the semiconductor memory array include at least: single read and multiple read. When the read mode is single read, the read method at least includes: determining the source line (e.g., the first source line SL1) corresponding to the row where the selected semiconductor storage unit 1 (e.g., the first row and the first column) is located, and the read bit line (e.g., the first read bit line RBL1) corresponding to the column where the selected semiconductor storage unit 1 is located; controlling the corresponding read bit line (e.g., the first read bit line RBL1) to be connected to the external read unit through a multiplexer, and the corresponding source line (e.g., the first source line SL1) is grounded, so that the read path corresponding to the selected semiconductor storage unit 1 is turned on, and other read bit lines (e.g., the second read bit line RBL2) and source lines (e.g., the second source line SL2 to the fourth source line SL4) are suspended, so that the read path corresponding to the unselected semiconductor storage unit 1 is turned off; when the corresponding write word line (e.g., the first write word line WWL1) controls the main control end of the write switch tube 5 to be turned off, the corresponding write bit line (e.g., the first write bit line WBL1) and the corresponding second end of the spin-track moment layer 11 are turned off, and its write path is turned off; thereby realizing the data reading of the selected semiconductor storage unit 1. When the read mode is multiple reads, the control logic is the same as the control logic for single reads, which will not be repeated here. It should be noted that the read mode of the semiconductor memory array and the setting of the external read unit can be adjusted according to needs during actual application, and will not be listed here one by one.

[0115] In this way, single reading and multiple reading of the semiconductor memory array can be realized, thereby improving the flexibility of the reading method. In particular, since each row of semiconductor memory cells 1 can share the same external reading unit during single reading, the layout area can be further optimized.

[0116] The semiconductor storage structure and array provided by the embodiments of the present disclosure can achieve the following technical effects: compared with the traditional solution of using top electrodes independently for semiconductor storage units, the embodiments of the present disclosure adopt a method in which multiple semiconductor storage units 1 share the same top electrode 2. On the one hand, each semiconductor storage unit 1 can set the same wiring between the common top electrode 2 and the substrate layer (for example, set the same top electrode interconnection through hole 4). Compared with the traditional solution of setting corresponding wiring between each top electrode 2 and the substrate layer, the embodiments of the present disclosure can reduce the number of wirings between the top electrode 2 and the substrate layer, thereby saving the layout area; on the other hand, only one wiring is set between the common top electrode 2 and the substrate layer. Compared with the traditional solution of setting wiring between each top electrode 2 and the substrate layer, the embodiments of the present disclosure do not need to set wiring in multiple places, which is conducive to simplifying the design process. In the embodiment of the present disclosure, a gating device (such as a unidirectional diode 31 or a selector 32) is arranged in the interconnection through hole between the top electrode 2 and the magnetic tunnel junction 12, so that the gating device is electrically connected to the top electrode 2 and the magnetic tunnel junction 12 respectively. On the one hand, the conventional transistor connected to the read channel is replaced by the gating device, so that the number of transistors equipped in each semiconductor storage unit 1 is reduced from two to one, which is conducive to saving the layout area of ​​the transistor layout area, thereby further saving the layout area; on the other hand, no wiring is required in the interconnection through hole between the top electrode 2 and the magnetic tunnel junction 12, which is not only conducive to further saving the layout area, but also saves a wiring process. In the embodiment of the present disclosure, the volume of the gating device arranged in the interconnection through hole between the top electrode 2 and the magnetic tunnel junction 12 is much smaller than the volume of the conventional transistor connected to the read channel, thereby further saving the layout area. By reducing the number of transistors and the number of wirings, and reducing the volume of the device electrically connected to the read channel, the layout area is saved, which is conducive to improving the storage density.

[0117] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Unless explicitly required, individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from the scope thereof.

Claims

1. A semiconductor storage structure, characterized in that: At least comprising: a plurality of semiconductor memory cells, a top electrode and a gating device corresponding to each of the semiconductor memory cells; Each of the semiconductor storage units at least comprises a spin-orbit moment layer and a magnetic tunnel junction disposed above the spin-orbit moment layer; The top electrode is located above the plurality of magnetic tunnel junctions, and the plurality of magnetic tunnel junctions share the same top electrode, and a corresponding interconnection through hole is provided between the top electrode and each of the semiconductor storage units; Each of the gating devices is respectively arranged in the corresponding interconnection through hole, and two ends of the gating device are respectively electrically connected to the corresponding magnetic tunnel junction and the top electrode.

2. The semiconductor storage structure according to claim 1, characterized in that: A corresponding writing path is formed between the first end and the second end of the spin-track moment layer in each of the semiconductor memory cells; A corresponding reading path is formed between one end of the top electrode, the gating device corresponding to each semiconductor storage unit, the corresponding magnetic tunnel junction, and the first end of the corresponding spin-orbit moment layer.

3. The semiconductor storage structure according to claim 2, characterized in that: The corresponding write path is electrically connected to a signal line through the second end of the spin-track moment layer in each semiconductor memory cell; The semiconductor storage structure further comprises at least one top electrode interconnection through hole; wherein one end of the top electrode is electrically connected to the top electrode interconnection through hole, so that a plurality of the semiconductor storage units share the same top electrode interconnection through hole; The read path corresponding to each semiconductor memory cell is electrically connected to the signal line through the top electrode interconnection via, so that the corresponding read path and the corresponding write path share the signal line.

4. The semiconductor storage structure according to claim 2, characterized in that: The corresponding write path is electrically connected to a write signal line through the second end of the spin-track moment layer corresponding to each semiconductor memory unit; The read path corresponding to each semiconductor memory cell is directly and electrically connected to a read signal line through one end of the top electrode.

5. A semiconductor storage array, characterized in that: At least: at least one top electrode interconnecting via and a plurality of semiconductor storage structures as claimed in claim 2; One end of the top electrode in each of the semiconductor storage structures is electrically connected to the top electrode interconnection through hole, so that a plurality of the semiconductor storage structures share the same top electrode interconnection through hole.

6. The semiconductor memory array according to claim 5, characterized in that: The read path and the write path corresponding to each semiconductor memory cell share the same signal line through the same top electrode interconnection through-hole.

7. A semiconductor storage array, characterized in that: At least comprising a plurality of semiconductor storage structures as claimed in claim 3; Wherein, the semiconductor storage units in each of the semiconductor storage structures serve as a column; The top electrode interconnection vias of each semiconductor memory structure allow the write path and the read path corresponding to each column of the semiconductor memory cells to share a same signal line.

8. A semiconductor storage array, characterized in that: At least comprising a plurality of semiconductor storage structures as claimed in claim 4; Wherein, the semiconductor storage units in each semiconductor storage structure serve as a column, and the semiconductor storage units in each row share the same spin-orbit moment layer; The write paths corresponding to each of the semiconductor memory cells share a same write signal line; and the read paths corresponding to each column of the semiconductor memory cells share a same read signal line.

9. A semiconductor storage array, characterized in that: At least comprising a plurality of semiconductor storage structures as claimed in claim 4; Wherein, the semiconductor storage units in each of the semiconductor storage structures serve as a row; The write paths corresponding to each of the semiconductor memory cells share a same write signal line; and the read paths corresponding to each of the semiconductor memory cells share a same read signal line.

10. A semiconductor storage array, characterized in that: At least comprising a plurality of semiconductor storage structures as claimed in claim 4; Wherein, the semiconductor storage units in each of the semiconductor storage structures serve as a column; The write paths corresponding to each column of the semiconductor memory cells share a same write signal line; the read paths corresponding to each column of the semiconductor memory cells share a same read signal line.

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