Semiconductor device

Abstract

The invention relates to a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating film, a first coil, a second coil, a third coil, a fourth coil, a first guard ring, and a second guard ring. A first coil and a second coil are formed on a semiconductor substrate. The third coil faces the first coil through the insulating film. The fourth coil faces the second coil through the insulating film. A first guard ring is formed to surround the third coil in plan view. A second guard ring is formed to surround the fourth coil in plan view. The first guard ring and the second guard ring are adjacent to each other while being spaced apart from each other in plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-192881 filed on November 13, 2023 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device. Background Art

[0004] The disclosed techniques are listed below.

[0005] [Patent Document 1] International Patent Application Publication No. WO2014 / 097425

[0006] For example, a semiconductor device is described in Patent Document 1. The semiconductor device described in Patent Document 1 includes a transformer made of a pair of coils facing each other through an insulating layer. Summary of the invention

[0007] When the transformer included in the semiconductor device described in Patent Document 1 is used as a high-voltage side transformer and a low-voltage side transformer to configure a power conversion device such as a DC to DC (direct current to direct current) converter, the withstand voltage between the high-voltage side transformer and the low-voltage side transformer is insufficient. Other problems and novel features will be apparent from the description and drawings of this specification.

[0008] A semiconductor device according to the present disclosure includes a semiconductor substrate, an insulating film, a first coil, a second coil, a third coil and a fourth coil, and a first guard ring and a second guard ring. The first coil and the second coil are formed on the semiconductor substrate. The third coil faces the first coil through the insulating film. The fourth coil faces the second coil through the insulating film. The first guard ring is formed to surround the third coil in a plan view. The second guard ring is formed to surround the fourth coil in a plan view. The first guard ring and the second guard ring are adjacent to each other and spaced apart from each other in a plan view.

[0009] In the semiconductor device according to the present disclosure, the withstand voltage between the transformer made of the first coil and the third coil and the transformer made of the second coil and the fourth coil can be ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of a semiconductor device DEV1;

[0011] Figure 2 is an explanatory diagram illustrating an example of signal transmission from the control circuit CC to the drive circuit;

[0012] Figure 3is a first plan view of the semiconductor chip CHP2;

[0013] Figure 4 is a second plan view of the semiconductor chip CHP2;

[0014] Figure 5 is a third plan view of the semiconductor chip CHP2;

[0015] Figure 6 It is along Figure 5 A cross-sectional view taken along line VI-VI shown in FIG.

[0016] Figure 7 It is along Figure 5 A cross-sectional view taken along line VII-VII shown in FIG.

[0017] Figure 8 is a plan view of a semiconductor chip CHP2 according to a first modified example;

[0018] Fig. 9 is a plan view of a semiconductor chip CHP2 according to a second modified example;

[0019] Fig.10 is a flow chart for manufacturing a semiconductor chip CHP2;

[0020] Fig.11 is a cross-sectional view for explaining the ion implantation step S2;

[0021] Fig.12 is a cross-sectional view for explaining the first insulating film forming step S3;

[0022] Fig.13 is a cross-sectional view for explaining the first via plug forming step S4;

[0023] Fig.14 is a cross-sectional view for explaining the first wiring layer forming step S5;

[0024] Fig.15 is a cross-sectional view for explaining the second insulating film forming step S6;

[0025] Fig.16 is a cross-sectional view for explaining the second via plug forming step S7;

[0026] Fig.17 is a cross-sectional view for explaining the second wiring layer forming step S8;

[0027] Fig.18 is a cross-sectional view for explaining the third insulating film forming step S9;

[0028] Fig.19is a cross-sectional view for explaining the third via plug forming step S10;

[0029] Fig. 20 is a cross-sectional view for explaining the third wiring layer forming step S11;

[0030] Fig.21 is a cross-sectional view for explaining the fourth wiring layer forming step S12;

[0031] Fig. 22 is a first plan view of the semiconductor chip CHP2 in the semiconductor device DEV2;

[0032] Fig.23 is a second plan view of the semiconductor chip CHP2 in the semiconductor device DEV2;

[0033] Fig.24 is a third plan view of the semiconductor chip CHP2 in the semiconductor device DEV2;

[0034] Fig.25 It is along Fig. 22 A cross-sectional view taken along line XXV-XXV shown in FIG.

[0035] Fig.26 is a plan view of the semiconductor chip CHP2 in the semiconductor device DEV3. DETAILED DESCRIPTION

[0036] The details of the embodiments of the present disclosure will now be described with reference to the accompanying drawings. In the drawings described below, the same or corresponding components are represented by the same reference numerals, and their overlapping descriptions will not be repeated.

[0037] (First embodiment)

[0038] The semiconductor device according to the first embodiment will be described. The semiconductor device according to the first embodiment is described as a semiconductor device DEV1.

[0039] (Configuration of semiconductor device DEV1)

[0040] The configuration of the semiconductor device DEV1 will be described below.

[0041] <Schematic Configuration of Semiconductor Device DEV1>

[0042] A schematic configuration of the semiconductor device DEV1 will be described below.

[0043] Figure 1 is a block diagram of a semiconductor device DEV1. Figure 1As illustrated, the semiconductor device DEV1 includes a semiconductor chip CHP1, a semiconductor chip CHP2, a semiconductor chip CHP3, and a semiconductor chip CHP4. The semiconductor device DEV1 configures a DC to DC converter. The semiconductor device DEV1 may configure an OBC (On-Board Charger).

[0044] The semiconductor chip CHP1 includes a control circuit CC, a transmission circuit TX1, and a transmission circuit TX2. The semiconductor chip CHP3 includes a reception circuit RX1. The semiconductor chip CHP4 includes a reception circuit RX2. The transmission circuit TX1 and the transmission circuit TX2 are electrically connected to the control circuit CC. The reception circuit RX1 and the reception circuit RX2 are electrically connected to a drive circuit not shown.

[0045] The semiconductor chip CHP2 includes a transformer TR1, a transformer TR2, and lead wirings PL1 and PL2. The transformer TR1 and the transformer TR2 are a high-voltage side transformer and a low-voltage side transformer, respectively.

[0046] The transformer TR1 includes a transmission coil CL1 and a reception coil CL3. The transmission coil CL1 includes a coil CL11 and a coil CL12, and the reception coil CL3 includes a coil CL31 and a coil CL32. The transmission coil CL1 and the reception coil CL3 are electrically connected to a transmission circuit TX1 and a reception circuit RX1, respectively.

[0047] More specifically, one end of the coil CL11 is electrically connected to the transmission circuit TX1, the other end of the coil CL11 is electrically connected to one end of the coil CL12, and the other end of the coil CL12 is electrically connected to the transmission circuit TX1. One end of the coil CL31 is electrically connected to the receiving circuit RX1, the other end of the coil CL31 is electrically connected to one end of the coil CL32 via the lead-out wiring PL1, and the other end of the coil CL32 is electrically connected to the receiving circuit RX1.

[0048] The transformer TR2 includes a transmission coil CL2 and a reception coil CL4. The transmission coil CL2 includes a coil CL21 and a coil CL22, and the reception coil CL4 includes a coil CL41 and a coil CL42. The transmission coil CL2 and the reception coil CL4 are electrically connected to the transmission circuit TX2 and the reception circuit RX2, respectively.

[0049] More specifically, one end of the coil CL21 is electrically connected to the transmission circuit TX2, the other end of the coil CL21 is electrically connected to one end of the coil CL22, and the other end of the coil CL22 is electrically connected to the transmission circuit TX2. One end of the coil CL41 is electrically connected to the receiving circuit RX2, the other end of the coil CL41 is electrically connected to one end of the coil CL42 via the lead-out wiring PL2, and the other end of the coil CL42 is electrically connected to the receiving circuit RX2.

[0050] In the semiconductor device DEV1, signals are transmitted from the control circuit CC to the drive circuit by the transmission circuit TX1, transformer TR1 and receiving circuit RX1. In the semiconductor device DEV1, signals are also transmitted from the control circuit CC to the drive circuit by the transmission circuit TX2, transformer TR2 and receiving circuit RX2.

[0051] Figure 2 1 is an explanatory diagram illustrating an example of signal transmission from the control circuit CC to the drive circuit. Figure 2 As shown, the control circuit CC inputs the signal SG1 to the transmission circuit TX1. The signal SG1 is a square wave. The transmission circuit TX1 modulates the signal SG1 into the signal SG2, and sends the signal SG2 to the transmission coil CL1. When the signal SG2 flows through the transmission coil CL1, the signal SG3 corresponding to the signal SG2 flows through the receiving coil CL3 due to the induced electromotive force. The receiving circuit RX1 amplifies the signal SG3 and demodulates the signal SG3 into the signal SG4 (square wave), and outputs the resulting signal to the drive circuit. The signal is sent from the control circuit CC to the above-mentioned drive circuit. Signal transmission using the transmission circuit TX2, the transmission coil CL2 and the receiving coil CL4 is also performed similarly. Therefore, in the semiconductor device DEV1, the signal transmission between the transmission circuit TX1 and the receiving circuit RX1 and the signal transmission between the transmission circuit TX2 and the receiving circuit RX2 are performed in the pulse communication mode.

[0052] <Detailed Configuration of Semiconductor Chip CHP2>

[0053] Figure 3 is a first plan view of the semiconductor chip CHP2. Figure 4 2 is a second plan view of the semiconductor chip CHP2. Figure 5 is a third plan view of the semiconductor chip CHP2. Figure 6 It is along Figure 5 A cross-sectional view taken along line VI-VI shown in FIG. Figure 7 It is along Figure 5 The cross-sectional view taken along the line VII-VII shown in FIG. Figures 3 to 7 As illustrated, the semiconductor chip CHP2 includes a semiconductor substrate SUB.

[0054] The semiconductor substrate SUB has a first surface FS and a second surface SS. The second surface SS is a surface opposite to the first surface FS. The first surface FS and the second surface SS are each an end surface of the semiconductor substrate USB in the thickness direction. The material configuring the semiconductor substrate SUB is, for example, single crystal silicon. The semiconductor substrate SUB includes an impurity injection region IR. The impurity injection region IR is formed at the first surface FS. The conductivity type of the semiconductor substrate SUB is, for example, a p-type. The dopant concentration in the impurity injection region IR is higher than the dopant concentration in other regions except the impurity injection region IR.

[0055] The semiconductor chip CHP2 further includes an insulating film IF1. The insulating film IF1 is arranged on the semiconductor substrate SUB. More specifically, the insulating film IF1 is arranged on the first surface FS. The material configuring the insulating film IF1 is, for example, silicon oxide.

[0056] The semiconductor chip CHP2 also includes a wiring layer WL1. The wiring layer WL1 is arranged on the insulating film IF1. The wiring layer WL1 includes wiring WL1a, wiring WL1b, wiring WL1c, and wiring WL1d. The wiring WL1a, wiring WL1b, wiring WL1c, and wiring WL1d extend along the first direction DR1 in a plan view. The material configuring the wiring layer WL1 is, for example, a conductive material containing aluminum as a main component.

[0057] The wiring layer WL1 also includes a wiring WL1e. The wiring WL1e overlaps with a guard ring GR3 described later in a plan view, although not shown. The semiconductor chip CHP2 also includes a via plug VP1. The via plug VP1 is embedded in a through hole formed in the insulating film IF1, and connects the wiring WL1e and the semiconductor substrate SUB (impurity injection region IR) to each other. The material configuring the via plug VP1 is, for example, a conductive material containing tungsten as a main component.

[0058] The semiconductor chip CHP2 further includes an insulating film IF2. The insulating film IF2 is arranged on the insulating film IF1 to cover the wiring layer WL1. The material configuring the insulating film IF2 is, for example, silicon oxide.

[0059] The semiconductor chip CHP2 also includes a wiring layer WL2. The wiring layer WL2 is arranged on the insulating film IF2. The wiring layer WL2 includes a transmission coil CL1 (coil CL11 and coil CL12), a transmission coil CL2 (coil CL21 and coil CL22), wiring WL2a, wiring WL2b, wiring WL2c and wiring WL2d. The material configuring the wiring layer WL2 is, for example, a conductive material containing aluminum as a main component.

[0060] The coil CL11 and the coil CL12 are adjacent to each other in the first direction DR1. The coil CL11 and the coil CL12 are spirally wound in a plan view. More specifically, Figure 4 In the illustrated example, coil CL11 is wound counterclockwise in a plan view from its innermost circumference toward its outermost circumference, and coil CL12 is wound spirally clockwise in a plan view from its outermost circumference toward its innermost circumference. Coil CL11 and coil CL12 are electrically connected in series with each other. More specifically, the outermost end of coil CL11 is connected to the outermost end of coil CL12.

[0061] The coil CL21 and the coil CL22 are adjacent to each other in the first direction DR1. The coil CL21 and the coil CL22 are spirally wound in a plan view. More specifically, Figure 4 In the illustrated example, coil CL21 is wound counterclockwise in a plan view from its innermost circumference toward its outermost circumference, and coil CL22 is wound spirally clockwise in a plan view from its outermost circumference toward its innermost circumference. Coil CL21 and coil CL22 are electrically connected in series with each other. More specifically, the outermost end of coil CL21 is connected to the outermost end of coil CL22.

[0062] The transmission coil CL1 and the transmission coil CL2 are adjacent to each other while being spaced apart from each other in the first direction DR1. More specifically, the coil CL12 is adjacent to the coil CL21 in the first direction DR1.

[0063] The wiring WL2a, the wiring WL2b, the wiring WL2c, and the wiring WL2d extend along the second direction DR2 in a plan view. The second direction DR2 is a direction perpendicular to the first direction DR1 in a plan view. One end of the wiring WL2a and one end of the wiring WL2b are adjacent to the coil CL11 and the coil CL12, respectively. One end of the wiring WL2c and one end of the wiring WL2d are adjacent to the coil CL21 and the coil CL22, respectively.

[0064] The wiring layer WL2 also includes a wiring WL2e. The wiring WL2e surrounds the transmission coil CL1 and the transmission coil CL2 in a plan view, and overlaps with the guard ring GR3 described later. However, the wiring WL2e does not completely surround the transmission coils CL1 and CL2, but is partially separated. The semiconductor chip CHP2 also includes a via plug VP2. The via plug VP2 is embedded in a through hole formed in the insulating film IF2, and connects the wiring WL1e and the wiring WL2e to each other. The material configuring the via plug VP2 is, for example, a conductive material containing tungsten as a main component.

[0065] The wiring WL1a is connected to the wiring WL2a and the coil CL11 through the via plug VP2. The wiring WL1b is connected to the wiring WL2b and the coil CL12 through the via plug VP2. The wiring WL1c is connected to the wiring WL2c and the coil CL21 through the via plug VP2. The wiring WL1d is connected to the wiring WL2d and the coil CL22 through the via plug VP2. The material configuring the via plug VP2 is, for example, a conductive material containing tungsten as a main component.

[0066] The semiconductor chip CHP2 further includes a plurality of insulating films IF3. The plurality of insulating films IF3 are stacked. The insulating film IF3 as the lowermost layer is arranged on the insulating film IF2 to cover the wiring layer WL2. The material configuring the insulating film IF3 is, for example, silicon oxide.

[0067] The semiconductor chip CHP2 also includes a wiring layer WL3. The wiring layer WL3 includes a receiving coil CL3 (coil CL31 and coil CL32), a receiving coil CL4 (coil CL41 and coil CL42), a lead wiring PL1, a lead wiring PL2, a guard ring GR1, a guard ring GR2, and a guard ring GR3. The material configuring the wiring layer WL3 is, for example, a conductive material containing aluminum as a main component.

[0068] The coil CL31 and the coil CL32 are adjacent to each other in the first direction DR1. The coil CL31 and the coil CL32 are spirally wound in a plan view. More specifically, Figure 5 In the illustrated example, the coil CL31 is wound counterclockwise in a plan view from its innermost circumference toward its outermost circumference, and the coil CL32 is wound spirally clockwise in a plan view from its outermost circumference toward its innermost circumference. The coil CL31 and the coil CL32 are electrically connected in series to each other via lead-out wiring PL1. More specifically, the outermost end of the coil CL31 is connected to the outermost end of the coil CL32.

[0069] The coil CL31 and the coil CL32 face the coil CL11 and the coil CL12 through the insulating film (plural insulating films IF3), respectively. Therefore, the coil CL31 and the coil CL32 are magnetically coupled to the coil CL11 and the coil CL12, respectively.

[0070] The coil CL41 and the coil CL42 are adjacent to each other in the first direction DR1. The coil CL41 and the coil CL42 are spirally wound in a plan view. More specifically, Figure 5In the illustrated example, the coil CL41 is wound counterclockwise in a plan view along a direction from its innermost circumference toward its outermost circumference, and the coil CL42 is helically wound clockwise in a plan view along a direction from its outermost circumference toward its innermost circumference. The coil CL41 and the coil CL42 are electrically connected in series with each other through the lead wiring PL2. More specifically, the end portion of the outermost circumference of the coil CL41 is connected to the end portion of the outermost circumference of the coil CL42.

[0071] The coil CL41 and the coil CL42 face the coils CL21 and CL22 through an insulating film (insulating films IF3). Accordingly, the coil CL41 and the coil CL42 are magnetically coupled to the coils CL21 and CL22, respectively. As described above, the coils CL12 and CL21 are spaced apart from each other in the first direction DR1. Accordingly, the coils CL32 and CL41 are also spaced apart from each other in the first direction DR1.

[0072] The protection ring GR1 surrounds the receiving coil CL3 in a plan view. The protection ring GR2 surrounds the receiving coil CL4 in a plan view. The protection ring GR2 is adjacent to the protection ring GR1 in the first direction DR1 while being spaced apart from the protection ring GR1. In a plan view, the protection ring GR3 surrounds the protection ring GR1 and the protection ring GR2. A first potential is applied to the protection ring GR1. A second potential is applied to the protection ring GR2. A third potential is applied to the protection ring GR3. The first potential and the second potential are higher than the third potential. The first potential is higher than the second potential. The protection rings GR1, GR2, and GR3 each have, for example, an elliptical shape in a plan view.

[0073] The shortest distance between the protection rings GR1 and GR2 in a plan view is set as the distance DIS1. The shortest distance between the protection rings GR1 and GR3 in a plan view is set as the distance DIS2. The shortest distance between the protection rings GR2 and GR3 in a plan view is set as the distance DIS3. Since the protection rings GR1 and GR2 are spaced apart from each other as described above, the distance DIS1 is greater than zero. The distance DIS1 is preferably equal to or less than the distances DIS2 and DIS3. That is, among the distances DIS1, DIS2, and DIS3, the relationships of "0 < DIS1 ≤ DIS2" and "0 < DIS1 ≤ DIS3" are preferably satisfied. The distance DIS1 is preferably equal to or greater than 15 μm. The distances DIS2 and DIS3 are each preferably equal to or greater than 150 μm.

[0074] Wiring layer WL3 also includes pads PD1, pads PD2, pads PD3, pads PD4, pads PD5 and pads PD6. Pads PD1 and PD2 are connected to the innermost end of coil CL31 and the innermost end of coil CL32, respectively. Pads PD3 and PD4 are connected to the innermost end of coil CL41 and the innermost end of coil CL42, respectively. Pads PD5 and PD6 are connected to lead-out wiring PL1 and lead-out wiring PL2, respectively. Pads PD5 are also connected to guard ring GR1, and pads PD6 are also connected to guard ring GR2.

[0075] The wiring layer WL3 further includes pads PD7, pads PD8, pads PD9, and pads PD10. Pads PD7, pads PD8, pads PD9, and pads PD10 are arranged outside the guard ring GR3 in a plan view. Pads PD7 and PD8 overlap with the other end of the wiring WL2a and the other end of the wiring WL2b in a plan view, respectively. Pads PD9 and PD10 overlap with the other end of the wiring WL2c and the other end of the wiring WL2d in a plan view, respectively.

[0076] The semiconductor chip CHP2 also includes a plurality of wiring layers WL4. Each of the plurality of wiring layers WL4 is arranged on an insulating film IF3 and covered by another insulating film IF3 arranged on the one insulating film IF3. However, the wiring layer WL4 as the lowermost layer is arranged on the insulating film IF2 and covered by the insulating film IF3 as the lowermost layer. Each of the plurality of wiring layers WL4 includes a wiring WL4a. The wiring WL4a overlaps with the guard ring GR3 in a plan view, although not shown.

[0077] The semiconductor chip CHP2 also includes a plurality of via plugs VP3. The plurality of via plugs VP3 are respectively embedded in through holes formed in the plurality of insulating films IF3. The via plugs VP3 respectively connect two overlapping wirings WL4a through the insulating film IF3, connect the wiring WL4a as the uppermost layer and the guard ring GR3, and connect the wiring WL4a as the lowermost layer and the wiring WL2e to each other.

[0078] Although not shown in the figure, pads PD7, PD8, PD9, and PD10 are electrically connected to the other end of wiring WL2a, the other end of wiring WL2b, the other end of wiring WL2c, and the other end of wiring WL2d through via plugs VP3 and multiple wiring layers WL4, respectively. Therefore, pads PD7, PD8, PD9, and PD10 are electrically connected to coils CL11, CL12, CL21, and CL22, respectively.

[0079] The semiconductor chip CHP2 also includes a passivation film PF. The passivation film PF is arranged on the insulating film IF3 as the uppermost layer to cover the wiring layer WL3. Pads PD1, pads PD2, pads PD3, pads PD4, pads PD5, pads PD6, pads PD7, pads PD8, pads PD9 and pads PD10 are exposed from the opening of the passivation film PF. The material configuring the passivation film PF is, for example, silicon nitride. Pads PD1, pads PD2, pads PD3, pads PD4, pads PD5, pads PD6, pads PD7, pads PD8, pads PD9 and pads PD10 are each used as a bonding pad for external connection.

[0080] <Modification Example of Semiconductor Chip CHP2>

[0081] A modified example of the semiconductor chip CHP2 will be described below.

[0082] Figure 8 is a plan view of a semiconductor chip CHP2 according to a first modified example. Figure 8 As illustrated, each of the guard ring GR1 and the guard ring GR2 may have a straight portion GRa. The straight portion GRa extends along the second direction DR2 in a plan view. The second direction DR2 is a direction perpendicular to the first direction DR1 in a plan view. The straight portion GRa of the guard ring GR1 and the straight portion GRa of the guard ring GR2 face each other in the first direction DR1. In the first direction DR1, the length of the straight portion GRa is preferably greater than the width of the receiving coil CL3 (coil CL31 and coil CL32) and the width of the receiving coil CL4 (coil CL41 and coil CL42). The length of the straight portion GRa in the second direction DR2 may be equal to or greater than 50 μm, for example.

[0083] Each of the guard ring GR1 and the guard ring GR2 may also have a straight portion GRb, a straight portion GRc, a corner portion GRd, a corner portion GRe, and an arc portion GRf. The straight portion GRb and the straight portion GRc extend in the first direction DR1 and face each other in the second direction DR2. One end of the straight portion GRb is connected to one end of the straight portion GRa through the corner portion GRd. One end of the straight portion GRc is connected to the other end of the straight portion GRa through the corner portion GRe. The corner portion GRd and the corner portion GRe extend in a curved shape with a predetermined curvature in a plan view. The arc portion GRf connects the other end of the straight portion GRb and the other end of the straight portion GRc to each other. The arc portion GRf has an arc shape in a plan view.

[0084] Fig. 9 is a plan view of a semiconductor chip CHP2 according to a second modified example. Fig. 9As illustrated, each of the guard ring GR1 and the guard ring GR2 does not need to include the straight line portion GRb, the straight line portion GRc, the corner portion GRd, the corner portion GRe, and the arc portion GRf. In this case, the remaining portion of each of the guard ring GR1 and the guard ring GR2 may extend while bending from one end of the straight line portion GRa to the other end. From another perspective, the remaining portion of each of the guard ring GR1 and the guard ring GR2 may have a wedge shape in a plan view.

[0085] <Method of Manufacturing Semiconductor Chip CHP2>

[0086] A method of manufacturing the semiconductor chip CHP2 will be described below.

[0087] Fig.10 1 is a flow chart for manufacturing the semiconductor chip CHP2. Fig.10 As shown, the method for manufacturing the semiconductor chip CHP2 includes a preparation step S1, an ion implantation step S2, a first insulating film forming step S3, a first via plug forming step S4, a first wiring layer forming step S5, and a second insulating film forming step S6. The method for manufacturing the semiconductor chip CHP2 also includes a second via plug forming step S7, a second wiring layer forming step S8, a third insulating film forming step S9, a third via plug forming step S10, a third wiring layer forming step S11, a fourth wiring layer forming step S12, and a passivation film forming step S13.

[0088] In the preparation step S1, a semiconductor substrate SUB is prepared. After the preparation step S1, an ion implantation step S2 is performed. Fig.11 2 is a cross-sectional view for explaining the ion implantation step S2. Fig.11 As illustrated, when ion implantation is performed in the ion implantation step S2, the impurity implantation region IR is formed. After the ion implantation step S2, the first insulating film forming step S3 is performed.

[0089] Fig.12 2 is a cross-sectional view for explaining the first insulating film forming step S3. Fig.12 As illustrated, in the first insulating film forming step S3, the insulating film IF1 is formed on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method. After the first insulating film forming step S3, the first via plug forming step S4 is performed.

[0090] Fig.13 2 is a cross-sectional view for explaining the first via plug forming step S4. Fig.13As shown, in the first via plug forming step S4, the via plug VP1 is embedded in the insulating film IF1. In the first via plug forming step S4, first, a through hole is formed in the insulating film IF1 by dry etching using a resist pattern formed by a photolithography method as a mask. Second, a material configuring the via plug VP1 is embedded in the through hole by, for example, a CVD method. Third, the material configuring the via plug VP1 protruding from the through hole is removed by, for example, a CMP (chemical mechanical polishing) method. After the first via plug forming step S4, a first wiring layer forming step S5 is performed.

[0091] Fig.14 2 is a cross-sectional view for explaining the first wiring layer forming step S5. Fig.14 As shown, in the first wiring layer forming step S5, the wiring layer WL1 is formed on the insulating film IF1. In the first wiring layer forming step S5, first, a material configuring the wiring layer WL1 is formed by, for example, a sputtering method. Second, using a resist pattern formed by a photolithography method as a mask, the material configuring the formed wiring layer WL1 is patterned by, for example, dry etching. After the first wiring layer forming step S5, a second insulating film forming step S6 is performed.

[0092] Fig.15 2 is a cross-sectional view for explaining the second insulating film forming step S6. Fig.15 As shown, in the second insulating film forming step S6, an insulating film IF2 is formed on the insulating film IF1 to cover the wiring layer WL1. In the second insulating film forming step S6, first, a material configuring the insulating film IF2 is formed by, for example, a CVD method. Second, the material configuring the formed insulating film IF2 is flattened by, for example, a CMP method. After the second insulating film forming step S6, a second via plug forming step S7 is performed.

[0093] Fig.16 2 is a cross-sectional view for explaining the second via plug forming step S7. Fig.16 As illustrated, in the second via plug forming step S7, the via plug VP2 is embedded in the insulating film IF2 by a method similar to that in the first via plug forming step S4. After the second via plug forming step S7, the second wiring layer forming step S8 is performed.

[0094] Fig.17 2 is a cross-sectional view for explaining the second wiring layer forming step S8. Fig.17As shown, in the second wiring layer forming step S8, the wiring layer WL2 is formed on the insulating film IF2. In the second wiring layer forming step S8, first, a material configuring the wiring layer WL2 is formed by, for example, sputtering. Second, using a resist pattern formed by a photolithography method as a mask, the material configuring the formed wiring layer WL2 is patterned by, for example, dry etching. After the second wiring layer forming step S8, a third insulating film forming step S9 is performed.

[0095] Fig.18 2 is a cross-sectional view for explaining the third insulating film forming step S9. Fig.18 As illustrated, in the third insulating film forming step S9, the insulating film IF3 is formed on the insulating film IF2 to cover the wiring layer WL2. After the third insulating film forming step S9, the third via plug forming step S10 is performed.

[0096] Fig.19 2 is a cross-sectional view for explaining the third via plug forming step S10. Fig.19 As illustrated, in the third via plug forming step S10, the via plug VP3 is embedded in the insulating film IF3 by a method similar to that in the second via plug forming step S7. After the third via plug forming step S10, the third wiring layer forming step S11 is performed.

[0097] Fig. 20 2 is a cross-sectional view for explaining the third wiring layer forming step S11. Fig. 20 As shown, in the third wiring layer forming step S11, the wiring layer WL4 is formed by a method similar to that in the second wiring layer forming step S8. Before forming the insulating film IF3 as the uppermost layer, the third insulating film forming step S9, the third via plug forming step S10, and the third wiring layer forming step S11 are repeated. After forming the insulating film IF3 as the uppermost layer, the fourth wiring layer forming step S12 is performed.

[0098] Fig.21 2 is a cross-sectional view for explaining the fourth wiring layer forming step S12. Fig.21 As illustrated, in the fourth wiring layer forming step S12, the wiring layer WL3 is formed on the insulating film IF3 as the uppermost layer by a method similar to that in the second wiring layer forming step S8. After the fourth wiring layer forming step S12, a passivation film forming step S13 is performed.

[0099] In the passivation film forming step S13, the passivation film PF is formed on the insulating film IF3 as the uppermost layer to cover the wiring layer WL4. In the passivation film forming step S13, first, a material configuring the passivation film PF is formed by, for example, a CVD method. Second, using a resist pattern formed by a photolithography method as a mask, the material configuring the passivation film PF is patterned by, for example, dry etching.

[0100] When block division is performed by cutting or the like after the aforementioned steps, the Figures 3 to 7 The structure of the semiconductor chip CHP2 is shown.

[0101] <Effect of semiconductor device DEV1>

[0102] Next, the effects of the semiconductor device DEV1 will be described.

[0103] In the semiconductor device DEV1, the transformer TR1 and the transformer TR2 are used as a high voltage side transformer and a low voltage side transformer, respectively. Therefore, it is necessary to ensure the withstand voltage between the transformer TR1 and the transformer TR2.

[0104] In the semiconductor chip CHP2, the receiving coil CL3 (coil CL31 and coil CL32) is surrounded by the guard ring GR1 in a plan view, and the receiving coil CL4 (coil CL41 and coil CL42) is surrounded by the guard ring GR2 in a plan view. Therefore, in the semiconductor chip CHP2, the potential difference between the receiving coils CL3 and CL4 and their periphery (specifically, the potential difference between the receiving coils CL3 and CL4 and the guard ring GR3) is stabilized. Therefore, according to the semiconductor device DEV1 including the semiconductor chip CHP2, the withstand voltage between the transformer TR1 and the transformer TR2 can be ensured.

[0105] The problem between the receiving coils CL3 and CL4 and the guard ring GR3 (between the guard rings GR1 and GR2 and the guard ring GR3) is the withstand voltage for alternating current, and the distance DIS2 and the distance DIS3 are set to meet the withstand voltage. The problem between the receiving coil CL3 and the receiving coil CL4 (between the guard ring GR1 and the guard ring GR2) is the withstand voltage for direct current, and the withstand voltage can be guaranteed even if the distance DIS1 is smaller than the distance DIS2 and the distance DIS3. Therefore, when the relationship of "0<distance DIS1≤distance DIS2" and the relationship of "0<distance DIS1≤distance DIS3" are met, the semiconductor chip CHP2 can be reduced in size while ensuring the desired withstand voltage.

[0106] When each of the guard ring GR1 and the guard ring GR2 includes the straight line portion GRa, it is difficult to form a singular point where the electric field is concentrated between the guard ring GR1 and the guard ring GR2. Therefore, in this case, even if the distance DIS1 is small, the withstand voltage between the guard ring GR1 and the guard ring GR2 (between the receiving coil CL3 and the receiving coil CL4) can be increased, so that the semiconductor chip CHP2 can be reduced.

[0107] In the semiconductor device DEV1, the distance between the transmission coil CL2 and the reception coil CL4 is greater than the distance in the semiconductor device DEV2 described later. This means that the capacitance caused by the transmission coil CL2, the reception coil CL4, and the insulating film between the transmission coil CL2 and the reception coil CL4 is reduced. The smaller the above capacitance, the more the common mode transient immunity (CMTI) is improved. Therefore, according to the semiconductor device DEV1, the CMTI can be improved.

[0108] (Second embodiment)

[0109] A semiconductor device according to a second embodiment will be described. The semiconductor device according to the second embodiment is described as a semiconductor device DEV2. Here, differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions thereof will not be repeated.

[0110] (Configuration of semiconductor device DEV2)

[0111] The configuration of the semiconductor device DEV2 will be described below.

[0112] The semiconductor device DEV2 includes a semiconductor chip CHP1, a semiconductor chip CHP2, a semiconductor chip CHP3, and a semiconductor chip CHP4. In this respect, the configuration of the semiconductor device DEV2 is common to the configuration of the semiconductor device DEV1.

[0113] Fig. 22 is a first plan view of the semiconductor chip CHP2 in the semiconductor device DEV2. Fig.23 is a second plan view of the semiconductor chip CHP2 in the semiconductor device DEV2. Fig.24 is a third plan view of the semiconductor chip CHP2 in the semiconductor device DEV2. Fig.25 It is along Fig. 22 A cross-sectional view taken along line XXV-XXV shown in FIG. Figures 22 to 25As shown, in the semiconductor chip CHP2 in the semiconductor device DEV2, one wiring layer WL4 includes a receiving coil CL4 (coil CL41 and coil CL42), a guard ring GR2, a pad PD3, a pad PD4, and a pad PD6. In the semiconductor chip CHP2 in the semiconductor device DEV2, another wiring layer WL4 includes wiring WL4a, wiring WL4b, and wiring WL4c. In the semiconductor chip CHP2 in the semiconductor device DEV2, the wiring layer WL3 also includes pads PD11, pads PD12, and pads PD13.

[0114] From another perspective in this regard, when it is assumed that the insulating film IF3 between the transmission coil CL2 and the receiving coil CL4 is set as the first insulating film, and the collective insulating film IF3 other than the first insulating film is set as the second insulating film, only the first insulating film is inserted between the transmission coil CL2 and the receiving coil CL4, and both the first insulating film and the second insulating film are inserted between the transmission coil CL1 and the receiving coil CL3. The transformer TR2 is a low-voltage side transformer, and therefore, even if the thickness of the insulating film between the transmission coil CL2 and the receiving coil CL4 is small, the withstand voltage between the transmission coil CL2 and the receiving coil CL4 can be ensured.

[0115] In the semiconductor chip CHP2 in the semiconductor device DEV2, the wiring WL4a is a guard ring GR4 surrounding the guard ring GR2 in a plan view. When the shortest distance between the guard ring GR2 and the guard ring GR4 in a plan view is described as a distance DIS4, it is preferable to satisfy the relationship of "distance DIS1 ≤ distance DIS4". For example, the wiring layer WL4 including the receiving coil CL4, the guard ring GR2 and the guard ring GR4 is the wiring layer WL4 used as the lowest layer.

[0116] The wiring layer WL4 including the wiring WL4b, the wiring WL4c and the wiring WL4d is located on a layer above the wiring layer WL4 including, for example, the receiving coil CL4, the guard ring GR2 and the guard ring GR4. The wiring WL4b, the wiring WL4c and the wiring WL4d extend along the second direction DR2 in a plan view. One end of the wiring WL4b and one end of the wiring WL4c overlap with the pad PD3 and the pad PD4 in a plan view. One end of the wiring WL4d overlaps with the pad PD6 in a plan view. The other end of the wiring WL4b and the other end of the wiring WL4c overlap with the pad PD11 and the pad PD12 in a plan view. The other end of the wiring WL4d overlaps with the pad PD13 in a plan view. The pads PD11, the pads PD12 and the pads PD13 are arranged outside the guard ring GR3 in a plan view.

[0117] The pads PD11, PD12, and PD13 are electrically connected to the pads PD3, PD4, and PD6 through the via plugs VP3 and the plurality of wiring layers WL4, respectively. That is, in the semiconductor chip CHP2 in the semiconductor device DEV2, the pads PD3, PD4, and PD6 are not used as bonding pads for external connection because they are not located on the wiring layer as the uppermost layer, and are pulled upward to the pads PD11, PD12, and PD13 located on the wiring layer as the uppermost layer through the wiring layer (wiring WL4b, wiring WL4c, and wiring WL4d) located one layer above. Then, the pads PD11, PD12, and PD13 are used as bonding pads. Note that the semiconductor chip CHP2 in the semiconductor device DEV2 may not include the guard ring GR2. In these aspects, the configuration of the semiconductor device DEV2 is different from the configuration of the semiconductor device DEV1.

[0118] <Effect of semiconductor device DEV2>

[0119] Next, the effects of the semiconductor device DEV2 will be described.

[0120] In the semiconductor chip CHP2 in the semiconductor device DEV2, the receiving coil CL3 and the receiving coil CL4 are respectively formed on different wiring layers. Therefore, in the semiconductor device DEV2, even if the distance DIS1 is small, the distance required to ensure the withstand voltage can be ensured between the receiving coil CL3 and the receiving coil CL4, and the chip size of the semiconductor chip CHP2 (more specifically, the size in the first direction DR1) can be reduced.

[0121] (Third Embodiment)

[0122] A semiconductor device according to a third embodiment will be described. The semiconductor device according to the third embodiment is described as a semiconductor device DEV3. Here, the difference from the semiconductor device DEV2 will be mainly described, and the overlapping description thereof will not be repeated.

[0123] (Configuration of semiconductor device DEV3)

[0124] The configuration of the semiconductor device DEV3 will be described below.

[0125] The semiconductor device DEV3 includes a semiconductor chip CHP1, a semiconductor chip CHP2, a semiconductor chip CHP3, and a semiconductor chip CHP4. In this respect, the configuration of the semiconductor device DEV3 is common to the configuration of the semiconductor device DEV2.

[0126] Fig.26 FIG. 1 is a plan view of the semiconductor chip CHP2 in the semiconductor device DEV3. Fig.26As shown, in the semiconductor chip CHP2 in the semiconductor device DEV3, the width of the coil CL41 and the width of the coil CL42 in the first direction DR1 are smaller than the width of the coil CL31 and the width of the coil CL32 in the first direction DR1. In the semiconductor chip CHP2 in the semiconductor device DEV3, the width of the coil CL41 and the width of the coil CL42 in the second direction DR2 are also smaller than the width of the coil CL31 and the width of the coil CL32 in the second direction DR2. Similarly, in the semiconductor chip CHP2 in the semiconductor device DEV3, the width of the coil CL21 and the width of the coil CL22 in the first direction DR1 are smaller than the width of the coil CL11 and the width of the coil CL12 in the first direction DR1, and the width of the coil CL21 and the width of the coil CL22 in the second direction DR2 are also smaller than the width of the coil CL11 and the width of the coil CL12 in the second direction DR2.

[0127] In the semiconductor chip CHP2 in the semiconductor device DEV3, note that the pads PD3 and the pads PD4 are not used as bonding pads, but their sizes can be reduced. Therefore, in the semiconductor chip CHP2 in the semiconductor device DEV3, the size of the coil CL41 (coil CL42) can be made smaller than the coil CL31 (coil CL32) while maintaining the number of windings. However, in the semiconductor chip CHP2 in the semiconductor device DEV3, when the number of windings of the coil CL41 (coil CL42) is made smaller than the number of windings of the coil CL31 (coil CL32), the corresponding width of the coil CL41 (coil CL42) can be made smaller than the corresponding width of the coil CL31 (coil CL32) in the first direction DR1 and the second direction DR2. In these aspects, the configuration of the semiconductor device DEV3 is different from the configuration of the semiconductor device DEV2.

[0128] <Effect of semiconductor device DEV3>

[0129] Next, the effects of the semiconductor device DEV3 will be described.

[0130] In the semiconductor chip CHP2 in the semiconductor device DEV2, the thickness of the insulating film interposed between the transmission coil CL2 and the reception coil CL4 is smaller than the thickness of the semiconductor chip CHP2 in the semiconductor device DEV1. Therefore, the capacitance caused by the transmission coil CL2, the reception coil CL4, and the insulating film interposed therebetween increases, and therefore, there is a risk of reduced CMTI.

[0131] Even in the semiconductor chip CHP2 in the semiconductor device DEV3, the thickness of the insulating film interposed between the transmission coil CL2 and the reception coil CL4 is equal to the thickness of the semiconductor chip CHP2 in the semiconductor device DEV2. However, in the semiconductor chip CHP2 in the semiconductor device DEV3, since the respective sizes of the transmission coil CL2 and the reception coil CL4 are small, the capacitance caused by the transmission coil CL2, the reception coil CL4, and the insulating film interposed therebetween is reduced. Therefore, according to the semiconductor device DEV3, the CMTI in the transformer TR2 can be improved, while the size of the semiconductor chip CHP2 can be reduced.

[0132] (appendix)

[0133] Embodiments of the present disclosure include the following configurations.

[0134] <Appendix 1>

[0135] A semiconductor device comprising:

[0136] Semiconductor substrate;

[0137] Insulating film;

[0138] a first coil, a second coil, a third coil, a fourth coil, a fifth coil, a sixth coil, a seventh coil, and an eighth coil; and

[0139] a first guard ring and a second guard ring;

[0140] The first coil, the second coil, the third coil and the fourth coil are formed on a semiconductor substrate,

[0141] The first coil and the second coil are electrically connected in series with each other,

[0142] The third coil and the fourth coil are electrically connected in series with each other,

[0143] The fifth coil faces the first coil through the insulating film,

[0144] The sixth coil faces the second coil through the insulating film,

[0145] The seventh coil faces the third coil through the insulating film,

[0146] The eighth coil faces the fourth coil through the insulating film,

[0147] The fifth coil and the sixth coil are electrically connected in series with each other,

[0148] The seventh coil and the eighth coil are electrically connected in series with each other,

[0149] The first guard ring is formed to surround the fifth coil and the sixth coil in a plan view,

[0150] A second guard ring is formed to surround the seventh coil and the eighth coil in a plan view, and

[0151] The first guard ring and the second guard ring are adjacent to each other while being spaced apart from each other in a plan view.

[0152] <Appendix 2>

[0153] In the semiconductor device described in statement 1,

[0154] The first coil and the second coil are arranged side by side along a first direction in a plan view,

[0155] Each of the first guard ring and the second guard ring has a first straight line portion extending in a second direction perpendicular to the first direction, and

[0156] The first straight portion of the first guard ring is arranged to face the first straight portion of the second guard ring.

[0157] <Appendix 3>

[0158] In the semiconductor device described in statement 2,

[0159] The first straight portion has a first end and a second end on an opposite side of the first end, and

[0160] The remaining portion of each of the first guard ring and the second guard ring extends from the first end to the second end while being bent in a plan view.

[0161] <Appendix 4>

[0162] In the semiconductor device described in statement 2,

[0163] The first straight portion has a first end and a second end on an opposite side of the first end,

[0164] Each of the first guard ring and the second guard ring further has a second straight line portion, a third straight line portion, a first corner portion, a second corner portion, and an arc portion,

[0165] The second straight line portion and the third straight line portion extend in the first direction and face each other in the second direction,

[0166] The second straight line portion has a third end and a fourth end on an opposite side of the third end,

[0167] the third straight line portion has a fifth end and a sixth end on an opposite side of the fifth end,

[0168] The first corner portion connects the third end and the first end,

[0169] The second corner portion connects the fifth end and the second end,

[0170] The first corner portion and the second corner portion extend in a curved shape in a plan view, and

[0171] The arc portion connects the fourth end and the sixth end, and extends in an arc shape in a plan view.

[0172] <Appendix 5>

[0173] In the semiconductor device described in statement 2, a length of the first straight line portion in the second direction is equal to or larger than a width of the third coil and a width of the fourth coil therein.

[0174] <Appendix 6>

[0175] In the semiconductor device described in statement 5, a length of the first straight line portion in the second direction is equal to or greater than 50 μm.

[0176] <Appendix 7>

[0177] In the semiconductor device described in statement 1, the third coil, the fourth coil, the first guard ring, and the second guard ring are formed in the same layer in the cross-sectional view.

[0178] <Appendix 8>

[0179] The semiconductor device described in statement 1 further includes a third guard ring,

[0180] The third guard ring is formed to surround the first guard ring and the second guard ring in a plan view.

[0181] <Appendix 9>

[0182] In the semiconductor device described in statement 8, the first distance which is the shortest distance between the first guard ring and the second guard ring in a plan view is smaller than the second distance which is the shortest distance between the first guard ring and the third guard ring in a plan view and the third distance which is the shortest distance between the second guard ring and the third guard ring in a plan view.

[0183] <Appendix 10>

[0184] In the semiconductor device described in statement 9,

[0185] The first distance is equal to or greater than 15 μm, and

[0186] Each of the second distance and the third distance is equal to or greater than 50 μm.

[0187] <Addendum 11>

[0188] In the semiconductor device described in statement 8, each of a first voltage applied to the first guard ring and a second voltage applied to the second guard ring is higher than a third voltage applied to the third guard ring.

[0189] <Addendum 12>

[0190] In the semiconductor device described in statement 1,

[0191] The first coil and the third coil configure a high-voltage side transformer when magnetically coupled, and

[0192] The second coil and the fourth coil configure a low voltage side transformer when magnetically coupled.

[0193] <Appendix 13>

[0194] A semiconductor device comprising:

[0195] Semiconductor substrate;

[0196] a first insulating film, a second insulating film, and a third insulating film;

[0197] a first wiring layer, a second wiring layer, and a third wiring layer;

[0198] a first coil, a second coil, a third coil, a fourth coil, a fifth coil, a sixth coil, a seventh coil, and an eighth coil; and

[0199] a first guard ring and a second guard ring;

[0200] A first insulating film is formed on a semiconductor substrate,

[0201] A first wiring layer is formed on the first insulating film,

[0202] A second insulating film is formed on the first insulating film to cover the first wiring layer,

[0203] A second wiring layer is arranged on the second insulating film,

[0204] A third insulating film is formed on the second insulating film to cover the second wiring layer,

[0205] A third wiring layer is formed on the third insulating film,

[0206] The first coil, the second coil, the third coil and the fourth coil are formed in a first wiring layer,

[0207] The fifth coil and the sixth coil are formed in the third wiring layer,

[0208] The seventh coil and the eighth coil are formed in the second wiring layer,

[0209] The first coil and the second coil face the fifth coil and the sixth coil through the second insulating film and the third insulating film, respectively.

[0210] The third coil and the fourth coil face the seventh coil and the eighth coil respectively through the second insulating film,

[0211] The first guard ring is formed to surround the fifth coil and the sixth coil in a plan view,

[0212] A second guard ring is formed to surround the seventh coil and the eighth coil in a plan view, and

[0213] The first guard ring and the second guard ring are adjacent to each other while being spaced apart from each other in a plan view.

[0214] <Addendum 14>

[0215] A semiconductor device comprising:

[0216] a first semiconductor chip;

[0217] a second semiconductor chip;

[0218] a third semiconductor chip; and

[0219] a fourth semiconductor chip,

[0220] The first semiconductor chip includes a first transmission circuit and a second transmission circuit,

[0221] The second semiconductor chip includes a first transformer on the high voltage side and a second transformer on the low voltage side,

[0222] The third semiconductor chip includes a first receiving circuit,

[0223] The fourth semiconductor chip includes a second receiving circuit,

[0224] The signal transmitted by the first transmission circuit is transmitted to the first receiving circuit via the first transformer in the pulse communication mode,

[0225] The signal transmitted by the second transmission circuit is transmitted to the second receiving circuit via the second transformer in the pulse communication mode,

[0226] The third semiconductor chip includes a semiconductor substrate, an insulating film, a first coil, a second coil, a third coil, a fourth coil, a first guard ring, and a second guard ring.

[0227] The first coil and the second coil are formed on a semiconductor substrate,

[0228] The third coil faces the first coil through the insulating film,

[0229] The fourth coil faces the second coil through the insulating film,

[0230] The first coil and the third coil configure a first transformer when magnetically coupled,

[0231] The second coil and the fourth coil configure a second transformer when magnetically coupled, and

[0232] The first guard ring is formed to surround the third coil in a plan view,

[0233] A second guard ring is formed to surround the fourth coil in a plan view, and

[0234] The first guard ring and the second guard ring are adjacent to each other while being spaced apart from each other in a plan view.

[0235] In the foregoing, the invention made by the inventors of the present application has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the foregoing embodiments, and various modifications can be made within the scope of the present invention.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; Insulating film; a first coil, a second coil, a third coil, and a fourth coil; as well as a first guard ring and a second guard ring; wherein the first coil and the second coil are formed on the semiconductor substrate, wherein the third coil faces the first coil through the insulating film, wherein the fourth coil faces the second coil through the insulating film, wherein the first guard ring is formed to surround the third coil in a plan view, wherein the second guard ring is formed to surround the fourth coil in a plan view, and The first guard ring and the second guard ring are adjacent to each other and are spaced apart from each other in a plan view.

2. The semiconductor device according to claim 1, wherein the first coil and the second coil are arranged side by side along a first direction in a plan view, wherein each of the first guard ring and the second guard ring has a first straight line portion extending in a second direction perpendicular to the first direction, and The first straight line portion of the first guard ring is arranged to face the first straight line portion of the second guard ring.

3. The semiconductor device according to claim 2, wherein the first straight portion has a first end and a second end, the second end being on an opposite side of the first end, and wherein a remaining portion of each of the first guard ring and the second guard ring extends from the first end to the second end while being curved in a plan view.

4. The semiconductor device according to claim 2, wherein the first straight portion has a first end and a second end, the second end being on an opposite side of the first end, wherein each of the first guard ring and the second guard ring further comprises a second straight line portion, a third straight line portion, a first corner portion, a second corner portion and an arc portion, wherein the second straight line portion and the third straight line portion extend in the first direction and face each other in the second direction, wherein the second straight line portion has a third end and a fourth end, the fourth end being on the opposite side of the third end, wherein the third straight line portion has a fifth end and a sixth end, the sixth end being on the opposite side of the fifth end, wherein the first corner portion connects the third end and the first end, wherein the second corner portion connects the fifth end and the second end, wherein the first corner portion and the second corner portion extend in a curved shape in a plan view, and The arc portion connects the fourth end and the sixth end and extends in an arc shape in a plan view.

5. The semiconductor device according to claim 2, In the second direction, the length of the first straight line portion is equal to or greater than the width of the third coil and the width of the fourth coil.

6. The semiconductor device according to claim 5, The length of the first straight line portion in the second direction is equal to or greater than 50 μm.

7. The semiconductor device according to claim 1, The third coil, the fourth coil, the first guard ring, and the second guard ring are formed in the same layer in a cross-sectional view.

8. The semiconductor device according to claim 1, further comprising: The third protection ring, The third guard ring is formed to surround the first guard ring and the second guard ring in a plan view.

9. The semiconductor device according to claim 8, Wherein a first distance being the shortest distance between the first guard ring and the second guard ring in a plan view is smaller than a second distance being the shortest distance between the first guard ring and the third guard ring in a plan view and a third distance being the shortest distance between the second guard ring and the third guard ring in a plan view.

10. The semiconductor device according to claim 9, wherein the first distance is equal to or greater than 15 μm, and Wherein each of the second distance and the third distance is equal to or greater than 50 μm.

11. The semiconductor device according to claim 8, Wherein each of a first voltage applied to the first guard ring and a second voltage applied to the second guard ring is higher than a third voltage applied to the third guard ring.

12. The semiconductor device according to claim 1, wherein the first coil and the third coil configure a high-voltage side transformer when magnetically coupled, and The second coil and the fourth coil configure a low-voltage side transformer when magnetically coupled.

13. A semiconductor device comprising: Semiconductor substrate; a first insulating film, a second insulating film, and a third insulating film; a first wiring layer, a second wiring layer, and a third wiring layer; a first coil, a second coil, a third coil, and a fourth coil; and a first guard ring and a second guard ring, wherein the first insulating film is formed on the semiconductor substrate, wherein the first wiring layer is formed on the first insulating film, wherein the second insulating film is formed on the first insulating film to cover the first wiring layer, wherein the second wiring layer is arranged on the second insulating film, wherein the third insulating film is formed on the second insulating film to cover the second wiring layer, wherein the third wiring layer is formed on the third insulating film, wherein the first coil and the second coil are formed in the first wiring layer, wherein the third coil is formed in the third wiring layer, wherein the fourth coil is formed in the second wiring layer, wherein the first coil and the third coil face each other through the second insulating film and the third insulating film, wherein the second coil and the fourth coil face each other through the second insulating film, wherein the first guard ring is formed to surround the third coil in a plan view, wherein the second guard ring is formed to surround the fourth coil in a plan view, and The first guard ring and the second guard ring are adjacent to each other and are spaced apart from each other in a plan view.

14. The semiconductor device according to claim 13, wherein the first guard ring is formed in the third wiring layer, and The second guard ring is formed in the second wiring layer.

15. The semiconductor device according to claim 13, further comprising: The third protection ring, The third guard ring is formed to surround the first guard ring and the second guard ring in a plan view.

16. The semiconductor device according to claim 15, Wherein a first distance being the shortest distance between the first guard ring and the second guard ring in a plan view is smaller than a second distance being the shortest distance between the first guard ring and the third guard ring in a plan view and a third distance being the shortest distance between the second guard ring and the third guard ring in a plan view.

17. The semiconductor device according to claim 16, wherein the first distance is equal to or greater than 15 μm, and Wherein each of the second distance and the third distance is equal to or greater than 50 μm.

18. The semiconductor device according to claim 13, wherein the first coil and the second coil are arranged side by side along a first direction in a plan view, wherein in the first direction, the width of the second coil and the width of the fourth coil are smaller than the width of the first coil and the width of the third coil, and In a second direction perpendicular to the first direction, a width of the second coil and a width of the fourth coil in the second direction perpendicular to the first direction are smaller than a width of the first coil and a width of the third coil in the second direction.

19. The semiconductor device according to claim 13, The number of windings of the second coil and the number of windings of the fourth coil are smaller than the number of windings of the first coil and the number of windings of the third coil.

20. A semiconductor device comprising: a first semiconductor chip; a second semiconductor chip; a third semiconductor chip; as well as a fourth semiconductor chip, The first semiconductor chip includes a first transmission circuit and a second transmission circuit, The second semiconductor chip includes a first transformer on the high voltage side and a second transformer on the low voltage side, The third semiconductor chip includes a first receiving circuit. wherein the fourth semiconductor chip comprises a second receiving circuit, wherein the signal transmitted by the first transmission circuit is transmitted to the first receiving circuit via the first transformer, wherein the signal transmitted by the second transmission circuit is transmitted to the second receiving circuit via the second transformer, The third semiconductor chip includes a semiconductor substrate, an insulating film, a first coil, a second coil, a third coil, a fourth coil, a first guard ring and a second guard ring. wherein the first coil and the second coil are formed on the semiconductor substrate, wherein the third coil faces the first coil through the insulating film, wherein the fourth coil faces the second coil through the insulating film, wherein the first coil and the third coil configure the first transformer when magnetically coupled, wherein the second coil and the fourth coil configure the second transformer when magnetically coupled, and wherein the first guard ring is formed to surround the third coil in a plan view, wherein the second guard ring is formed to surround the fourth coil in a plan view, and The first guard ring and the second guard ring are adjacent to each other and are spaced apart from each other in a plan view.

Images