A forward conducting voltage drop positive temperature characteristic FRD process control method

Abstract

The present application relates to the technical field of semiconductor device manufacturing, in particular to a forward conduction voltage drop positive temperature characteristic FRD process control method, comprising the following steps: S1, ring base area process, S2, cut-off ring process, S3, contact hole process, S4, platinum sputtering, S5, platinum gold doping failure suppression process, S6, metallization, S7, irradiation treatment, S8, back thinning, S9, back gold process, by accurately controlling the process steps, especially the injection dose of boron ions, the diffusion conditions of the platinum gold layer and the comprehensive application of electron irradiation, the method can ensure that the FRD has the optimized performance of the forward conduction voltage drop approximately zero temperature or positive temperature characteristic, this characteristic makes the forward conduction voltage drop of the diode can be kept in a relatively stable range when the working temperature rises, or can be increased with the temperature rise, thereby improving the current conduction capacity and thermal stability of the parallel device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, specifically to a method for controlling the forward conduction voltage drop to a positive temperature characteristic in FRD process. Background Technology

[0002] Fast recovery diodes (FRDs) are key components in power electronic devices, and their performance is crucial to the efficiency and reliability of the system. However, traditional FRDs suffer from a decrease in forward voltage drop as temperature increases under high-temperature operating conditions, which severely affects the performance and stability of the device in parallel applications.

[0003] In traditional technologies, the forward voltage drop characteristic of a forward voltage regulator (FRD) typically decreases with increasing temperature. This characteristic can cause a series of problems at high temperatures, such as directional increase in current density and thermal runaway, which can severely impact the stability and lifespan of the device. To address this issue, the industry has been exploring how to develop an FRD whose forward voltage drop increases with increasing temperature, ensuring excellent performance under various operating temperature conditions.

[0004] Carrier lifetime is one of the key factors affecting the reverse recovery time and forward conduction voltage drop of an FRD. While existing technologies employ methods such as platinum killing (Pt) or irradiation to modulate carrier lifetime, these methods either result in high leakage current affecting reliability or exhibit negative temperature characteristics, making it difficult to achieve ideal temperature characteristics and high reliability requirements. This means that in practical applications, the performance of FRDs is often limited by carrier lifetime modulation techniques.

[0005] Furthermore, existing FRD manufacturing processes also face numerous challenges. From high-energy ion implantation and chemical vapor deposition (CVD) to sputtering and electron irradiation, each step requires precise parameter control to ensure the performance of the final product. However, existing processes still have room for improvement in certain aspects, such as optimizing doping concentration, enhancing breakdown voltage, and metallization and contact treatment, all of which require further research and refinement.

[0006] Meanwhile, the heat dissipation and soldering interface design on the back side of the wafer are also important factors affecting device reliability and application range. The shortcomings of traditional processes in these areas impose many limitations on the practical application of FRDs. Summary of the Invention

[0007] Technical problems to be solved

[0008] To address the shortcomings of existing technologies, this invention provides an FRD process control method with a positive temperature characteristic for forward conduction voltage drop.

[0009] (II) Technical Solution

[0010] To achieve the above objectives, the present invention provides the following technical solution: A method for controlling an FRD process with a positive temperature characteristic forward conduction voltage drop, comprising the following steps:

[0011] S1, ring base region process

[0012] A window is formed on the high-resistivity epitaxial layer of the chip by photolithography, and boron ions are implanted using high-energy ion implantation technology;

[0013] S2, Cut-off Ring Process

[0014] Phosphorus oxychloride is deposited in the chip terminal region using chemical vapor deposition to form a cutoff ring;

[0015] S3, Contact Hole Process

[0016] The base region window of the chip is opened by photolithography to facilitate subsequent contact metallization processing;

[0017] S4, Platinum Sputtering

[0018] A platinum layer with a thickness of 300~500 Å is formed in the active region of the chip using a sputtering device. The platinum layer is used to achieve subsequent platinum diffusion processing.

[0019] S5, Platinum Doping Failure Suppression Process

[0020] The chip is placed in a high-temperature environment of 860~930°C, and platinum atoms are diffused into the Si epitaxial layer using a semiconductor-specific diffusion furnace.

[0021] S6, Metallized

[0022] A metal layer is formed in the active region of the chip using evaporation and photolithography processes.

[0023] S7, Irradiation treatment

[0024] The chip is penetrated by a high-energy electron beam with electron beam penetration parameters of 8~40 KGy and annealed at 280°C~350°C. The high-energy electron beam is further modulated by electron irradiation technology.

[0025] S8, thinner back panel

[0026] Grind excess substrate material from the chip to reduce thermal resistance;

[0027] S9, Gold Backing Process

[0028] An evaporation technique is used to form a TiNiAg alloy layer on the back side of the wafer to provide good heat dissipation and a good soldering interface.

[0029] Preferably, in step S1, the resistivity of the high-resistivity epitaxial layer is 10~100 Ω·cm; and in step S2, the temperature range of the chemical vapor deposition is 800~950°C.

[0030] More preferably, in step S5 and step S7, the dose of the high-energy electron beam is 8~40KGy, and the annealing temperature is 280°C~350°C.

[0031] Preferably, in step S8, the thickness of the polished wafer is 200 μm to 300 μm; and in step S9, the thickness of the TiNiAg alloy layer is 1 to 5 μm.

[0032] Preferably, the following additional steps are also included:

[0033] S10. Testing and Screening: Conduct electrical performance tests on the FRDs that have completed all the above process steps, and screen out qualified products that meet the positive temperature characteristic of forward conduction voltage drop.

[0034] S11. Packaging: The qualified FRDs are packaged to ensure their reliability and stability in practical applications.

[0035] More preferably, in step S2, the stop ring process further includes annealing after POCl3 deposition, wherein the diffusion temperature is 800~950°C and the annealing time is 10~50 minutes.

[0036] Preferably, in step S4, the formation of the platinum layer further includes pre-treatment of the active region surface before sputtering, and the pre-treatment includes either cleaning treatment or activation treatment; in step S5, the platinum doping failure suppression process further includes pre-oxidation treatment before diffusion, wherein the pre-oxidation temperature is 800~900°C and the time is 10~30 minutes.

[0037] Preferably, in step S7, the irradiation treatment further includes annealing after electron irradiation, wherein the temperature range is 280°C to 350°C.

[0038] (III) Beneficial Effects

[0039] Compared with the prior art, the present invention provides an FRD process control method with a positive temperature characteristic for forward conduction voltage drop, which has the following beneficial effects:

[0040] Optimized forward conduction characteristics: By precisely controlling the process steps, especially the boron ion implantation dose, the diffusion conditions of the platinum layer, and the comprehensive application of electron irradiation, this method can ensure that the FRD has optimized performance with a forward conduction voltage drop of near zero temperature or positive temperature. This characteristic allows the diode to maintain its forward conduction voltage drop within a relatively stable range as the temperature rises, and it can also increase with the temperature, thereby improving the current conduction capability and thermal stability of parallel devices.

[0041] Improved reverse withstand voltage performance: Specific processing techniques, such as chemical vapor deposition to form a cutoff ring, effectively enhance the reverse withstand voltage reliability of the FRD. This allows the diode to operate more reliably under reverse voltage, reducing the risk of device failure due to voltage breakdown.

[0042] Fast Reverse Recovery Capability: Due to the use of special platinum layer diffusion and irradiation processes, this method enables the FRD to have fast reverse recovery capability. This means that when the diode switches from the forward conducting state to the reverse blocking state, its recovery time is greatly shortened, thereby improving the overall response speed and efficiency of the circuit.

[0043] Enhancing Reliability and Stability: The entire process control methodology emphasizes detailed optimization and precise control, including additional steps such as testing and screening, and packaging, ensuring the reliability and stability of the FRD in practical applications. This enables the diode to operate stably for extended periods in various harsh environments, reducing maintenance costs and failure rates.

[0044] In summary, this FRD process control method with a positive temperature characteristic forward conduction voltage drop significantly improves the performance and reliability of FRDs by precisely controlling process steps and optimizing device structure, providing strong support for the application of high-frequency and high-power electronic circuits. Attached Figure Description

[0045] Figure 1 This is a schematic diagram outlining the process flow of the present invention;

[0046] Figure 2 This is a schematic diagram showing the key process steps of the present invention;

[0047] Figure 3 This is a schematic diagram of the additional processing steps of the present invention. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] Please see Figure 1-3 The present invention provides a method for controlling an FRD process with a positive forward conduction voltage drop and a positive temperature characteristic, comprising the following steps:

[0050] S1, ring base region process

[0051] A window is formed on the high-resistivity epitaxial layer of the chip by photolithography, and boron ions are implanted using high-energy ion implantation technology;

[0052] S2, Cut-off Ring Process

[0053] Phosphorus oxychloride is deposited in the chip terminal region using chemical vapor deposition to form a cutoff ring;

[0054] S3, Contact Hole Process

[0055] The base region window of the chip is opened by photolithography to facilitate subsequent contact metallization processing;

[0056] S4, Platinum Sputtering

[0057] A platinum layer with a thickness of 300~500 Å is formed in the active region of the chip using a sputtering device. The platinum layer is used to achieve subsequent platinum diffusion processing.

[0058] S5, Platinum Doping Failure Suppression Process

[0059] The chip is placed in a high-temperature environment of 860~930°C, and platinum atoms are diffused into the Si epitaxial layer using a semiconductor-specific diffusion furnace.

[0060] S6, Metallized

[0061] A metal layer is formed in the active region of the chip using evaporation and photolithography processes.

[0062] S7, Irradiation treatment

[0063] The chip is penetrated by a high-energy electron beam with electron beam penetration parameters of 8~40 KGy and annealed at 280°C~350°C. The high-energy electron beam is further modulated by electron irradiation technology.

[0064] S8, thinner back panel

[0065] Grind excess substrate material from the chip to reduce thermal resistance;

[0066] S9, Gold Backing Process

[0067] A TiNiAg alloy layer is formed on the back side of the wafer using an evaporation technique.

[0068] This method of controlling the forward conduction voltage drop with a positive temperature characteristic (FRD) provides a fast recovery diode (FRD) for use as a freewheeling diode in insulated gate bipolar field-effect transistors (IGBTs). Through a series of precise process steps, it ensures that the FRD exhibits the characteristic that the forward conduction voltage drop increases with increasing temperature. The core working principle includes:

[0069] Carrier lifetime regulation:

[0070] Platinum doping failure suppression technology (Pt killing) and electron irradiation technology are used to precisely control carrier lifetime, thereby affecting the reverse recovery time and forward conduction voltage drop of the device.

[0071] Doping concentration optimization:

[0072] By implanting boron ions with high-energy ions, the doping concentration in the base region is optimized, thereby improving electrical properties.

[0073] Improved pressure resistance:

[0074] A cutoff ring is formed in the terminal region to improve the edge withstand voltage performance of the device.

[0075] Metallization and contact optimization:

[0076] To ensure a good current transmission path and electrical connection, a base region window is opened by photolithography, and a metal layer is formed in the active region.

[0077] Heat dissipation and soldering interface:

[0078] A TiNiAg alloy layer is evaporated on the back side of the wafer to provide good heat dissipation and a good welding interface.

[0079] Working principles of various preferred technical solutions

[0080] Ring-based region process (S1)

[0081] Working principle: A window is formed by photolithography, and boron ions are implanted using high-energy ion implantation technology to optimize the doping concentration of the base region and adjust the resistivity to improve electrical properties.

[0082] Preferred parameters: the resistivity of the high-resistivity epitaxial layer is 10~100 Ω·cm; the implantation depth is 0.5~2 μm.

[0083] Cut-off ring process (S2)

[0084] Working principle: Phosphoryl chloride (POCl3) is deposited in the terminal area using chemical vapor deposition (CVD) technology to form a stop ring, thereby enhancing the edge pressure resistance.

[0085] Preferred parameters: After POCl3 deposition, annealing is performed at a temperature of 900~1000°C for 30~60 minutes.

[0086] Contact hole process (S3)

[0087] Working principle: The base region window is opened by photolithography to ensure good electrical connection for subsequent contact metallization.

[0088] Platinum sputtering (S4)

[0089] Working principle: A platinum layer with a thickness of 300~500 Å is formed in the active region using sputtering equipment to prepare for subsequent platinum diffusion treatment.

[0090] Platinum doping failure suppression process (S5)

[0091] Working principle: The FRD is placed in a high-temperature environment of 860°C~930°C, and a semiconductor-specific diffusion furnace is used to diffuse platinum atoms into the Si substrate, which shortens the carrier lifetime and improves the reverse recovery speed.

[0092] Preferred parameters: diffusion time is 30~60 minutes; pre-oxidation treatment is performed before diffusion, with a pre-oxidation temperature of 800~900°C and a time of 10~30 minutes.

[0093] Metallization (S6)

[0094] Working principle: A metal layer is formed in the active region of the FRD using deposition and photolithography processes to ensure a good current transmission path.

[0095] Irradiation treatment (S7)

[0096] Working principle: High-energy electron beams are used to penetrate the FRD, adjust the carrier lifetime, and further enhance the stability and reliability of the device.

[0097] Preferred parameters: electron beam dose of 8~40KGy; annealing treatment after irradiation at a temperature range of 280°C~350°C.

[0098] Backside thinning (S8)

[0099] Working principle: Grinding excess substrate material in the FRD reduces thermal resistance and optimizes device performance.

[0100] Preferred parameters: The thickness of the polished wafer is 200 μm to 300 μm;

[0101] Gold backing technique (S9)

[0102] Working principle: An evaporation technology is used to form a TiNiAg alloy layer on the back of the wafer, providing good heat dissipation and a good soldering interface.

[0103] Preferred parameters: TiNiAg alloy layer thickness is 1~5 μm; pre-plating treatment is performed before evaporation, such as titanium undercoating.

[0104] Detailed Workflow

[0105] S1, ring base region process

[0106] On the high-resistivity epitaxial layer of the chip, a window is formed by photolithography, and boron ions are implanted using high-energy ion implantation technology with an implantation dose of 1e15~5e12.

[0107] S2, Cut-off Ring Process

[0108] Phosphorus oxychloride (POCl3) is deposited in the chip terminal area using chemical vapor deposition (CVD) technology to form a stop ring;

[0109] S3, Contact Hole Process

[0110] The base region window of the chip is opened by photolithography to facilitate subsequent contact metallization processing;

[0111] S4, Platinum Sputtering

[0112] A platinum layer with a thickness of 300~500 Å is formed in the active region of the chip using a sputtering device. The platinum layer is used to realize the subsequent Pt diffusion process.

[0113] S5, Platinum Doping Failure Suppression Process

[0114] The chip is placed in a high-temperature environment of 860~930°C, and platinum atoms are diffused into the Si epitaxial layer using a semiconductor-specific diffusion furnace.

[0115] S6, Metallized

[0116] Evaporation and photolithography processes are used to form a metal layer in the active region of the chip to ensure a good current transport path;

[0117] S7, Irradiation treatment

[0118] The chip is penetrated by a high-energy electron beam with electron beam penetration parameters of 8~40 KGy and annealed at 280°C~350°C. The high-energy electron beam is further modulated by electron irradiation technology.

[0119] S8, thinner back panel

[0120] Grinding excess substrate material from the chip reduces thermal resistance and optimizes device performance.

[0121] S9, Gold Backing Process

[0122] An evaporation technique is used to form a TiNiAg alloy layer on the back side of the wafer to provide good heat dissipation and a good soldering interface.

[0123] S10, Testing and Screening

[0124] The chips that have completed all the above process steps are subjected to electrical performance tests, and qualified products that meet the characteristic that the forward conduction voltage drop is positive at a certain temperature are selected.

[0125] S11, Packaging

[0126] The qualified FRDs are packaged to ensure their reliability and stability in practical applications.

[0127] Summarize

[0128] This invention discloses a process control method for FRD (Front Conductor Dropout) with positive temperature characteristics. Through a series of precise process steps, it ensures the excellent performance of the FRD under different temperature conditions. The key technical point lies in the combined use of global Pt lifetime control technology and global irradiation lifetime control technology to precisely regulate carrier lifetime. Furthermore, the specific parameters and sequence of each step constitute an important part of the patent protection. In addition, the additional testing, screening, and packaging steps further guarantee the reliability and stability of the product.

[0129] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for controlling an FRD process with a positive temperature characteristic forward conduction voltage drop, characterized in that, Includes the following steps: S1, ring base region process A window is formed on the high-resistivity epitaxial layer of the chip by photolithography, and boron ions are implanted using high-energy ion implantation technology; S2, Cut-off Ring Process Phosphorus oxychloride is deposited in the chip terminal region using chemical vapor deposition to form a cutoff ring; S3, Contact Hole Process The base region window of the chip is opened by photolithography to facilitate subsequent contact metallization processing; S4, Platinum Sputtering A platinum layer with a thickness of 300~500 Å is formed in the active region of the chip using a sputtering device. The platinum layer is used to achieve subsequent platinum diffusion processing. S5, Platinum Doping Failure Suppression Process The chip is placed in a high-temperature environment of 860~930°C, and platinum atoms are diffused into the Si epitaxial layer using a semiconductor-specific diffusion furnace. S6, Metallized A metal layer is formed in the active region of the chip using evaporation and photolithography processes. S7, Irradiation treatment The chip is penetrated by a high-energy electron beam with electron beam penetration parameters of 8~40 KGy and annealed at 280°C~350°C. The high-energy electron beam is further modulated by electron irradiation technology. S8, thinner back panel Grind excess substrate material from the chip to reduce thermal resistance; S9, Gold Backing Process A TiNiAg alloy layer is formed on the back side of the wafer using an evaporation technique.

2. The FRD process control method with positive temperature characteristics for forward conduction voltage drop as described in claim 1, characterized in that, In step S1, the resistivity of the high-resistivity epitaxial layer is 10~100 Ω·cm; in step S2, the temperature range of the chemical vapor deposition is 800~950°C.

3. The FRD process control method with positive temperature characteristics for forward conduction voltage drop according to claim 2, characterized in that, In step S7, the dose of the high-energy electron beam is 8~40KGy, and the annealing temperature is 280°C~350°C.

4. The FRD process control method with positive temperature characteristics for forward conduction voltage drop as described in claim 3, characterized in that, In step S8, the thickness of the polished wafer is 200~300 μm; in step S9, the thickness of the TiNiAg alloy layer is 1~5 μm.

5. The FRD process control method with positive temperature characteristics for forward conduction voltage drop according to claim 4, characterized in that, It also includes the following additional steps: S10. Testing and Screening: Conduct electrical performance tests on the FRDs that have completed all the above process steps, and screen out qualified products that meet the positive temperature characteristic of forward conduction voltage drop. S11. Packaging: The qualified FRDs are packaged to ensure their reliability and stability in practical applications.

6. The FRD process control method with positive temperature characteristics for forward conduction voltage drop according to claim 5, characterized in that, In step S2, the stop ring process further includes annealing after POCl3 deposition, wherein the diffusion temperature is 800~950°C and the annealing time is 10~50 minutes.

7. The FRD process control method with positive temperature characteristics for forward conduction voltage drop according to claim 6, characterized in that, In step S4, the formation of the platinum layer further includes pre-treatment of the active region surface before sputtering, and the pre-treatment includes either cleaning treatment or activation treatment; in step S5, the platinum doping failure suppression process further includes pre-oxidation treatment before diffusion, wherein the pre-oxidation temperature is 800~900°C and the time is 10~30 minutes.

8. The FRD process control method with positive temperature characteristics for forward conduction voltage drop according to claim 7, characterized in that, In step S7, the irradiation treatment further includes annealing after electron irradiation, wherein the temperature range is 280°C to 350°C.

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