SiC triode applied to integrated circuit and preparation method thereof

Abstract

The invention discloses a SiC triode applied to an integrated circuit. The SiC triode comprises a SiC substrate, a P-type epitaxial layer located on the SiC substrate and an N-type drift layer located on the P-type epitaxial layer. The P-type epitaxial layer is used as a first RESUEF region; a base region and a collector region are respectively formed on two sides of the N-type drift layer; a floating ring of which the distance is gradually increased is formed between the base region and the collector region; the floating ring is used as a second RESUEF region; an emitter region and a base region ohmic contact region are respectively formed on two sides of the base region; metal electrodes are arranged on the collector region, the base region ohmic contact region and the emitter region; surface passivation layers are connected between the collector and the base and between the base and the emitter; and a surface grid electrode is arranged on the surface passivation layer between the base electrode and the emitter electrode. The invention further discloses a preparation method of the SiC triode applied to the integrated circuit. The floating ring structure and the P-type epitaxial layer form a double-RESUEF structure, so that the breakdown voltage of the device is improved, and meanwhile, the condition that the electric field concentration is borne by the last ring can be effectively relieved.

Description

Technical Field

[0001] The present invention relates to the technical field of BJT devices, and in particular to a SiC triode applied to an integrated circuit and a preparation method thereof. Background Art

[0002] BJT is the abbreviation of Bipolar Junction Transistor, also known as triode. In recent years, with the continuous development of microelectronics technology, third-generation wide bandgap semiconductors such as SiC have gradually developed. Compared with Si, SiC materials have the advantages of wide bandgap, large thermal conductivity, large electron saturation drift velocity, and high breakdown electric field. In theory, SiC devices can withstand high temperatures of 600°C, which can well meet the application requirements of T>300°C. In addition, the thermal conductivity of SiC materials is high, which facilitates heat transfer in devices and helps to increase the working environment temperature of devices. In addition, SiC devices have a very high switching frequency, which helps to reduce the volume, weight and cost of the system. Moreover, under the same voltage level, the on-resistance of SiC devices is small, which helps to reduce losses and improve system efficiency.

[0003] The current integrated circuits have higher and higher requirements for integration, high speed, and low power consumption. Although traditional bipolar technology has natural advantages in high speed and strong driving capability, with the advancement of technology, its disadvantages in integration have become more and more obvious, and power consumption has always been a pain point for bipolar technology. Therefore, MOS devices have gradually developed. MOS devices and their circuits have unmatched advantages over bipolar devices in terms of high integration, low power consumption, and anti-interference capabilities, but they are not as good as bipolar devices in terms of high speed and strong driving capabilities. Therefore, a new technology that combines the advantages of the two technologies, namely BiCMOS devices and their circuits, has naturally developed.

[0004] However, the existing lateral BJT devices have a low breakdown voltage, and are therefore rarely used in power devices, and there is currently no better structure to increase the breakdown voltage. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a SiC triode for integrated circuits and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] A first aspect of an embodiment of the present invention provides a SiC triode applied to an integrated circuit, comprising: a SiC substrate, a P-type epitaxial layer located on the SiC substrate, and an N-type drift layer located on the P-type epitaxial layer; the P-type epitaxial layer serves as a first RESUEF region;

[0007] A base region and a collector region are formed on both sides of the N-type drift layer by ion implantation;

[0008] A floating ring is formed on the N-type drift layer between the base region and the collector region by ion implantation, the spacing of which gradually increases from the base region to the collector region; the doping concentration of the floating ring is 1e18-5e19; the floating ring serves as a second RESUEF region;

[0009] An emitter region and a base region ohmic contact region are formed on both sides of the base region by ion implantation;

[0010] The collector region, the base region ohmic contact region and the emitter region are provided with a collector electrode, a base electrode and an emitter electrode;

[0011] A surface passivation layer is connected between the collector and the base, and between the base and the emitter respectively;

[0012] A surface gate is arranged on the surface passivation layer between the base and the emitter.

[0013] In one embodiment of the present invention, the base region is formed by P-type ion implantation.

[0014] In one embodiment of the present invention, the floating ring is formed by P-type ion implantation.

[0015] In one embodiment of the present invention, the emitter region is formed by N-type ion implantation.

[0016] In one embodiment of the present invention, the collector region is formed by N-type ion implantation.

[0017] A second aspect of an embodiment of the present invention provides a method for preparing a SiC triode for use in an integrated circuit, comprising the following steps:

[0018] Step 1, epitaxially growing a P-type epitaxial layer on a SiC substrate, and then epitaxially growing an N-type drift layer on the P-type epitaxial layer; the P-type epitaxial layer serves as a first RESUEF region;

[0019] Step 2, performing ion implantation on one side of the N-type drift layer to form a base region;

[0020] Step 3, ion implantation is performed on one side of the base region and the N-type drift layer on one side of the base region to form a base region ohmic contact region and a floating ring with gradually increasing spacing; the doping concentration of the floating ring is 1e18-5e19; the floating ring serves as a second RESUEF region;

[0021] Step 4, performing ion implantation on the other side of the base region to form an emitter region;

[0022] Step 5, performing ion implantation on the N-type drift layer on one side of the floating ring to form a collector region; wherein the floating ring is located between the base region and the collector region, and the distance between two adjacent floating rings gradually increases from the base region toward the collector region;

[0023] Step 6, forming a passivation layer on the surface of the product manufactured in step 5, and then etching the passivation layer to form ohmic contact windows on the collector region, the base ohmic contact region and the emitter region, forming ohmic contacts on the ohmic contact windows, and forming a surface passivation layer between the ohmic contact window of the collector region and the ohmic contact window of the base ohmic contact region, and between the ohmic contact window of the base ohmic contact region and the ohmic contact window of the emitter region;

[0024] Step seven, preparing a collector, a base and an emitter at positions corresponding to the ohmic contact window, and preparing a surface gate on the surface passivation layer between the ohmic contact window of the base ohmic contact region and the ohmic contact window of the emitter region.

[0025] In one embodiment of the present invention, the specific steps of step 1 include:

[0026] The SiC substrate is placed in a MOCVD reaction chamber to epitaxially grow an epitaxial layer, and P-type doping is performed to form a P-type epitaxial layer. A drift layer is grown on the P-type epitaxial layer, and N-type doping is performed to form an N-type drift layer.

[0027] In one embodiment of the present invention, the specific steps of step 2 include:

[0028] P-type ion implantation is performed on one side of the N-type drift layer to form a base region.

[0029] In one embodiment of the present invention, the specific steps of step three include:

[0030] P-type ion implantation is performed on one side of the base region and the N-type drift layer on one side of the base region to form a base region ohmic contact region and a floating ring with gradually increasing spacing.

[0031] In one embodiment of the present invention, the specific steps of step 4 include:

[0032] Performing N-type ion implantation on the other side of the base region to form an emitter region;

[0033] The specific steps of step five include:

[0034] N-type ion implantation is performed in the N-type drift layer at one side of the floating ring to form a collector region.

[0035] Beneficial effects of the present invention:

[0036] The present invention reduces the surface electric field of the device by epitaxially growing a layer of P-type epitaxial layer as a RESUEF region, thereby improving the breakdown voltage of the device. The surface passivation layer is deposited between the base contact point and the emitter contact point to improve the current gain as much as possible, and a surface gate is deposited on the surface passivation layer. The surface gate applies a negative potential to the deposited surface passivation layer, which reduces the depletion region of the non-intrinsic part of the base region formed due to the deposition of the surface passivation layer. Therefore, compared with the structure in which only the surface passivation layer is deposited, the effective base thickness of the structure in which the surface gate is deposited is increased, thereby improving the breakdown voltage. In addition, the present invention increases the spacing of the floating rings in sequence to form a floating ring structure with a gradient spacing, and forms a double RESUEF structure with the P-type epitaxial layer, which can effectively alleviate the situation where the electric field concentration is borne by the last ring while improving the breakdown voltage of the device.

[0037] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0038] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0040] Figure 1 A schematic diagram of the structure of a SiC triode applied to an integrated circuit provided by an embodiment of the present invention;

[0041] Figure 2 A schematic flow chart of a method for preparing a SiC triode for use in an integrated circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0043] like Figure 1As shown, the first aspect of the embodiment of the present invention provides a SiC triode applied to an integrated circuit, comprising: a SiC substrate 1, a P-type epitaxial layer 2 located on the SiC substrate 1, and an N-type drift layer 3 located on the P-type epitaxial layer 2; the P-type epitaxial layer 2 serves as a first RESUEF region. A base region 5 and a collector region 4 are formed on both sides of the N-type drift layer 3 by ion implantation. The base region 5 and the collector region 4 are spaced apart and located on both sides of the N-type drift layer 3.

[0044] On the N-type drift layer 3 between the base region 5 and the collector region 4, floating rings 13 are formed by ion implantation, with the spacing gradually increasing from the base region 5 to the collector region 4; the doping concentration of the floating rings 13 is 1e18-5e19; the floating rings 13 serve as the second RESUEF region. Here, the plurality of floating rings 13 are spaced apart, and the spacing gradually increases from S1 to Sn.

[0045] An emitter region 7 and a base ohmic contact region 6 are formed on both sides of the base region 5 by ion implantation. There is a gap between the emitter region 7 and the base ohmic contact region 6. A collector 11, a base 9 and an emitter 10 are arranged on the collector region 4, the base ohmic contact region 6 and the emitter region 7; a surface passivation layer 8 is connected between the collector 11 and the base 9, and between the base 9 and the emitter 10. The surface passivation layer 8 is located on the surface of the N-type drift layer 3 between the base 9 and the emitter 10 and on the floating ring 13, and a surface gate 12 is arranged on the surface passivation layer 8 on the base region 5 between the base 9 and the emitter 10. There is a gap between the surface gate 12 and the base 9 and the emitter 10.

[0046] The base region 5 is formed by P-type ion implantation. The floating ring 13 is formed by P-type ion implantation. The emitter region 7 is formed by N-type ion implantation. The collector region 4 is formed by N-type ion implantation.

[0047] In this embodiment, a layer of P-type epitaxial layer 2 is epitaxially grown as a RESUEF region, which reduces the surface electric field of the device, thereby improving the breakdown voltage of the device. At the same time, by introducing a high-doped region of opposite conductivity type on the surface of the N-type drift region, a floating ring 13 is formed to reduce the surface electric field and improve the breakdown characteristics. Here, the P-type epitaxial layer 2 and the floating ring 13 form a double-layer RESUEF structure, which further reduces the surface electric field strength and improves the breakdown voltage. At the same time, the spacing between the floating rings 13 is increased from S1 to Sn in sequence, which can effectively alleviate the situation where the electric field concentration is borne by the last ring.

[0048] In addition, the surface passivation layer 8 is deposited between the contact point of the base 9 and the contact point of the emitter 10, so as to increase the current gain as much as possible, and at the same time, a surface gate 12 is deposited on the surface passivation layer 8. The surface gate 12 applies a negative potential to the deposited surface passivation layer 8, which reduces the depletion region of the non-intrinsic part of the base region 5 formed due to the deposition of the surface passivation layer 8. Therefore, relative to the structure in which only the surface passivation layer 8 is deposited, the effective thickness of the base 9 of the structure in which the surface gate 12 is deposited is increased, thereby increasing the breakdown voltage.

[0049] like Figure 2 As shown, the second aspect of the embodiment of the present invention provides a method for preparing a SiC triode applied to an integrated circuit, which is used to prepare the SiC triode of the first aspect of the embodiment of the present invention, comprising the following steps:

[0050] Step 1: epitaxially grow a P-type epitaxial layer 2 on a SiC substrate 1 , and then epitaxially grow an N-type drift layer 3 on the P-type epitaxial layer 2 .

[0051] The P-type epitaxial layer 2 serves as the first RESUEF region.

[0052] Step 2: perform ion implantation on one side of the N-type drift layer 3 to form a base region 5 .

[0053] Step three, ion implantation is performed on one side of the base region 5 and the N-type drift layer 3 on one side of the base region 5 to form a base ohmic contact region 6 and floating rings 13 with gradually increasing spacing.

[0054] The doping concentration of the floating ring 13 is 1e18-5e19; the floating ring 13 serves as a second RESUEF region.

[0055] Step 4: perform ion implantation on the other side of the base region 5 to form an emitter region 7.

[0056] Step five: ion implantation is performed on the N-type drift layer 3 on one side of the floating ring 13 to form a collector region 4 .

[0057] The floating ring 13 is located between the base region 5 and the collector region 4 , and the distance between two adjacent floating rings 13 gradually increases from the base region 5 toward the collector region 4 .

[0058] Step six, forming a passivation layer on the surface of the product completed in step five, and then etching the passivation layer to form ohmic contact windows on the collector region 4, the base ohmic contact region 6 and the emitter region 7, forming an ohmic contact on the ohmic contact window, and forming a surface passivation layer 8 between the ohmic contact window of the collector region 4 and the ohmic contact window of the base ohmic contact region 6, and between the ohmic contact window of the base ohmic contact region 6 and the ohmic contact window of the emitter region 7.

[0059] Step seven, prepare a collector 11, a base 9 and an emitter 10 at positions corresponding to the ohmic contact windows, and prepare a surface gate 12 on the surface passivation layer 8 between the ohmic contact window of the base ohmic contact region 6 and the ohmic contact window of the emitter region 7.

[0060] The above preparation method is further described in detail below:

[0061] Step S21, fine processing is performed on the single crystal SiC substrate 1, including cutting, grinding and polishing, etc., to obtain a flat and defect-free surface. Before growing the epitaxial layer, the surface of the SiC substrate 1 needs to be thoroughly cleaned to remove the oxide layer and impurities on the surface to ensure good bonding between the epitaxial layer and the substrate.

[0062] Step S22, epitaxially growing a P-type epitaxial layer 2 on the SiC substrate 1, and then epitaxially growing an N-type drift layer 3 on the P-type epitaxial layer 2; the P-type epitaxial layer 2 serves as a first RESUEF region.

[0063] Specifically, the SiC substrate 1 is placed in a MOCVD reaction chamber to epitaxially grow an epitaxial layer and perform P-type doping to form a P-type epitaxial layer 2 , and a drift layer 3 is grown on the P-type epitaxial layer 2 and performed N-type doping to form an N-type drift layer 3 .

[0064] The MOCVD process can precisely control the doping concentration by controlling the gas flow and reaction chamber conditions. Common doping sources include nitrogen (N2) as an N-type dopant and titanium tetrachloride (TiCl4) as a P-type dopant. By adjusting the flow of these gases, the molar flow of dopants entering the reaction chamber can be controlled, thereby controlling the doping concentration in the SiC. The doping concentration of the P-type epitaxial layer 2 is 1e15-1e16.

[0065] Step S23 , performing P-type ion implantation on one side of the N-type drift layer 3 to form a base region 5 .

[0066] Specifically, first, a layer of metal or other material is deposited on the surface of the product manufactured in the previous step as an ion implantation barrier layer, and then a window pattern of the base region 5 to be implanted with ions is obtained by mask photolithography transfer on one side of the N-type drift layer 3, and then the excess mask barrier material is etched away to form an ion implantation barrier window, and then ion implantation is performed under appropriate conditions, thereby increasing the doping concentration of the base 9 contact region, facilitating the formation of ohmic contact and reducing contact resistance. For the N-type region, phosphorus (P) is usually used as a donor element.

[0067] In step S24, P-type ion implantation is performed on one side of the base region 5 and the N-type drift layer 3 on one side of the base region 5 to form a base region ohmic contact region 6 and floating rings 13 with gradually increasing spacing; the doping concentration of the floating rings 13 is 1e18-5e19; the floating rings 13 serve as the second RESUEF region.

[0068] Specifically, first, a layer of metal or other material is deposited on the surface of the product made in the previous step as an ion implantation barrier layer, and then the window pattern for ion implantation of the base ohmic contact region 6 and the floating ring 13 is obtained by mask photolithography transfer on one side of the base region 5 and the N-type drift layer 3 on one side of the base region 5, and then the excess mask barrier material is etched away to form an ion implantation barrier window, and then ion implantation is performed under appropriate conditions, thereby increasing the doping concentration of the base 9 contact region, facilitating the formation of ohmic contact and reducing contact resistance. For the N-type region, phosphorus (P) is usually used as a donor element. The base ohmic contact region 6 is located in the base region 5, and the floating ring 13 is located outside the base region 5.

[0069] Step S25 , performing N-type ion implantation on the other side of the base region 5 to form an emitter region 7 .

[0070] Specifically, a layer of metal or other material is deposited on the surface of the product prepared in the previous step as an ion implantation barrier layer, and then the window pattern of the emitter region 7 for N-type ion implantation is obtained by mask photolithography transfer on the other side of the base region 5, and then the excess mask barrier material is etched away to form an ion implantation barrier window, and then ion implantation is performed under appropriate conditions, thereby increasing the doping concentration of the base 9 contact area, facilitating the formation of ohmic contact and reducing contact resistance. For the P-type region, aluminum (Al) is usually used as the acceptor element. The emitter region 7 is located in the base region 5, and is spaced apart from the base region ohmic contact region 6. The base region ohmic contact region 6 is located between the emitter region 7 and the floating ring 13.

[0071] Step S26 , performing N-type ion implantation on the N-type drift layer 3 on one side of the floating ring 13 to form a collector region 4 ; wherein the floating ring 13 is located between the base region 5 and the collector region 4 , and the distance between two adjacent floating rings 13 gradually increases from the base region 5 toward the collector region 4 .

[0072] Specifically, a layer of metal or other material is deposited on the surface of the product prepared in the previous step as an ion implantation barrier layer, and then a window pattern for ion implantation in the collector region 4 is obtained by mask photolithography transfer, and then the excess mask barrier material is etched away to form an ion implantation barrier window, and then ion implantation is performed under appropriate conditions, thereby increasing the doping concentration of the base 9 contact region, facilitating the formation of ohmic contact and reducing contact resistance. For the P-type region, aluminum (Al) is usually used as the acceptor element.

[0073] Step S27, after ion implantation, since the high-energy implanted ions form many tiny defects in the crystal, the implanted atoms do not properly occupy the lattice position, so the resistance of the implanted area is high. For the SiC wafer undergoing ion implantation, high-temperature (usually above 1700°C) activation annealing is performed in an inert gas atmosphere to form p-type and n-type low-resistance areas.

[0074] Step S28, forming a passivation layer on the surface of the product manufactured in the previous step.

[0075] Silicon dioxide is deposited by plasma chemical vapor deposition (PECVD) and annealed in an atmosphere of 1100° C. to form a passivation layer between the base region 5 and the collector region 4 and between the base region 5 and the collector region 4 .

[0076] Step S29, first obtain the front P-type ohmic contact window pattern on the base ohmic contact area 6 through mask plate photolithography transfer, then etch away the excess sacrificial oxide layer and passivation layer to form a P-type ohmic contact window, then deposit contact metal on the wafer surface, and then remove the photoresist and excess metal through a stripping process, then clean and dry the wafer, and perform metallization annealing under appropriate conditions to form a P-type ohmic contact.

[0077] Step S30, firstly, the front N-type ohmic contact window pattern is obtained on the collector region 4 and the emitter region 7 respectively by photolithography transfer through a mask, then the redundant sacrificial oxide layer and the passivation layer are etched away to form the N-type ohmic contact window, then the contact metal is deposited on the surface of the wafer, and then the photoresist and redundant metal are removed by a stripping process, then the wafer is cleaned and dried, and metallization annealing is performed under appropriate conditions to form the N-type ohmic contact. At the same time, the passivation layer between the ohmic contact window of the collector region 4 and the ohmic contact window of the base region ohmic contact region 6, and between the ohmic contact window of the base region ohmic contact region 6 and the ohmic contact window of the emitter region 7 is the surface passivation layer 8.

[0078] Step S31, after the front ohmic contact is completed, a layer of SiO2 is re-deposited on the product surface as an annealing protection layer.

[0079] Step S32, forming metal interconnections of the emitter 10, the base 9 and the collector 11 on the front side.

[0080] A layer of metal such as Al is deposited on the front surface as a whole. Then, the electrode patterns of the front emitter 10, the base 9, the surface gate 12 and the collector 11 are transferred on the emitter region 7, the base ohmic contact region 6, the passivation layer between the emitter region 7 and the base ohmic contact region 6, and the collector region 4 through mask lithography. Then, the electrodes of the emitter 10, the base 9, the surface gate 12 and the collector 11 are separated by etching to form the outermost metal electrode of the device.

[0081] Step S33, finally removing the photoresist and cleaning the device surface, thereby completing the preparation of the SiC triode according to the first aspect of the embodiment of the present invention.

[0082] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0083] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0084] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0085] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0086] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0087] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A SiC triode used in integrated circuits, characterized in that: include: A SiC substrate, a P-type epitaxial layer located on the SiC substrate, and an N-type drift layer located on the P-type epitaxial layer; The P-type epitaxial layer serves as a first RESUEF region; A base region and a collector region are formed on both sides of the N-type drift layer by ion implantation; A floating ring is formed on the N-type drift layer between the base region and the collector region by ion implantation, the spacing of which gradually increases from the base region to the collector region; the doping concentration of the floating ring is 1e18-5e19; the floating ring serves as a second RESUEF region; An emitter region and a base region ohmic contact region are formed on both sides of the base region by ion implantation; The collector region, the base region ohmic contact region and the emitter region are provided with a collector electrode, a base electrode and an emitter electrode; A surface passivation layer is connected between the collector and the base, and between the base and the emitter respectively; A surface gate is arranged on the surface passivation layer between the base and the emitter.

2. A SiC triode for integrated circuits as claimed in claim 1, characterized in that: The base region is formed by P-type ion implantation.

3. A SiC triode for integrated circuits as claimed in claim 1, characterized in that: The floating ring is formed by P-type ion implantation.

4. A SiC triode for integrated circuits as claimed in claim 1, characterized in that: The emitter region is formed by N-type ion implantation.

5. The SiC triode used in an integrated circuit according to claim 1, characterized in that: The collector region is formed by N-type ion implantation.

6. A method for preparing a SiC triode for use in integrated circuits, characterized in that: The following steps are involved: Step 1, epitaxially growing a P-type epitaxial layer on a SiC substrate, and then epitaxially growing an N-type drift layer on the P-type epitaxial layer; the P-type epitaxial layer serves as a first RESUEF region; Step 2, performing ion implantation on one side of the N-type drift layer to form a base region; Step 3, ion implantation is performed on one side of the base region and the N-type drift layer on one side of the base region to form a base region ohmic contact region and a floating ring with gradually increasing spacing; the doping concentration of the floating ring is 1e18-5e19; the floating ring serves as a second RESUEF region; Step 4, performing ion implantation on the other side of the base region to form an emitter region; Step 5, performing ion implantation on the N-type drift layer on one side of the floating ring to form a collector region; wherein the floating ring is located between the base region and the collector region, and the distance between two adjacent floating rings gradually increases from the base region toward the collector region; Step 6, forming a passivation layer on the surface of the product manufactured in step 5, and then etching the passivation layer to form ohmic contact windows on the collector region, the base ohmic contact region and the emitter region, forming ohmic contacts on the ohmic contact windows, and forming a surface passivation layer between the ohmic contact window of the collector region and the ohmic contact window of the base ohmic contact region, and between the ohmic contact window of the base ohmic contact region and the ohmic contact window of the emitter region; Step seven, preparing a collector, a base and an emitter at positions corresponding to the ohmic contact window, and preparing a surface gate on the surface passivation layer between the ohmic contact window of the base ohmic contact region and the ohmic contact window of the emitter region.

7. A method for preparing a SiC triode for use in an integrated circuit according to claim 6, characterized in that: The specific steps of step one include: The SiC substrate is placed in a MOCVD reaction chamber to epitaxially grow an epitaxial layer, and P-type doping is performed to form a P-type epitaxial layer. A drift layer is grown on the P-type epitaxial layer, and N-type doping is performed to form an N-type drift layer.

8. The method for preparing a SiC triode for an integrated circuit according to claim 6, characterized in that: The specific steps of step 2 include: P-type ion implantation is performed on one side of the N-type drift layer to form a base region.

9. The method for preparing a SiC triode for an integrated circuit according to claim 6, characterized in that: The specific steps of step three include: P-type ion implantation is performed on one side of the base region and the N-type drift layer on one side of the base region to form a base region ohmic contact region and floating rings with gradually increasing spacing.

10. The method for preparing a SiC triode for an integrated circuit according to claim 6, characterized in that: The specific steps of step 4 include: Performing N-type ion implantation on the other side of the base region to form an emitter region; The specific steps of step five include: N-type ion implantation is performed in the N-type drift layer at one side of the floating ring to form a collector region.

Images