Silicon controlled rectifier integrated with transistor

Abstract

The invention relates to a silicon controlled rectifier integrated with transistors. The present disclosure relates to semiconductor structures, and more particularly, to silicon controlled rectifiers (SCRs) and methods of manufacture. The structure comprises a doped region in a semiconductor substrate; at least two semiconductor material regions comprising opposite doping types over the doped region; and polysilicon regions over respective ones of the at least two semiconductor material regions.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures, and more particularly, to silicon controlled rectifiers (SCRs) integrated with transistors and methods of fabrication. Background Art

[0002] SCRs are used for electrostatic discharge (ESD) protection of integrated circuits (ICs) to prevent sudden currents caused by, for example, contact, electrical shorts, or dielectric breakdown. ESD devices using SCRs can protect integrated circuits from failures due to their high current handling capability per unit area. These devices are most commonly used in high-performance analog and radio frequency (RF) designs for chips with large signal swings, low leakage, and low capacitance. RF performance can suffer due to capacitive loading and poor harmonics of SCRs. Summary of the invention

[0003] In one aspect of the present disclosure, a structure includes: a doped region in a semiconductor substrate; at least two semiconductor material regions including opposite doping types above the doped region; and a polysilicon region above corresponding ones of the at least two semiconductor material regions.

[0004] In one aspect of the present disclosure, a structure includes: a first doped region having a first dopant type in a semiconductor substrate; a first semiconductor layer above the first doped region and having the first dopant type; a second semiconductor layer above the first doped region and having a second dopant type opposite to the first dopant type; and a polysilicon region in contact with the first semiconductor layer and the second semiconductor layer.

[0005] In one aspect of the present disclosure, a method includes: forming a doped region in a semiconductor substrate; forming at least two semiconductor material regions including opposite doping types over the doped region; and forming a polysilicon region over corresponding semiconductor material regions of the at least two semiconductor material regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0007] Figure 1A A top view of a silicon controlled rectifier (SCR) in a PNPN configuration and a corresponding manufacturing process are shown according to aspects of the present disclosure.

[0008] Figure 1B According to aspects of the present disclosure, Figure 1A Cross-sectional view of the SCR device along line X1-X1.

[0009] Figure 2AA top view of an SCR in a bipolar junction transistor (BJT) configuration is shown in accordance with aspects of the present disclosure.

[0010] Figure 2B According to aspects of the present disclosure, Figure 2A Cross-sectional view of the SCR device along line X2-X2.

[0011] Figure 2C According to aspects of the present disclosure, Figure 2A Cross-sectional view of the SCR device along line X3-X3.

[0012] Figure 3 A cross-sectional view of another SCR device in a BJT configuration according to other aspects of the present disclosure is shown.

[0013] Figures 4A-4E According to other aspects of the present disclosure, Figure 1A and 1B Cross-sectional view of the steps in the SCR manufacturing process. DETAILED DESCRIPTION

[0014] The present disclosure relates to semiconductor structures, and more particularly, to silicon controlled rectifiers (SCRs) and methods of manufacturing. In an embodiment, the SCR includes: a doped collector region; a semiconductor region of opposite dopant type formed on top of the doped collector region and separated by a dielectric material; and an anode and a cathode formed on a doped polysilicon region connected to the semiconductor region of opposite dopant type. Advantageously, the structures described herein exhibit reduced capacitance with less RF degradation, improved space savings, faster switching times, and higher current drive due to more efficient bipolar and vertical integration.

[0015] In a more specific embodiment, the SCR includes an n-type region defined by a shallow trench isolation region. A doped SiGe region with an opposite dopant type may be formed on top of the n-type region and separated by a dielectric material. An anode and cathode are formed on n+ polysilicon and p+ polysilicon, which contact the SiGe region with the opposite dopant type. The SiGe region with the opposite dopant type may be, for example, a p-SiGe and n-SiGe layer. In an embodiment, an ohmic contact to the p-SiGe and n-SiGe through the polysilicon region may be parallel orthogonal to the anode / cathode.

[0016] The structures disclosed herein can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer dimensions. Methods (i.e., techniques) for manufacturing the structures disclosed herein have been adopted based on integrated circuit (IC) technology. For example, these structures are built on a wafer and implemented in a material film patterned on top of the wafer by means of a photolithography process. Specifically, the manufacture of the structure uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithography imaging; and (iii) selectively etching the film to the mask. In addition, as is known in the art, a pre-cleaning process can be used to clean any contaminants on the etched surface. In addition, as is known in the art, a rapid thermal annealing process can be used to drive in dopants or material layers when necessary.

[0017] Figure 1A shows a top view of a SCR in a PNPN configuration and the corresponding manufacturing process, Figure 1B Shows Figure 1A The cross-sectional view of the SCR device along the line X1-X1. Figure 1A and 1B The structure 100 includes: a doped region 16 located in a semiconductor substrate 12; a p-type semiconductor material 20 and an n-type doped semiconductor material 22 in contact with the doped region 16; and polysilicon regions 24, 26 in contact with the p-type doped semiconductor material 20. Similarly, polysilicon regions 24a, 26a are in contact with the n-type doped semiconductor material 20.

[0018] In an exemplary embodiment, the p-type doped semiconductor material 20 and the n-type doped semiconductor material 20 may be a single crystal p-SiGe material and an n-SiGe material, respectively. Moreover, the doped region 16 may be a sub-collector region including an n-doped semiconductor material. And the polysilicon regions 24, 24a, 26, 26a may be doped polysilicon between the contact 28 (i.e., cathode and anode) and the corresponding SiGe regions 20, 22 and in contact with the contact 28 and the corresponding SiGe regions 20, 22. The polysilicon regions 24, 24a, 26, 26a may also partially overlap with the insulator material 18. In an embodiment, the polysilicon regions 24, 24a may include p+ type polysilicon, and the polysilicon 26, 26a may include n+ type polysilicon. In addition to other suitable examples, the p-type dopant may be, for example, boron (B), and the n-type dopant may be, for example, arsenic (As), phosphorus (P), and antimony (Sb). In this way, the SCR may be a PNPN device.

[0019] In further embodiments, the semiconductor substrate 12 may include any suitable semiconductor material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. The semiconductor substrate 12 may also include any suitable single crystal orientation (e.g., (100), (110), (111) or (001) crystal orientation). In further embodiments, the semiconductor substrate 12 may be a bulk substrate including the semiconductor material described herein, or alternatively, may include a semiconductor-on-insulator technology as known in the art. In the semiconductor-on-insulator technology, the semiconductor substrate 12 will be the top semiconductor layer above the insulator material and the handle substrate, as known in the art.

[0020] A shallow trench isolation region 14 is formed in the semiconductor substrate adjacent to and isolating the sub-collector 16. In an embodiment, the SiGe regions 20, 22 are aligned with the edges of the shallow trench isolation region 14. That is, in a preferred embodiment, the SiGe regions 20, 22 do not overlap the shallow trench isolation region 14 so that a polycrystalline SiGe layer will not be formed in the structure 100. In addition, those skilled in the art will recognize that the positions of the p-SiGe region 20 and the n-SiGe region 22 may be swapped in each of the different embodiments.

[0021] In addition, the insulator material 18 can isolate the p-type doped semiconductor material 20 and the n-type doped semiconductor material 22. In further embodiments, the insulator material 18 can be a buried oxide material. In addition, the polysilicon regions 24, 26 can be isolated from each other by sidewall spacers 19. The sidewall spacers 19 can be, for example, a nitride material formed by a conventional deposition method (e.g., chemical vapor deposition (CVD)) and then by an anisotropic etching process. Contacts 28 (i.e., cathode and anode) extend to the polysilicon regions 24, 16. In an embodiment, the contacts 28 are parallel to each other and can be formed of any known conductive material, such as, for example, tungsten, Al, Cu lined with TiN or TaN. The contacts 20 can be formed in the interlayer dielectric material 15 using conventional photolithography, etching and deposition methods as known in the art.

[0022] The sub-collector 16 can be formed by a conventional implantation process, such as Figure 4A In an embodiment, the shallow trench isolation region 14 may be formed by conventional photolithography, etching and deposition methods known to those skilled in the art, such as those described in detail in the accompanying drawings. Figure 4AFurther described. In addition, the p-type doped semiconductor material 20 and the n-type doped semiconductor material 22 can be formed by an epitaxial growth process and a corresponding in-situ doping process. Similarly, the polysilicon regions 24, 24a, 26, 26a can be formed on the insulator material 18 by an epitaxial growth process and a corresponding in-situ doping process. Among other suitable examples, the p-type dopant can be, for example, boron (B), and the n-type dopant can be, for example, arsenic (As), phosphorus (P) and antimony (Sb).

[0023] Figure 2A A top view of an SCR in a bipolar junction transistor (BJT) configuration is shown in accordance with additional aspects of the present disclosure. Figure 2B Shows Figure 2A A cross-sectional view of the SCR device along line X2-X2, and Figure 2C Shows Figure 2A A cross-sectional view of the SCR device along line X3-X3. Figure 2A-2C In the structure 200, the polysilicon regions 24, 26 are oriented in the z-axis relative to the device. In addition, the ohmic contacts to the p-SiGe material 20 and the n-SiGe material 22 through the polysilicon p+ and n+ regions 24, 26 are orthogonal to the anode and cathode. For example, Figure 2B An n-type doped polysilicon region 24 disposed on and in contact with the p-SiGe material 20 and a p-type doped polysilicon region 26 disposed on and in contact with the n-SiGe material 22 are shown. Figure 2C The p-type doped polysilicon region 26 is disposed on and in contact with the p-SiGe material 20 and the n-type doped polysilicon region 24 is disposed on and in contact with the n-SiGe material 22. The remaining features may also be similar to Figure 1A and 1B The structure 100 is shown in FIG. 1 such that no further explanation is required herein.

[0024] Figure 3 A cross-sectional view of an SCR device in a BJT configuration is shown. For example, structure 300 includes a p-type doped region 16c in an N-well 16a and adjacent to an n-type doped region 16b (which may be part of the N-well 16a). The p-type doped region 16c and the n-type doped region 16b may form a pn junction. The p-type doped polysilicon region 26 may be disposed on and in contact with the p-SiGe material 20; and the n-type doped polysilicon region 24 may be disposed on and in contact with the n-SiGe material 22. The p-type doped polysilicon region 26 and the n-type doped polysilicon region 24 may overlap with the insulator material 18. The remaining features of structure 200 may also be similar to Figure 1A and 1BThe structure 100 is shown in FIG. 1 such that no further explanation is required herein.

[0025] Figures 4A-4E According to other aspects of the present disclosure, Figure 1A and 1B 2 is a cross-sectional view of steps in the manufacturing process of an SCR. It should be understood by those skilled in the art that similar processes can also be used to prepare SCR structures 200 and 300, for example, by using different in-situ dopants during the epitaxial growth process as described herein. In an embodiment, the sub-collector region can be formed by an ion implantation process as known in the art, so that no further explanation is required to fully understand the present disclosure.

[0026] Reference Figure 4A , forming an n-type sub-collector 16 in the semiconductor substrate 12. For example, a patterned implantation mask is used to select an exposed area for forming the n-type sub-collector 16. The implantation mask may include a layer of photosensitive material, such as an organic photoresist, which is applied by a spin coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer. The implantation mask has a thickness and blocking capability sufficient to block the masked area from receiving a dose of implanted ions. The n-type dopant may be, for example, arsenic (As), phosphorus (P), and Sb, among other suitable examples.

[0027] Still refer to Figure 4A , a shallow trench isolation region 14 is formed adjacent to the n-type sub-collector 16. The shallow trench isolation region 14 can be formed by conventional photolithography, etching and deposition methods known to those skilled in the art. For example, a resist formed above the semiconductor substrate 12 is exposed to energy (light) and developed using a conventional resist developer to form a pattern (opening). An etching process with selective chemistry, such as reactive ion etching (RIE), is used to transfer the pattern from the patterned photoresist layer to the semiconductor substrate 12 to form one or more trenches in the semiconductor substrate 12. After the resist is removed by a conventional oxygen ashing process or other known strippers, an insulator material (e.g., SiO2) can be deposited by any conventional deposition process, such as a chemical vapor deposition (CVD) process. Any residual material on the surface of the semiconductor substrate 12 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0028] exist Figure 4BIn the embodiment, a p-SiGe material 20 is formed on the n-type sub-collector 16. To form the p-SiGe material 20, an insulator material 18 is deposited on the semiconductor substrate 12. The insulator material 18 can be deposited by any conventional deposition method (e.g., CVD). A masking layer 34 is deposited on the insulator material 18. The masking layer 34 can be a nitride deposited by a conventional deposition method (e.g., CVD). An opening is formed through the insulator material 18 and the masking layer 34 to expose the underlying n-type sub-collector 16. The opening can be formed by conventional photolithography and etching processes as known in the art. SiGe material is epitaxially grown on the exposed underlying n-type sub-collector 16. In an embodiment, the epitaxial growth process includes an in-situ doping process using a p-type dopant to form the p-SiGe material 20.

[0029] exist Figure 4C In the embodiment, n-SiGe material 22 is formed over n-type sub-collector 16. To form n-SiGe material 22, insulator material 36 and masking layer 38 are formed over masking layer 34 using any conventional deposition method (e.g., CVD). As an example, insulator material 36 may also be an oxide, and masking layer 38 may also be a nitride. Again using conventional photolithography and etching processes, openings are formed through insulator materials 18, 36 and masking layers 34, 38 to expose the underlying n-type sub-collector 16. SiGe material is epitaxially grown on the exposed underlying n-type sub-collector 16. In an embodiment, the epitaxial growth process includes an in-situ doping process using an n-type dopant to form n-SiGe material 22.

[0030] exist Figure 4D In the embodiment of the present invention, the insulator material 18, 36 and the masking layer 38 are removed by conventional stripping techniques as known in the art, such as chemical mechanical polishing (CMP) or an etching process (e.g., a reactive ion etching process using selective chemistry). The p+ type polysilicon regions 26, 26a can be formed on the p-SiGe material 20 and the n-SiGe material 22, overlapping the insulator material 18. The epitaxial growth process can include an in-situ doping process using a p-type dopant (e.g., boron). As known in the art, the polysilicon material will be formed on the insulator material 18. After a conventional patterning process, a sidewall spacer material 19, such as a nitride, can be deposited and patterned on the p+ type polysilicon regions 26, 26a.

[0031] exist Figure 4EIn the embodiment of the present invention, n+ type polysilicon regions 24, 24a can be formed on the p-SiGe material 20 and the n-SiGe material 22, overlapping the insulator material 18. The epitaxial growth process can include an in-situ doping process using an n-type dopant (e.g., arsenic). Again, as is known in the art, the polysilicon material will be formed on the insulator material 18. After a conventional patterning process, a sidewall spacer material 19, such as a nitride, can be deposited and patterned on the n+ type polysilicon regions 26, 26a.

[0032] Return to reference Figure 1B , for example, contacts 28 may be formed through the interlayer dielectric material 15 by conventional photolithography, etching, and deposition processes as known in the art. Prior to depositing the conductive material to form the contacts 28, a conventional silicide process may be used to provide silicide contacts to the various regions. It will be appreciated by those skilled in the art that the silicide process begins by depositing a thin transition metal layer, such as nickel, cobalt, or titanium, over the exposed regions 24, 24a, 26, 26a. After the material is deposited, the structure is heated to allow the transition metal to react with the exposed silicon (or other semiconductor materials described herein) to form a low resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active areas of the device.

[0033] These structures can be exploited in system-on-chip (SoC) technology. An SoC is an integrated circuit (also called a "chip") that integrates all the components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes much less power and occupies a much smaller area than a multi-chip design with equivalent functionality. As a result, SoCs are becoming a dominant force in the mobile computing (e.g., in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things.

[0034] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die or in a packaged form. In the latter case, the chip is installed in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier having surface interconnects or buried interconnects, or both surface interconnects and buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product including an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices and central processing units.

[0035] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: a doped region in a semiconductor substrate; at least two regions of semiconductor material comprising opposite doping types over said doped region; as well as A polysilicon region is located over a corresponding semiconductor material region of the at least two semiconductor material regions.

2. The structure according to claim 1, wherein: The at least two semiconductor material regions include n-SiGe material and p-SiGe material.

3. The structure according to claim 2, wherein: The doped region in the semiconductor substrate includes an n-type doped region located below and in contact with the n-SiGe material and the p-SiGe material.

4. The structure according to claim 3, wherein: The n-SiGe material and the p-SiGe material are located at an edge of a shallow trench isolation structure and are separated by a dielectric material.

5. The structure according to claim 4, wherein: The polysilicon region includes a first p-type doped polysilicon region and a first n-doped polysilicon region on and in contact with the n-SiGe material, and a second p-type doped polysilicon region and a second n-doped polysilicon region on and in contact with the p-SiGe material.

6. The structure of claim 5 further comprising contacts to the first and second n-doped polysilicon regions and the first and second p-doped polysilicon regions.

7. The structure according to claim 5, wherein: The p-SiGe material and the n-SiGe material include single crystal materials.

8. The structure according to claim 6, wherein: The contacts are parallel to each other.

9. The structure according to claim 2, wherein: The doped region in the semiconductor substrate includes a p+ region in an n-well, and the n-SiGe material is connected to the n-well and the p-SiGe material is connected to the p+ region.

10. The structure according to claim 9, wherein: The polysilicon region includes a p-type doped polysilicon region connected to the p-SiGe and an n-doped polysilicon region connected to the n-SiGe.

11. The structure according to claim 1, wherein: The doped region includes a pn junction.

12. The structure according to claim 1, wherein: The at least two semiconductor material regions include a p-SiGe region and an n-SiGe region, and the polysilicon region includes: a first n-type doped polysilicon material connected to the p-SiGe region; a second n-type doped polysilicon material connected to the n-SiGe region; a first p-type doped polysilicon material connected to the p-SiGe region; and A second n-type doped polysilicon material is connected to the n-SiGe region.

13. The structure according to claim 12, wherein: The ohmic contacts are positioned orthogonally.

14. A structure comprising: a first doped region having a first dopant type in the semiconductor substrate; a first semiconductor layer having a first dopant type over the first doped region; a second semiconductor layer over the first doped region and having a second dopant type opposite to the first dopant type; as well as A polysilicon region is in contact with the first semiconductor layer and the second semiconductor layer.

15. The structure according to claim 14, wherein: The first semiconductor layer includes a p-SiGe layer, and the second semiconductor layer includes an n-SiGe layer.

16. The structure according to claim 15, wherein: The polysilicon region comprises: first and second polysilicon having opposite dopant types in contact with the p-SiGe layer; and First and second polysilicon having opposite dopant types are in contact with the n-SiGe layer.

17. The structure of claim 14, wherein: The first doped region includes a pn junction.

18. The structure of claim 14 further comprising contacts connected to the polysilicon regions parallel to each other.

19. The structure of claim 14 further comprising orthogonally positioned contacts connected to the polysilicon regions.

20. A method comprising: forming a doped region in a semiconductor substrate; forming at least two regions of semiconductor material including opposite doping types over the doped region; as well as A polysilicon region is formed over a corresponding semiconductor material region of the at least two semiconductor material regions.

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