Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention provides a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductors, and the preparation method comprises the steps: forming a semiconductor body which is set to be of a first conductive type and comprises a first surface and a second surface which are oppositely arranged, forming a source trench, the source trench extends into the semiconductor body from the first surface, an insulating layer and a source trench structure are formed in the source trench, the source trench structure comprises a bottom surface close to the second surface and a side wall connected with the bottom surface, the insulating layer is arranged between the source trench structure and the source trench, an interlayer insulating layer is formed on the first surface, and the interlayer insulating layer is arranged between the source trench structure and the source trench. And removing the part, close to the first surface, of the source trench structure to enable the side wall to be covered by the insulating layer, forming a source on the first surface, and forming a drain on the second surface, so as to improve the reliability of the semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] The gate oxide layer plays a vital role in semiconductor devices. It not only affects the electrical performance of semiconductor devices, but also directly affects the reliability and stability of semiconductor devices. In silicon carbide trench metal oxide semiconductor field effect transistors (SiC trench MOSFET), the materials of the interlayer dielectric (ILD) and the gate oxide layer are usually the same. In the process of etching the interlayer dielectric, the gate oxide layer on the sidewall of the source trench will be overetched, resulting in a gap between the trench source and the semiconductor body, which affects the reliability of the semiconductor device. Summary of the invention

[0003] The present application provides a semiconductor device and a preparation method, a power module, a power conversion circuit and a vehicle, which are used to improve the electrical performance of the semiconductor device, thereby improving the reliability and stability of the semiconductor device.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0005] On the one hand, a method for preparing a semiconductor device is provided, the preparation method comprising: forming a semiconductor body, the semiconductor body being set to a first conductive type, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, forming a source groove, the source groove extending from the first surface into the semiconductor body, forming an insulating layer and a source groove structure in the source groove, the source groove structure comprising a bottom surface close to the second surface and a side wall connected to the bottom surface, the insulating layer being arranged between the source groove structure and the source groove, forming an interlayer insulating layer on the first surface, removing a portion of the source groove structure close to the first surface so that the side wall is covered by the insulating layer, forming a source on the first surface, and forming a drain on the second surface.

[0006] In the above preparation method, after forming the semiconductor body, the source trench, the insulating layer and the source trench structure, during the process of forming the interlayer insulating layer, the insulating layer is etched so that the sidewall of the source trench structure exceeds the insulating layer in a direction perpendicular to the second surface and pointing from the second surface to the first surface. Then, the portion of the source trench structure close to the first surface is removed so that the sidewall is completely covered by the insulating layer, thereby eliminating the gap between the source trench structure and the semiconductor body, avoiding the gap from affecting the conductive properties of the conductive layer located above the source trench structure and the semiconductor body, and thus improving the reliability and stability of the semiconductor device.

[0007] In some embodiments, an interlayer insulating layer is formed on the first surface, including forming an interlayer insulating film on the first surface, the material of the interlayer insulating film being the same as the material of the insulating layer, etching the interlayer insulating film to form the interlayer insulating layer, and etching part of the insulating layer.

[0008] In some embodiments, the semiconductor body further includes a first region and a well region, the first region being located on the first surface and being set to a first conductivity type, and the well region being located on a side of the first region away from the first surface and being set to a second conductivity type. After forming the source trench and before forming the insulating layer and the source trench structure, the above-mentioned preparation method further includes forming a second region on the surface of the source trench, and the second region is set to a second conductivity type. After removing a portion of the source trench structure close to the first surface and before forming the source, the above-mentioned preparation method further includes forming an ohmic contact layer, the ohmic contact layer being electrically connected to the first region and the second region, and the ohmic contact layer is also in contact with the insulating layer and the source trench structure.

[0009] On the other hand, a semiconductor device is provided, which includes a semiconductor body, a source trench structure, a source, an interlayer insulating layer and a drain. The semiconductor body is set to a first conductivity type, and includes a first surface and a second surface arranged opposite to each other, the first surface is provided with a source trench, the source trench extends from the first surface into the semiconductor body, the semiconductor body also includes an insulating layer arranged in the source trench, the source trench structure is arranged in the source trench, the insulating layer is arranged between the source trench structure and the source trench, the source is arranged on the first surface, the interlayer insulating layer is arranged between the semiconductor body and the source, and the drain is arranged on the second surface.

[0010] The source trench structure includes a bottom surface close to the second surface, a side wall connected to the bottom surface, and a top surface opposite to the bottom surface. The vertical distance between the top surface and the second surface is smaller than the vertical distance between the first surface and the second surface, and the side wall is covered by an insulating layer.

[0011] In the above-mentioned semiconductor device, the source trench extends from the first surface of the semiconductor body into the semiconductor body, the source trench structure is arranged in the source trench, and the insulating layer is arranged between the source trench structure and the source trench, the source trench structure includes a bottom surface of the second surface, and a side wall connected to the bottom surface and a top surface opposite to the bottom surface, the vertical distance between the top surface and the second surface is smaller than the vertical distance between the first surface and the second surface, and the side wall is covered by the insulating layer, that is, along a direction perpendicular to the second surface and pointing from the second surface to the first surface, the top surface of the source trench structure is lower than the first surface, and its side wall is not exposed, that is, there is no gap between the trench source and the semiconductor body, so as to avoid the gap from affecting the conductive performance of the conductive layer located above the trench source and the semiconductor body. This structure improves the conductive performance of the semiconductor device, thereby improving the reliability and stability of the semiconductor device.

[0012] In some embodiments, along a direction perpendicular to the second surface and pointing from the second surface to the first surface, a top surface of the source trench structure does not exceed the insulating layer.

[0013] In some embodiments, a top surface of the source trench structure is a curved surface recessed toward the second surface.

[0014] In some embodiments, the semiconductor body further includes a first region, a well region, and a second region, the first region is located on the first surface and is set to the first conductivity type, the well region is located on a side of the first region away from the first surface and is set to the second conductivity type, the second region is arranged on the surface of the source trench, and the second region is set to the second conductivity type. The semiconductor device further includes an ohmic contact layer, the ohmic contact layer is arranged between the semiconductor body and the source, the ohmic contact layer is electrically connected to the first region and the second region, and the ohmic contact layer is also in contact with the insulating layer and the source trench structure.

[0015] In yet another aspect, a power module is provided. The power module includes a substrate and a semiconductor device according to any one of the above embodiments. The substrate is used for carrying the semiconductor device.

[0016] In another aspect, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and a semiconductor device as described in any of the above embodiments, and the semiconductor device is electrically connected to the circuit board.

[0017] On the other hand, a vehicle is provided, which includes a load and a power conversion circuit as described in the above embodiment, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0018] The above-mentioned power module, power conversion circuit and vehicle have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above-mentioned embodiments, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present application, the actual process of the method, etc.

[0020] Figure 1 A flowchart of the steps of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0021] Figure 2 to Figure 12 It is a diagram of each step of the preparation method provided in the examples of this application;

[0022] Fig.13 A structural diagram of a power module provided in an embodiment of the present application;

[0023] Fig.14 A structural diagram of a power conversion circuit provided in an embodiment of the present application;

[0024] Fig.15 A structural diagram of a vehicle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0026] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0027] In the description of the present application, “plurality” means two or more.

[0028] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0029] The embodiment of the present application also provides a method for preparing a semiconductor device. Figure 1 A flowchart of the steps of a method for preparing a semiconductor device provided in an embodiment of the present application; Figure 2 to Figure 12 Schematic diagram of each step of the preparation method provided in the examples of this application. Figure 1 The preparation method comprises the following steps S1 to S7:

[0030] Step S1: Figure 2 As shown, a semiconductor body is formed, the semiconductor body includes a first surface 101 and a second surface 102 arranged opposite to each other, and the semiconductor body is set to a first conductivity type. Exemplarily, the first conductivity type can be P-type or N-type. The embodiment of the present application takes the first conductivity type as N-type as an example for explanation. The semiconductor body includes a silicon carbide substrate 103 and an epitaxial layer 104 stacked on the silicon carbide substrate 103. The "first surface 101" is the surface of the epitaxial layer 104 away from the silicon carbide substrate 103, and the "second surface 102" is the surface of the silicon carbide substrate 103 away from the epitaxial layer 104.

[0031] In some embodiments, Figure 2 As shown, the process of forming the semiconductor body also includes forming a well region 10 and a first region 11. The well region 10 and the first region 11 are formed by ion implantation into the epitaxial layer 104 through the first surface 101. The first region 11 is arranged on the first surface 101, and the first region 11 is set to the first conductivity type. The well region 10 is arranged on the side of the first region 11 away from the first surface 101, and the well region 10 is set to the second conductivity type. Exemplarily, P-type ions are implanted into the well region 10, and its conductivity type is P-type. The well region 10 can also be called a "P-type well region (P-well)", the conductivity type of the silicon carbide substrate 103 and the epitaxial layer 104 are both N-type, and N-type ions are implanted into the first region 11, and its conductivity type is also N-type. The first region 11 can also be called an "N+ contact region".

[0032] Step S2: Figure 3As shown, the epitaxial layer 104 is etched so that a gate trench 20 and source trenches 30 disposed on both sides of the gate trench 20 are provided on the first surface 101 of the semiconductor body. Both the gate trench 20 and the source trench 30 extend from the first surface 101 into the semiconductor body.

[0033] In some embodiments, Figure 4 As shown, a second region 12 is formed on the surface of the source trench 30, the second region 12 is located on the first surface 101, and is located outside the first region 11 and the well region 10, and the second region 12 is also set to the second conductivity type. Exemplarily, the second region 12 is formed by performing ion implantation of the second conductivity type on the epitaxial layer 104, and when the silicon carbide substrate 103 and the epitaxial layer 104 are of N-type conductivity, P-type ions are implanted into the second region 12, and its conductivity type is P-type, and the second region 12 can also be called a "P+ contact region".

[0034] Step S3: Figure 5 to Figure 7 As shown, a first insulating layer 32 and a source trench structure 31 are formed in the source trench 30, and the first insulating layer 32 is disposed between the source trench 30 and the source trench structure 31, and a second insulating layer 22 and a gate trench structure 21 are formed in the gate trench 20, and the second insulating layer 22 is disposed between the gate trench 20 and the gate trench structure 21. The source trench structure 31 includes a bottom surface 310 close to the second surface 102 and a sidewall 311 connected to the bottom surface 310.

[0035] In some embodiments, the specific process of forming the first insulating layer 32, the source trench structure 31, the second insulating layer 22 and the gate trench structure 21 is as follows: Figure 5 As shown, firstly, an insulating film 320 is deposited on the first surface 101 as a whole layer. For example, the insulating film 320 may be silicon oxide. Then, as shown in FIG. Figure 6 As shown, a semiconductor material 350 is deposited on the side of the insulating film 320 away from the first surface 101, and the semiconductor material 350 at least covers the gate trench 20 and the source trench 30. For example, the semiconductor material 350 may be polysilicon. Figure 7 As shown, the semiconductor material 350 is etched to obtain the gate trench structure 21 and the source trench structure 31. After this step is completed, the first insulating layer 32 and the second insulating layer 22 are not separated yet, and both are still part of the insulating film 320.

[0036] Step S4: Figure 8 As shown, an interlayer insulating layer 7 is formed on the first surface 101 .

[0037] In some embodiments, the process of forming the interlayer insulating layer 7 includes first forming an interlayer insulating film on the first surface 101, the material of the interlayer insulating film being the same as the material of the insulating film 320, and then etching the interlayer insulating film to form Figure 8 The interlayer insulating layer 4 is shown. Since the material of the interlayer insulating film is the same as that of the insulating film 320, the insulating film 320 will also be etched during the etching process of the interlayer insulating film, and the insulating film 320 will be separated to form the first insulating layer 32 and the second insulating layer 22.

[0038] Among them, since the insulating film 320 is etched during the process of forming the interlayer insulating layer 7, the side wall 311 of the source trench structure 31 exceeds the first insulating layer 32 along the direction perpendicular to the second surface 102 and pointing from the second surface 102 to the first surface 101 (direction Z), that is, a gap is generated between the source trench structure 31 and the second region 12, thereby affecting the conductive performance of the conductive layer located above the source trench structure 31 and the second region 12.

[0039] Step S5: Fig. 9 As shown, the source trench structure 31 also includes a top surface 312 opposite to the bottom surface 310. The portion of the source trench structure 31 close to the first surface 101 is removed, that is, part of the top surface 312 of the source trench structure 31 is removed, so that the side wall 311 of the source trench structure 31 is covered by the first insulating layer 32. It can be understood that after removing the portion of the source trench structure 31 close to the first surface 101, the entire surface of the side wall 311 is covered by the first insulating layer 32, so that the side wall 311 is not exposed, so that there is no gap between the side wall 311 and the source trench 30, that is, there is no gap between the source trench structure 31 and the second region 12, so as to avoid the gap from affecting the conductive performance of the conductive layer located above the source trench structure 31 and the second region 12, thereby improving the reliability and stability of the subsequently formed semiconductor device.

[0040] Exemplarily, the process of removing part of the top surface 312 of the source trench structure 31 may adopt dry etching, wherein an opening is set on the mask plate to expose the top surface 312 of the mask plate, and then the top surface 312 of the source trench structure 31 is etched through the mask plate.

[0041] In some embodiments, Fig.10As shown, after removing the portion of the source trench structure 31 close to the first surface 101, the preparation method further includes forming an ohmic contact layer 6. The ohmic contact layer 6 is electrically connected to the first region 11 and the second region 12, and the ohmic contact layer 6 is also in contact with the first insulating layer 32 and the source trench structure 31. Since no gap is formed between the source trench structure 31 and the second region 12, after the ohmic contact layer 6 is formed, the ohmic contact layer 6 can be in contact with the first insulating layer 32, and can also be in contact with the top surface 312 of the source trench structure 31, which is conducive to improving the conductive performance of the ohmic contact layer 6, thereby improving the reliability and stability of the semiconductor device formed subsequently.

[0042] Step S6: Fig.11 As shown, a source electrode 4 is formed on the first surface 101 , and the source electrode 4 is electrically connected to the first region 11 and the second region 12 through the ohmic contact layer 6 .

[0043] Step S7: Fig.12 As shown, a drain 5 is formed on the second surface 102, and finally a semiconductor device A is formed.

[0044] By transmitting the turn-on voltage to the gate trench structure 21 , when the semiconductor device A is forward-conducting and the operating current is small, the operating current flows from the source 4 through the ohmic contact layer 6 , the first region 11 , the well region 10 , the epitaxial layer 104 and the silicon carbide substrate 103 to the drain 5 .

[0045] Since the P-type ion concentration in the second region 12 is higher than that in the well region 10, more PN junctions are formed between the second region 12 and the epitaxial layer 104. When the working current is large, the working current flows from the source 4 through the ohmic contact layer 6, the second region 12, the epitaxial layer 104 and the silicon carbide substrate 103 to the drain 5, thereby preventing the large working current from flowing through the well region 10, thereby protecting the channel in the well region 10.

[0046] In the method for preparing the semiconductor device A provided in the embodiment of the present application, after forming the semiconductor body, the source trench 30, the first insulating layer 32 and the source trench structure 31, during the process of forming the interlayer insulating layer 7, the first insulating layer 32 is etched, so that the sidewall 311 of the source trench structure 31 exceeds the first insulating layer 32 along the direction perpendicular to the second surface 102 and pointing from the second surface 102 to the first surface 101. Then, the portion of the source trench structure 31 close to the first surface 101 is removed, so that the sidewall 311 is completely covered by the first insulating layer 32, thereby eliminating the gap between the source trench structure 31 and the semiconductor body, avoiding the gap from affecting the conductive performance of the conductive layer located above the source trench structure 31 and the semiconductor body, and thus improving the reliability and stability of the semiconductor device A.

[0047] On the other hand, an embodiment of the present application further provides a semiconductor device, Fig.12 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application.

[0048] See also Fig.12 The semiconductor device A is a silicon carbide trench metal oxide semiconductor field effect transistor (SiC trench MOSFET), and the semiconductor device A includes a semiconductor body, a source trench 30, a first insulating layer 32, a source trench structure 31, a gate trench 20, a second insulating layer 22, a gate trench structure 21, a source 4, an interlayer insulating layer 7 and a drain 5.

[0049] The semiconductor body is set to a first conductivity type, and includes a first surface 101 and a second surface 102 arranged opposite to each other, the first surface 101 is provided with a gate trench 20 and a source trench 30 located on both sides of the gate trench 20, and the gate trench 20 and the source trench 30 extend from the first surface 101 into the semiconductor body. The semiconductor body also includes a first insulating layer 32 arranged in the source trench 30, and a second insulating layer 22 arranged in the gate trench 20.

[0050] The semiconductor body also includes a well region 10, a first region 11 and a second region 12. The first region 11 is located on the first surface 101 and is set to a first conductivity type. The well region 10 is located on a side of the first region 11 away from the first surface 101 and is set to a second conductivity type. The second region 12 is located on the first surface 101 and is located outside the first region 11 and the well region 10. The second region 12 is set to the first conductivity type. For example, P-type ions are injected into both the well region 10 and the second region 12, and the conductivity types of both are P-type. The well region 10 can also be called a "P-type well region (P-well)", and the second region 12 can also be called a "P+ contact region". The conductivity types of the silicon carbide substrate 103, the epitaxial layer 104 and the first region 11 are all N-type. N-type ions are injected into the first region 11, and the first region 11 can also be called an "N+ contact region".

[0051] For example, see Fig.12 The semiconductor body includes a silicon carbide substrate 103 and an epitaxial layer 104 stacked on the silicon carbide substrate 103, a "first surface 101" is a surface of the epitaxial layer 104 away from the silicon carbide substrate 103, and a "second surface 102" is a surface of the silicon carbide substrate 103 away from the epitaxial layer 104. The well region 10, the first region 11, and the second region 12 can all be arranged in the epitaxial layer 104.

[0052] A source trench structure 31 is also disposed in the source trench 30, a first insulating layer 32 is disposed between the source trench 30 and the source trench structure 31, and the source trench structure 31 includes a bottom surface 310 close to the second surface 102, a side wall 311 connected to the bottom surface 310, and a top surface 312 opposite to the bottom surface. The vertical distance between the top surface 312 and the second surface 102 is smaller than the vertical distance between the first surface 101 and the second surface 102, that is, along the direction Z, relative to the second surface 102, the top surface 312 is located below the first surface 101. Furthermore, the sidewall 311 of the source trench structure 31 is covered by the first insulating layer 32, that is, the entire surface of the sidewall 311 is covered by the first insulating layer 32, so that the sidewall 311 is not exposed, so that there is no gap between the sidewall 311 and the source trench 30, that is, there is no gap between the source trench structure 31 and the second region 12, thereby avoiding the gap from affecting the conductive properties of the conductive layer located above the source trench structure 31 and the second region 12, thereby improving the reliability and stability of the semiconductor device A.

[0053] A gate trench structure 21 is also disposed in the gate trench 20, and a second insulating layer 22 is disposed between the gate trench 20 and the gate trench structure 21. The second region 12 is located outside the first region 11 and the well region 10, that is, the second region 12 is located on a side of the first region 11 and the well region 10 away from the gate structure 2.

[0054] See also Fig.12 The source 4 is disposed on the first surface 101 of the semiconductor body and is electrically connected to the first region 11 and the second region 12 . The drain 5 is disposed on the second surface 102 of the semiconductor body.

[0055] In some embodiments, Fig.12 As shown, the semiconductor device A also includes an ohmic contact layer 6, which is arranged between the semiconductor body and the source 4, and the ohmic contact layer 6 is electrically connected to the first region 11 and the second region 12, and the ohmic contact layer 6 is also in contact with the first insulating layer 32 and the source trench structure 31. Since there is no gap between the source trench structure 31 and the second region 12, the ohmic contact layer 6 can be in contact with the first insulating layer 32, and can also be in contact with the top surface 312 of the source trench structure 31, which is beneficial to improve the conductive performance of the ohmic contact layer 6, thereby improving the reliability and stability of the semiconductor device A.

[0056] In semiconductor device A, by transmitting the turn-on voltage to the gate trench structure 21, when semiconductor device A is forward-conducting and the operating current is small, the operating current flows from the source 4 through the ohmic contact layer 6, the first region 11, the well region 10, the epitaxial layer 104 and the silicon carbide substrate 103 to the drain 5.

[0057] Since the P-type ion concentration in the second region 12 is higher than that in the well region 10, more PN junctions are formed between the second region 12 and the epitaxial layer 104. When the working current is large, the working current flows from the source 4 through the ohmic contact layer 6, the second region 12, the epitaxial layer 104 and the silicon carbide substrate 103 to the drain 5, thereby preventing the large working current from flowing through the well region 10, thereby protecting the channel in the well region 10.

[0058] In some embodiments, Fig.12 As shown, along the direction perpendicular to the second surface 102 and pointing from the second surface 102 to the first surface 101 (direction Z), the top surface 312 of the source trench structure 31 does not exceed the first insulating layer 31, which can be understood as two situations. Along the direction Z, with the second surface 102 as the reference plane, the top surface 312 is flush with the side of the first insulating layer 31 close to the first surface 101, or the top surface 312 is lower than the side of the first insulating layer 31 close to the first surface 101, which can avoid the formation of a gap between the trench source 31 and the second region 12, thereby avoiding the gap from affecting the conductive performance of the conductive layer located above the trench source 31 and the second region 12, thereby improving the reliability and stability of the semiconductor device A.

[0059] In some embodiments, Fig.12 As shown, the top surface 312 of the source trench structure 31 is an arc surface recessed toward the second surface 102. With the second surface 102 as a reference plane, the height of the top surface 312 gradually decreases from the edge to the middle, which can prevent the top surface 312 from protruding to form a gap between the source trench structure 31 and the second region 12, thereby improving the reliability and stability of the semiconductor device A.

[0060] The embodiment of the present application further provides a power module, Fig.13 A structural diagram of a power module provided in an embodiment of the present application.

[0061] See also Fig.13 The power module 8 includes a substrate 81 and the semiconductor device A in any of the above embodiments, and the substrate 81 is used to carry the semiconductor device A.

[0062] Exemplarily, the power module 8 can be used as one of a power amplifier, a power converter, a power controller, a power management module, or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another form. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is used to control the device of power flow. The power management module is used to manage the power supply to ensure that the power is stably and efficiently distributed to different parts of the electronic device. The power regulator is used to adjust the power output to meet the needs of a specific application.

[0063] The embodiment of the present application also provides a power conversion circuit, Fig.14 A structural diagram of a power conversion circuit provided in an embodiment of the present application.

[0064] See also Fig.14 The power conversion circuit 9 includes a circuit board 91 and a semiconductor device A in any of the above embodiments, the semiconductor device A is electrically connected to the circuit board 91, and the power conversion circuit 9 can be used for current conversion, voltage conversion or power factor correction.

[0065] Exemplarily, the power conversion circuit 9 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce the harmonic pollution of the power grid.

[0066] An embodiment of the present application further provides a vehicle, Fig.15 A structural diagram of a vehicle provided in an embodiment of the present application.

[0067] See also Fig.15 Vehicle B includes a load 90 and the power conversion circuit 9 in the above embodiment, and the power conversion circuit 9 is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load 90 to power the load 90.

[0068] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: forming a semiconductor body, the semiconductor body being configured as a first conductivity type and comprising a first surface and a second surface opposite to each other; forming a source trench extending from the first surface into the semiconductor body; forming an insulating layer and a source trench structure in the source trench, wherein the source trench structure comprises a bottom surface close to the second surface and a side wall connected to the bottom surface; The insulating layer is disposed between the source trench structure and the source trench; forming an interlayer insulating layer on the first surface; removing a portion of the source trench structure close to the first surface so that the sidewall is covered by the insulating layer; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

2. The preparation method according to claim 1, characterized in that: An interlayer insulating layer is formed on the first surface, comprising: forming an interlayer insulating film on the first surface, wherein the material of the interlayer insulating film is the same as that of the insulating layer; The interlayer insulating film is etched to form the interlayer insulating layer, and part of the insulating layer is etched.

3. The preparation method according to claim 1, characterized in that: The semiconductor body further comprises a first region and a well region, wherein the first region is located on the first surface and is set to be of a first conductivity type; the well region is located on a side of the first region away from the first surface and is set to be of a second conductivity type; After forming the source trench and before forming the insulating layer and the source trench structure, the preparation method further includes: forming a second region on the surface of the source trench, wherein the second region is set to a second conductivity type; After removing the portion of the source trench structure close to the first surface and before forming the source, the preparation method further includes: An ohmic contact layer is formed, wherein the ohmic contact layer is electrically connected to the first region and the second region, and the ohmic contact layer is also in contact with the insulating layer and the source trench structure.

4. A semiconductor device, characterized in that: include: A semiconductor body, which is set to a first conductivity type, comprises a first surface and a second surface which are arranged opposite to each other; a source trench is arranged on the first surface, and the source trench extends from the first surface into the semiconductor body; the semiconductor body further comprises an insulating layer arranged in the source trench; A source trench structure is disposed in the source trench, and the insulating layer is disposed between the source trench structure and the source trench; A source electrode, disposed on the first surface; An interlayer insulating layer, disposed between the semiconductor body and the source electrode; A drain electrode is disposed on the second surface; Wherein, the source trench structure includes a bottom surface close to the second surface, a side wall connected to the bottom surface, and a top surface opposite to the bottom surface; the vertical distance between the top surface and the second surface is smaller than the vertical distance between the first surface and the second surface; and the side wall is covered by the insulating layer.

5. The semiconductor device according to claim 4, characterized in that Along a direction perpendicular to the second surface and pointing from the second surface to the first surface, a top surface of the source trench structure does not exceed the insulating layer.

6. The semiconductor device according to claim 4, characterized in that The top surface of the source trench structure is a curved surface recessed toward the second surface.

7. The semiconductor device according to claim 4, characterized in that The semiconductor body further comprises a first region, a well region, and a second region, wherein the first region is located on the first surface and is set to a first conductivity type; the well region is located on a side of the first region away from the first surface and is set to a second conductivity type; the second region is arranged on a surface of the source trench and is set to a second conductivity type; The semiconductor device further includes an ohmic contact layer, which is disposed between the semiconductor body and the source; the ohmic contact layer is electrically connected to the first region and the second region, and the ohmic contact layer is also in contact with the insulating layer and the source trench structure.

8. A power module, characterized in that: include: At least one semiconductor device according to any one of claims 4 to 7; A substrate is used to carry the semiconductor device.

9. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 4 to 7, wherein the semiconductor device is electrically connected to the circuit board.

10. A vehicle, characterized in that: include: A load and a power conversion circuit as claimed in claim 9, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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