VDMOS groove type electric field modulation variable doping terminal and preparation method thereof

Abstract

The invention provides a VDMOS groove type electric field modulation variable doping terminal and a preparation method thereof, and the method comprises the steps: carrying out the epitaxial growth of the upper side surface of a silicon carbide substrate, and obtaining a drift layer; a barrier layer is formed, etching and ion implantation are carried out, and a P + well region and a P + region are formed; forming a barrier layer again, and etching to form a first groove, a second groove and a third groove; depositing to form a first P-type groove region, a second P-type groove region and a third P-type groove region; forming a barrier layer again, and performing thermal diffusion redistribution at a set temperature and a set time to form a first P-type doped region, a second P-type doped region and a third P-type doped region; a barrier layer is formed again, and an insulating layer is formed through etching and deposition; re-forming a barrier layer, etching and depositing to form a source metal layer and a cut-off ring metal layer; and the barrier layer is re-formed, the high-resistivity conductor layer is formed through etching and deposition, and the barrier layer is removed, so that the breakdown problem caused by electric field concentration is solved, and the reliability of the device is improved.

Description

Technical Field

[0001] The invention relates to a VDMOS trench type electric field modulation variable doping terminal and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. Based on the device structure design, the edge of the repeated cell has electric field concentration due to the lateral distribution of the electric field, resulting in breakdown at the edge of the device. Traditional cells use the same doping concentration field limiting ring structure to suppress electric field concentration. Since the doping concentration and spacing of the field limiting ring are equal, the electric field strength distribution gradually decreases, and there are still high and low differences in the electric field distribution. The risk of breakdown in the area close to the P+ well area is still high. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a VDMOS trench type electric field modulation variable doping terminal and a preparation method thereof, so as to solve the breakdown problem caused by electric field concentration and improve the reliability of the device.

[0004] In a first aspect, the present invention provides a method for preparing a VDMOS trench type electric field modulation variable doping terminal, comprising the following steps: Step 1: epitaxially grow a drift layer on the side of a silicon carbide substrate; Step 2, forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a P+ well region and a P+ region; Step 3, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching the drift layer to form a first groove, a second groove, and a third groove; Step 4, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching downwardly the second groove and the third groove; Step 5, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching downward a third groove; Step 6: remove the barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit silicon carbide material, and form a first P-type trench region; Step 7, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing silicon carbide material, and forming a second P-type trench region; Step 8, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing silicon carbide material, and forming a third P-type trench region; Step 9, removing the barrier layer, re-forming the barrier layer, and performing thermal diffusion and redistribution on the first P-type trench region, the second P-type trench region, and the third P-type trench region at a set temperature and a set time to form a first P-type doping region, a second P-type doping region, and a third P-type doping region; the main junction includes the first P-type doping region and the first P-type trench region; the first field limiting ring includes the second P-type doping region and the second P-type trench region; the second field limiting ring includes the third P-type doping region and the third P-type trench region, and the P+ well region, the first P-type doping region, the second P-type doping region, and the third P-type doping region are connected in sequence; Step 10, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating layer; Step 11, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a source metal layer and a stop ring metal layer; Step 12: remove the barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit to form a high resistivity conductor layer, and remove the barrier layer.

[0005] In a second aspect, the present invention provides a VDMOS trench type electric field modulation variable doping terminal, wherein the silicon carbide VDMOS is prepared by the method for preparing a VDMOS trench type electric field modulation variable doping terminal described in the first aspect.

[0006] The advantages of the present invention are: 1. The present invention arranges a high-resistivity conductor layer on the top of the device terminal structure. When the drain is subjected to voltage, there is a voltage difference between the source metal layer and the cutoff ring metal layer. The high-resistivity conductor layer makes the voltage evenly distributed in the region, thereby forming a uniformly distributed electric field under the insulating layer, thereby suppressing the breakdown problem caused by the electric field concentration near the P+ well region; 2. The present invention constructs a first P-type doping region, a second P-type doping region and a third P-type doping region with gradually decreasing concentration, gradually decreasing width and gradually increasing depth from the P+ well region to the cutoff ring metal layer. The first P-type doping region reduces the electric field strength at the interface with the P+ well region, the second P-type doping region reduces the electric field strength at the interface with the first P-type doping region, and the third P-type doping region reduces the electric field strength at the interface with the second P-type doping region and the drift layer; 3. The gradual increase in the depth of the first P-type doping region, the second P-type doping region and the third P-type doping region is to extend the interface with the largest electric field intensity toward the inside of the device, so as to avoid the electric field on the device surface affecting the electric field distribution near the cut-off ring metal layer and affecting the device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0008] Figure 1The schematic diagram of a VDMOS trench type electric field modulation variable doping terminal of the present invention.

[0009] Figure 2 A cross-sectional view of the process of a VDMOS trench type electric field modulation variable doping terminal of the present invention Figure 1 .

[0010] Figure 3 A cross-sectional view of the process of a VDMOS trench type electric field modulation variable doping terminal of the present invention Figure 2 .

[0011] Figure 4 A cross-sectional view of the process of a VDMOS trench type electric field modulation variable doping terminal of the present invention Figure 3 .

[0012] Figure 5 A cross-sectional view of the process of a VDMOS trench type electric field modulation variable doping terminal of the present invention Figure 4 .

[0013] Figure 6 A cross-sectional view of the process of a VDMOS trench type electric field modulation variable doping terminal of the present invention Figure 5 .

[0014] Figure 7 A cross-sectional view of the process of a VDMOS trench type electric field modulation variable doping terminal of the present invention Figure 6 .

[0015] Figure 8 A cross-sectional view of the process of a VDMOS trench type electric field modulation variable doping terminal of the present invention Figure 7 .

[0016] Fig. 9 A cross-sectional view of the process of a VDMOS trench type electric field modulation variable doping terminal of the present invention Figure 8 .

[0017] Fig.10 A cross-sectional view of the process of a VDMOS trench type electric field modulation variable doping terminal of the present invention Figure 9 .

[0018] Fig.11 A cross-sectional view of the process of a VDMOS trench type electric field modulation variable doping terminal of the present invention Figure 10 .

[0019] Fig.12 A cross-sectional view of the process of a VDMOS trench type electric field modulation variable doping terminal of the present invention Figure 10 one.

[0020] Fig.13 A cross-sectional view of the process of a VDMOS trench type electric field modulation variable doping terminal of the present invention Figure 10two. DETAILED DESCRIPTION

[0021] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0023] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0024] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0025] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0026] like Figures 1 to 13 As shown, the embodiment of the present application provides a method for preparing a VDMOS trench type electric field modulation variable doping terminal, comprising the following steps: Step 1: epitaxially grow a side surface of a silicon carbide substrate 1 to obtain a drift layer 2; Step 2, forming a barrier layer 8 on the drift layer 2, etching the barrier layer 8 to form a through hole, and implanting ions to form a P+ well region 21 and a P+ region 25; Step 3, removing the barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and etching the drift layer 2 to form a first groove 26, a second groove 27 and a third groove 28; Step 4, removing the barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and etching downward the second groove 27 and the third groove 28; Step 5, removing the barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and etching downwardly a third groove 28; Step 6, removing the barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, depositing silicon carbide material, and forming a first P-type trench region 222; Step 7, removing the barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, depositing silicon carbide material, and forming a second P-type trench region 232; Step 8, removing the barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, depositing silicon carbide material, and forming a third P-type trench region 242; Step 9, remove the barrier layer 8, re-form the barrier layer 8, set the temperature to 1200 degrees Celsius, set the time to 80 minutes, perform thermal diffusion and redistribution on the first P-type trench area 222, the second P-type trench area 232 and the third P-type trench area 242 to form the first P-type doping area 221, the second P-type doping area 231 and the third P-type doping area 241; the main junction 22 includes the first P-type doping area 221 and the first P-type trench area 222; the first field limiting ring 23 includes the second P-type doping area 231 and the second P-type trench area 232; the second field limiting ring 24 includes the third P-type doping area 241 and the third P-type trench area 242, and the P+ well area 21, the first P-type doping area 221, the second P-type doping area 231 and the third P-type doping area 241 are connected in sequence; Step 10, removing the barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and depositing to form an insulating layer 3; Step 11, removing the barrier layer 8, re-forming the barrier layer 8, etching the barrier layer 8 to form a through hole, and depositing to form a source metal layer 7 and a stop ring metal layer 4; Step 12: remove the barrier layer 8, re-form the barrier layer 8, etch the barrier layer 8 to form a through hole, deposit to form a high resistivity conductor layer 6, and remove the barrier layer 8.

[0027] In this embodiment, preferably, the lower side surface of the first P-type doping region 221 , the lower side surface of the second P-type doping region 231 , and the lower side surface of the third P-type doping region 241 are all arc-shaped.

[0028] In this embodiment, preferably, the depth of the P+ region 25 is less than the depth of the first P-type doping region 221 .

[0029] In this embodiment, preferably, it also includes a high-resistivity conductor layer 6, the lower side of the high-resistivity conductor layer 6 is connected to the insulating layer 3, the left side of the high-resistivity conductor layer 6 is connected to the source metal layer 7, and the right side of the high-resistivity conductor layer 6 is connected to the cut-off ring metal layer 4.

[0030] In this embodiment, preferably, the thickness of the high resistivity conductor layer 6 is greater than the thickness of the insulating layer 3 .

[0031] like Figure 1 As shown, the terminal obtained by the above manufacturing method includes: A silicon carbide substrate 1; a drain metal layer 5 is provided on the lower side of the silicon carbide substrate 1; A drift layer 2, wherein the drift layer 2 is disposed on the upper side of the silicon carbide substrate 1, wherein a P+ well region 21, a main junction 22, a first field limiting ring 23, a second field limiting ring 24 and a P+ region 25 are disposed in the drift layer 2, wherein the P+ well region 21, the main junction 22, the first field limiting ring 23 and the second field limiting ring 24 are connected in sequence, and the P+ region 25 is disposed at one end of the drift layer 2 and is located on one side of the second field limiting ring 24; an insulating layer 3, wherein the lower side of the insulating layer 3 is respectively connected to the P+ well region 21, the main junction 22, the first field limiting ring 23, the second field limiting ring 24, the drift layer 2 and the P+ region 25; the width of the main junction 22 is greater than the width of the first field limiting ring 23, and the width of the first field limiting ring 23 is greater than the width of the second field limiting ring 24; the depth of the main junction 22 is less than the depth of the first field limiting ring 23, and the depth of the first field limiting ring 23 is less than the depth of the second field limiting ring 24; A stop ring metal layer 4 , the lower side of which is connected to the P+ region 25 ; and a source metal layer 7 connected to the P+ region 25 and the drift layer 2 .

[0032] In this embodiment, preferably, the main junction 22 includes a first P-type doping region 221 and a first P-type groove region 222, the first P-type doping region 221 is connected to the P+ well region 21, and the first P-type groove region 222 is arranged in the first P-type doping region 221; the first field limiting ring 23 includes a second P-type doping region 231 and a second P-type groove region 232, the second P-type groove region 232 is arranged in the second P-type doping region 231, and the second P-type doping region 231 is connected to the first P-type doping region 221; the second field limiting ring 24 includes a third P-type doping region 241 and a third P-type groove region 242, the third P-type groove region 242 is arranged in the third P-type doping region 241, and the third P-type doping region 241 is connected to the second P-type doping region 231; The width of the first P-type trench region 222 is greater than the width of the second P-type trench region 232 , and the width of the second P-type trench region 232 is greater than the width of the third P-type trench region 242 ; The depth of the first P-type trench region 222 is less than the depth of the second P-type trench region 232 , and the depth of the second P-type trench region 232 is less than the depth of the third P-type trench region 242 ; The width of the first P-type doping region 221 is greater than the width of the second P-type doping region 231 , and the width of the second P-type doping region 231 is greater than the width of the third P-type doping region 241 ; The depth of the first P-type doping region 221 is smaller than the depth of the second P-type doping region 231 , and the depth of the second P-type doping region 231 is smaller than the depth of the third P-type doping region 241 .

[0033] In this embodiment, preferably, the doping concentration of the first P-type trench region 222 is greater than the doping concentration of the second P-type trench region 232 , and the doping concentration of the second P-type trench region 232 is greater than the doping concentration of the third P-type trench region 242 ; The doping concentration of the first P-type doping region 221 is greater than the doping concentration of the second P-type doping region 231 , and the doping concentration of the second P-type doping region 231 is greater than the doping concentration of the third P-type doping region 241 .

[0034] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer is 5-9e16cm -3 The doping concentration of the third P-type doping region 241 is 2-8e16cm -3 The doping concentration of the second P-type doping region 231 is 0.8-5e17cm -3 The doping concentration of the first P-type doping region 221 is 0.5-5e18cm -3 The doping concentrations of the P+ well region 21 and the P+ region 25 are both 5-8e18cm -3 The doping concentration of the third P-type trench region 242 is 2-8e17cm -3 The doping concentration of the second P-type trench region 232 is 0.8-5e18cm -3 The doping concentration of the first P-type doping region 221 is 0.5-5e19cm -3 , the material of the insulating layer 3 can be silicon dioxide, the materials of the source metal layer 7 and the stop ring metal layer 4 can be one metal or an alloy of several metals among Al, Cu, and Ni, and the high resistivity conductor layer 6 is SIPOS material or low-doped polysilicon; The doping concentrations of the silicon carbide substrate 1, the drift layer 2, and the p+ well region 21 are considered in the traditional design structure of the planar gate silicon carbide VDMOS device. The doping concentrations of the third P-type trench region 242, the second P-type trench region 232, and the first P-type trench region 222 are to form the third P-type doping region 241, the second P-type doping region 231, and the first P-type doping region 221 of corresponding concentrations under the conditions of the thermal diffusion process. The doping concentrations of the third P-type doping region 241, the second P-type doping region 231, and the first P-type doping region 221 are to form a distribution in which the P-type doping concentration gradually decreases from the P+ well region 21 to the first P-type doping region 221, the second P-type doping region 231, the third P-type doping region 241 to the stop ring metal layer 4. like Figure 1As shown, d1 is 10 μm, d2 is 6 μm, d3 is 3 μm, w1 is 2 μm, w2 is 1 μm, and w3 is 0.5 μm. This is the distribution of thermal diffusion after the width design optimized for the electric field distribution matching the doping concentration and under the doping conditions in the trench area; The depth of the P+ well region 21 is 1 μm, the depth of the first P-type doping region 221 is 1.5 μm, the depth of the second P-type doping region 231 is 2 μm, the depth of the third P-type doping region 241 is 3 μm, the depth of the third P-type trench region 242 is 2 μm, the depth of the second P-type trench region 232 is 1.2 μm, and the depth of the first P-type trench region 222 is 0.7 μm. This is to form a structure in which the depth of the P+ well region 21, the first P-type doping region 221, the second P-type doping region 231, and the third P-type doping region 241 gradually increases, and the depth of the trench region is to form a doping region of corresponding depth; The doping area in the device terminal is prepared by thermal diffusion. Due to the etching of the groove, the thermal diffusion depth of the device can be guaranteed. Compared with ion implantation, thermal diffusion causes less damage to the device lattice, and the device has higher reliability and stability. The thickness of the device's insulating layer 3 is 100 nm, the thickness of the high resistivity conductor layer 6 is 500 nm, and the thickness of the source metal layer 7 and the cutoff ring metal layer 4 are both 600 nm; By arranging a high resistivity conductor layer 6 on the top of the device terminal structure, when the drain is subjected to voltage, there is a voltage difference between the source metal layer 7 and the cut-off ring metal layer 4. The high resistivity conductor layer 6 makes the voltage evenly distributed in the region, thereby forming a uniformly distributed electric field under the insulating layer 3, thereby suppressing the breakdown problem caused by the electric field concentration near the P+ well region 21; A first P-type doping region 221, a second P-type doping region 231 and a third P-type doping region 241 are constructed in the direction extending from the P+ well region 21 to the cut-off ring metal layer 4, with their concentrations gradually decreasing, their widths gradually decreasing and their depths gradually increasing. The first P-type doping region 221 reduces the electric field strength at the interface with the P+ well region 21, the second P-type doping region 231 reduces the electric field strength at the interface with the first P-type doping region 221, and the third P-type doping region 241 reduces the electric field strength at the interface with the second P-type doping region 231 and the drift layer 2. The function of the P+ region 25 is to guide the potential of the cut-off ring metal layer 4 to the inside of the electrical appliance to ensure that the reverse withstand voltage of the device is not affected.

[0035] The gradual increase in the depth of the first P-type doping region 221, the second P-type doping region 231 and the third P-type doping region 241 is to extend the interface with the largest electric field intensity toward the inside of the device, so as to avoid the electric field affecting the electric field distribution near the cut-off ring metal layer 4 at the device surface and affecting the device reliability.

[0036] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a VDMOS trench type electric field modulation variable doping terminal, characterized in that: The steps include: Step 1: epitaxially grow a drift layer on the side of a silicon carbide substrate; Step 2, forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a P+ well region and a P+ region; Step 3, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching the drift layer to form a first groove, a second groove, and a third groove; Step 4, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching downwardly the second groove and the third groove; Step 5, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching downward a third groove; Step 6: remove the barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit silicon carbide material, and form a first P-type trench region; Step 7, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing silicon carbide material, and forming a second P-type trench region; Step 8, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing silicon carbide material, and forming a third P-type trench region; Step 9, removing the barrier layer, re-forming the barrier layer, and performing thermal diffusion and redistribution on the first P-type trench region, the second P-type trench region, and the third P-type trench region at a set temperature and a set time to form a first P-type doping region, a second P-type doping region, and a third P-type doping region; the main junction includes the first P-type doping region and the first P-type trench region; the first field limiting ring includes the second P-type doping region and the second P-type trench region; the second field limiting ring includes the third P-type doping region and the third P-type trench region, and the P+ well region, the first P-type doping region, the second P-type doping region, and the third P-type doping region are connected in sequence; Step 10, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating layer; Step 11, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form a source metal layer and a stop ring metal layer; Step 12: remove the barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit to form a high resistivity conductor layer, and remove the barrier layer.

2. The method for preparing a VDMOS trench type electric field modulation variable doping terminal according to claim 1, characterized in that: The step 9 is specifically as follows: removing the barrier layer, re-forming the barrier layer, setting the temperature to 1200 degrees Celsius, setting the time to 80 minutes, performing thermal diffusion and redistribution on the first P-type trench region, the second P-type trench region and the third P-type trench region to form the first P-type doping region, the second P-type doping region and the third P-type doping region; the main junction includes the first P-type doping region and the first P-type trench region; the first field limiting ring includes the second P-type doping region and the second P-type trench region; the second field limiting ring includes the third P-type doping region and the third P-type trench region, and the P+ well region, the first P-type doping region, the second P-type doping region and the third P-type doping region are connected in sequence; The width of the first P-type trench region is greater than the width of the second P-type trench region, and the width of the second P-type trench region is greater than the width of the third P-type trench region; The depth of the first P-type trench region is less than the depth of the second P-type trench region, and the depth of the second P-type trench region is less than the depth of the third P-type trench region; The width of the first P-type doping region is greater than the width of the second P-type doping region, and the width of the second P-type doping region is greater than the width of the third P-type doping region; The depth of the first P-type doping region is less than the depth of the second P-type doping region, and the depth of the second P-type doping region is less than the depth of the third P-type doping region.

3. A method for preparing a VDMOS trench type electric field modulation variable doping terminal according to claim 2, characterized in that: The doping concentration of the first P-type trench region is greater than the doping concentration of the second P-type trench region, and the doping concentration of the second P-type trench region is greater than the doping concentration of the third P-type trench region; The doping concentration of the first P-type doping region is greater than the doping concentration of the second P-type doping region, and the doping concentration of the second P-type doping region is greater than the doping concentration of the third P-type doping region.

4. The method for preparing a VDMOS trench type electric field modulation variable doping terminal according to claim 2, characterized in that: The lower side surface of the first P-type doping region, the lower side surface of the second P-type doping region, and the lower side surface of the third P-type doping region are all arc-shaped.

5. The method for preparing a VDMOS trench type electric field modulation variable doping terminal according to claim 2, characterized in that: The depth of the P+ region is less than the depth of the first P-type doping region.

6. The method for preparing a VDMOS trench type electric field modulation variable doping terminal according to claim 1, characterized in that: The invention also includes a high-resistivity conductor layer, wherein a lower side of the high-resistivity conductor layer is connected to the insulating layer.

7. A method for preparing a VDMOS trench type electric field modulation variable doping terminal according to claim 6, characterized in that: The thickness of the high resistivity conductor layer is greater than the thickness of the insulating layer.

8. A VDMOS trench type electric field modulation variable doping terminal, characterized in that: The terminal is prepared by the preparation method described in any one of claims 1 to claim 7.

Images