Group III nitride transistor with high N doping in access region

Abstract

Group III nitride transistors with high N doping in the access region. The new transistor structure for use with a group III nitride semiconductor structure includes a heavily doped n + + layer in a source region and a drain region. Source and drain electrodes are disposed on their respective heavily doped n + + layers. Further, in some embodiments, a portion of the gate electrode may be disposed on one or both of the heavily doped n + + regions. These regions improve the on-resistance of the transistor, especially for low voltage applications.

Description

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 548,315 filed on November 13, 2023 and U.S. Patent Application No. 18 / 937,593 filed on November 5, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of the present disclosure relate to a transistor and a method for making a transistor with low on-resistance in low voltage applications. Background Art

[0003] Figure 1 A typical conventional III-nitride semiconductor transistor is shown, which includes a substrate 1, a buffer layer 2 located on top of the substrate, a GaN channel layer 3 located on top of the buffer layer, and an AlGaN barrier layer 4 located on top of the channel layer. The substrate 1 is SiC, sapphire, Si or a self-supporting GaN semiconductor. A nucleation layer exists between the buffer layer 2 and the substrate 1. The AlGaN barrier layer 4 has a wider band gap than the GaN channel 3. A source electrode 7 and a drain electrode 8 are arranged on opposite sides of the gate electrode 6.

[0004] This structure has the disadvantage of relatively high on-resistance for low voltage applications due to access area resistance and contact resistance.

[0005] Therefore, it might be beneficial if there were new transistor structures that overcome the shortcomings of conventional device structures. Summary of the invention

[0006] A new transistor structure for use with a III-nitride semiconductor structure is disclosed. The transistor includes a heavily doped n++ layer located in a source region and a drain region. The source electrode and the drain electrode are disposed on their respective heavily doped n++ layers. In addition, in some embodiments, a portion of the gate electrode may be disposed on one or both of the heavily doped n++ regions. These regions improve the on-resistance of the transistor, particularly for low voltage applications.

[0007] According to one embodiment, a semiconductor structure for use in a III-nitride (III-N) semiconductor device is disclosed. The structure includes: a channel layer; a barrier layer, wherein electrons are formed at an interface between the channel layer and the barrier layer; a source electrode disposed in a source region and a drain electrode disposed in a drain region; a gate electrode disposed in the gate region between the source electrode and the drain electrode; a capping layer disposed between at least a portion of the gate electrode and the barrier layer; and a heavily doped n++ layer disposed on either side of the capping layer; wherein the source electrode and the drain electrode each contact at least a portion of the corresponding heavily doped n++ layer. In some embodiments, the heavily doped n++ layer has a higher n-type doping density than the capping layer. In some embodiments, the heavily doped n++ layer has at least 1e18 cm -3 n-type doping density. In some embodiments, the heavily doped n++ layer has a different n-type doping distribution from the capping layer in the vertical direction. In some embodiments, the top surface of the heavily doped n++ layer is flush with the top surface of the capping layer. In some embodiments, the top surface of the heavily doped n++ layer is uneven, and the portion of the top surface adjacent to the capping layer is flush with the top surface of the capping layer. In some embodiments, the portion has a length between 0nm and 2000nm. In some embodiments, a portion of the gate electrode is disposed on the heavily doped n++ layer in the source region. In certain embodiments, a portion of the gate electrode is disposed on the heavily doped n++ layer in the drain region. In some embodiments, the heavily doped n++ layer is disposed on top of the barrier layer. In some embodiments, the heavily doped n++ layer is at least partially disposed in the barrier layer. In some embodiments, the heavily doped n++ layer is disposed on top of the channel layer. In some embodiments, the heavily doped n++ layer is at least partially disposed in the channel layer.

[0008] According to another embodiment, a semiconductor structure for use in a III-nitride (III-N) semiconductor device is disclosed. The structure includes: a channel layer; a barrier layer, wherein electrons are formed at an interface between the channel layer and the barrier layer; a source electrode disposed in a source region and a drain electrode disposed in a drain region; a capping layer disposed on top of the barrier layer in a gate region; a gate recess disposed in the gate region, between the source electrode and the drain electrode, through the capping layer; a gate electrode disposed in the gate recess; and a heavily doped n++ layer disposed on either side of the capping layer; wherein the source electrode and the drain electrode each contact at least a portion of the corresponding heavily doped n++ layer. In some embodiments, the gate recess extends to a top surface of the barrier layer. In some embodiments, the gate recess extends through at least a portion of the barrier layer. In some embodiments, a gate dielectric layer is disposed along a bottom and a wall of the gate recess, and a gate electrode is disposed on the gate dielectric layer. In some embodiments, the gate recess extends through a portion of one or more of the heavily doped n++ layers. In some embodiments, the heavily doped n++ layer has a higher n-type doping density than the capping layer. In some embodiments, the heavily doped n++ layer has a different n-type doping profile in the vertical direction than the capping layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a better understanding of the present disclosure, reference is made to the drawings which are incorporated herein by reference, and wherein:

[0010] Figure 1 shows the layout of a conventional III-nitride transistor according to the prior art;

[0011] Figure 2 An improved III-nitride transistor including a heavily doped n++ region is shown;

[0012] Figure 3 Shows Figure 2 A variation of the III-nitride transistor;

[0013] Figure 4 Shows Figure 3 A variation of the III-nitride transistor;

[0014] Figure 5 Shows Figure 3 A variation of the III-nitride transistor;

[0015] Figure 6 Shows Figure 4 A variation of a III-nitride transistor; and

[0016] Figure 7 is a flow chart showing a sequence for fabricating the Group III-nitride transistor shown in any of the figures. DETAILED DESCRIPTION

[0017] The present disclosure describes a III-nitride transistor device having lower on-resistance.

[0018] refer to Figure 2 The transistor structure includes a substrate 10, a buffer layer 11, a channel layer 12, a barrier layer 13, and a capping layer 14. In many embodiments, a nucleation layer may be disposed between the substrate 10 and the buffer layer 11.

[0019] The substrate 10 may be SiC, sapphire, Si, free-standing GaN or any other substrate including multiple layers of polycrystalline AlN. A nucleation layer may be disposed between the buffer layer 11 and the surface of the substrate 10. The nucleation layer may include AlN.

[0020] The buffer layer 11 is formed on the nucleation layer. The buffer layer 11 may have a thickness between 0.5 nm and several microns, but other thicknesses are also within the scope of the present disclosure. The buffer layer 11 may include a Group III nitride semiconductor, including GaN, AlGaN, InGaN, InAlN, InAlGaN, and AlN.

[0021] The channel layer 12 is formed on the buffer layer 11. The channel layer 12 includes a semiconductor material selected from AlGaN, InGaN, GaN, or any other suitable semiconductor material or material combination.

[0022] Carriers, which may be free electrons, exist in the channel layer 12 to conduct current between the drain contact and the source contact.

[0023] The channel layer 12 may include a single layer (such as a GaN layer) or multiple layers. In one example, the channel layer 12 includes a back barrier structure, such as a GaN layer on an AlGaN layer (GaN / AlGaN) or a GaN layer on an InGaN layer and another GaN layer (GaN / InGaN / GaN). In another example, the channel layer 12 has a superlattice structure formed by repeating a double-layer structure of AlGaN / GaN or AlN / GaN. The thickness of the channel layer 12 may be greater than 5 nm, such as between 50 nm and 400 nm, but other thicknesses may also be used.

[0024] The barrier layer 13 is formed on the channel layer 12. The barrier layer 13 may be made of a III-group nitride semiconductor selected from AlGaN, InAlN, AlN, AlScN, or InAlGaN with a non-zero aluminum content. The barrier layer 13 may be undoped or doped with Si or other impurities. The barrier layer 13 has a wider band gap than the channel layer 12. The barrier layer 13 may be between 0.2nm and 30nm. A thin barrier layer may be used, such as less than 10nm. The barrier layer 13 may include sublayers. For example, a sublayer of AlN may be adjacent to the channel layer 12, and an AlGaN or InAlN sublayer may be disposed on top of the AlN sublayer.

[0025] The capping layer 14 includes a group III nitride semiconductor, such as GaN, AlN, AlGaN, or a combination of these. The capping layer 14 may be n-type doped, or may be undoped. In some embodiments, the capping layer 14 may have a thin incremental doping layer. The capping layer 14 may also have different doping levels in the vertical direction. The capping layer 14 may also include sublayers. For example, the bottom of the capping layer 14 may have a sublayer made of AlN or AlGaN as an etch stop layer, and the top of the capping layer 14 may have a sublayer made of GaN disposed on top of the bottom of the capping layer. The thickness of the capping layer 14 may be less than 200nm, such as between 0.5nm and 50nm.

[0026] The top of the device structure includes a gate electrode 15 , a source electrode 16 and a drain electrode 17 .

[0027] On the opposite side of the gate, a heavily n-type doped (n++) layer 18 is formed on top of the barrier layer 13. One such heavily doped n++ layer is called the source region, and the other heavily doped n++ layer is called the drain region. The composition of the heavily doped n++ layer 18 can be different from that of the capping layer 14, or it can be the same. In addition, the heavily doped n++ layer differs from the capping layer 14 in terms of doping profile. The heavily doped n++ layer 18 has a doping profile higher than 1e18 cm -3 In some embodiments, the heavily doped n++ layer 18 may have an n-type doping density of 1e20 cm -3Or higher n-type doping density. The capping layer 14 may have a lower doping density or a different doping distribution in the vertical (or height) direction. The n-type dopant may be Si. The heavily doped n++ layer 18 is made of a Group III nitride semiconductor, such as GaN, InGaN, AlGaN. The heavily doped n++ layer 18 may not have the same sublayers as in the capping layer 14. For example, the etch stop sublayer in the capping layer 14 may not be present in the heavily doped n++ layer 18. The heavily doped n++ layer 18 may be formed by epitaxial growth, such as molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). The heavily doped n++ layer 18 may also be formed by ion implantation.

[0028] The source electrode 16 and the drain electrode 17 are deposited on the heavily doped n++ layer 18 in the source region and the drain region, respectively. The source electrode 16 and the drain electrode 17 contact at least a portion of the heavily doped n++ layer 18 in the source region and the drain region, respectively. The source electrode 16 and the drain electrode 17 can be made of Ti, TiN, Al, W, Au, or other suitable materials and / or a combination of materials that form an ohmic contact with the heavily doped n++ layer 18. The gate electrode 15 is deposited on the capping layer 14. The gate electrode 15 can be made of materials such as Ni, Ti, TiN, W, WN, Pt, Al, Au, polysilicon, and any other suitable conductive materials and combinations thereof.

[0029] A passivation dielectric material 19 may be deposited on top of the cap layer 14 and the exposed portion of the heavily doped n++ layer 18. The passivation dielectric material 19 may be made of a dielectric material such as SiO2, Si x N y 、SiO x N y , Al2O3, HfO2 and any other suitable dielectric material.

[0030] Figure 2 The top of the heavily doped n++ layer 18 and the top of the capping layer 14 are shown aligned at the same height at their bonding boundary such that the top surface of the heavily doped n++ layer 18 is flush with the top surface of the capping layer 14 . Figure 2 It is also shown that the top surface of the heavily doped n++ layer 18 is flat. However, other embodiments are possible.

[0031] Figure 3 An example of a heavily doped n++ layer 18 having a non-flat surface in the source region and the drain region is shown. The height difference of the heavily doped n++ layer 18 can be several hundred nanometers. At the boundary between the heavily doped n++ layer 18 and the capping layer 14, the portion of the heavily doped n++ layer 18 having a length L has the same height and is flush with the top surface of the capping layer 14. The length L can range from 0 nm to more than 2000 nm. Figure 3Other components in the Figure 2 Described.

[0032] Note that Figure 2 and Figure 3 In the embodiment shown in FIG. 1 , the gate electrode 15 does not overlap the heavily doped n++ layer 18. However, other embodiments are also possible.

[0033] exist Figure 4 In another embodiment shown in , the gate electrode 15 is formed on a portion of the top surface of the capping layer 14 and overlaps the heavily doped n++ layer 18 in the source region. In another embodiment (not shown), the gate electrode 15 can overlap the heavily doped n++ layer 18 in both the source region and the drain region. The gate electrode 15 can form a Schottky contact with the capping layer 14, or a gate dielectric material can be provided between the gate electrode 15 and the capping layer 14 and the heavily doped n++ layer 18 below. Figure 4 Other components in the Figure 2 Described.

[0034] In the aforementioned embodiment, the heavily doped n++ layer 18 is provided on top of the barrier layer 13. However, other embodiments are also possible.

[0035] like Figure 5 As shown, the heavily doped n++ layer 18 may extend through the barrier layer 13 and into the channel layer 12. In another embodiment (not shown), the heavily doped n++ region may extend into the barrier layer 13 but not into the channel layer 12. In another embodiment (not shown), the heavily doped n++ region may extend through the barrier layer 13 and be disposed on top of the channel layer 12. Figure 5 Other components in the Figure 2 Described.

[0036] Figure 6 Another embodiment is shown, in which the gate recess is formed in the gate region through the cap layer 14 and a portion of the heavily doped n++ layer 18 in the source region. The gate recess may also be etched through a portion of the heavily doped n++ layer 18 in both the source region and the drain region. Figure 6 As shown, the bottom of the gate recess may be located at the top surface of the barrier layer 13, or located inside the barrier layer 13 or in the channel layer 12. A gate dielectric layer 20 is formed in the gate recess, and a gate electrode 15 is formed on the gate dielectric layer 20. The gate dielectric layer 20 may be along the bottom and side of the gate recess. The gate dielectric layer 20 may be made of a dielectric material, such as Si. x N y 、SiO2、Si x O y N z, Al2O3, AlN, AlOxNy or any other suitable dielectric material or combinations thereof. Figure 6 Other components in the Figure 2 Descriptive.

[0037] Note that these are not the only implementations. For example, Figure 2 The flat heavily doped n++ layer 18 shown in FIG. Figures 4 to 6 any embodiment of the present invention may be used together with Figure 5 The deeper heavily doped n++ layer 18 shown in FIG. 1 may also be connected to Figure 4 The offset gate electrode 15 shown in Figure 6 The gate dielectric layer 20 shown in FIG. Figure 6 The gate recess and gate dielectric layer 20 shown in FIG. Figures 2 to 5 any embodiment of the present invention may be used together with

[0038] Figures 2 to 6 Each transistor shown in the figure can be a normally-on transistor in which there are electrons in the channel layer 12 below the gate electrode 15 connecting the source and the drain when the gate electrode 15 is not biased, or it can be a normally-off transistor in which there are no electrons in the channel layer 12 below the gate when the gate electrode 15 is not biased.

[0039] Figure 7 Shows that it can be used to create Figure 2 The manufacturing sequence of the device structure is as follows. First, as shown in box 700, a buffer layer 11, a channel layer 12, a barrier layer 13, and a capping layer 14 are deposited on the substrate 10. Then, as shown in box 710, a sacrificial dielectric layer is deposited on top of the capping layer 14. The area in which the heavily doped n++ layer 18 will be formed is then etched. The etching extends at least through the sacrificial layer and the capping layer 14. In some embodiments, the etching extends into the barrier layer 13 and optionally into the channel layer 12. Next, as shown in box 720, a heavily doped n++ layer 18 is grown in the etched area. This can be done using MBE or MOCVD.

[0040] Next, as shown in block 730, the sacrificial dielectric layer and any n++ layers grown on the sacrificial layer are removed. As shown in block 740, a passivation dielectric material 19 can then be deposited on the top surface of the structure. As shown in block 750, the passivation dielectric material 19 is then etched to form an opening for the gate electrode 15. The gate electrode 15 is then formed in the opening. Finally, as shown in block 760, the passivation dielectric material is etched to form openings for the source electrode 16 and the drain electrode 17. These electrodes are then formed in these openings.

[0041] There are variations in this manufacturing sequence. For example, the order of forming the gate electrode 15 and the source and drain electrodes can be changed. In addition, additional process steps not shown here include depositing additional dielectric layers, forming field plates and interconnects.

[0042] Furthermore, additional passivation dielectric and field plate structures can be applied to Figures 2 to 6 In addition, the gate electrode 15, the source electrode 16 and the drain electrode 17 may have overhanging or inclined sidewalls instead of Figures 2 to 6 The rectangular shape shown in .

[0043] The system described herein has many advantages. The use of heavily doped n++ layer 18 reduces on-resistance even in low voltage applications. In addition, the shape of the heavily doped n++ region reduces transistor source resistance and parasitic capacitance.

[0044] The scope of the present disclosure is not limited by the specific embodiments described herein. In fact, according to the foregoing description and the accompanying drawings, in addition to those described herein, various other embodiments and modifications of the present disclosure are obvious to those of ordinary skill in the art. Therefore, such other embodiments and modifications are intended to fall within the scope of the present disclosure. In addition, although the present disclosure has been described herein in the context of a specific implementation for a specific purpose in a specific environment, it will be appreciated by those of ordinary skill in the art that its usefulness is not limited thereto, and the present disclosure can be advantageously implemented for any number of purposes in any number of environments. Therefore, the claims set forth below should be interpreted according to the full breadth and spirit of the present disclosure as described herein.

Claims

1. A semiconductor structure for use in a III-nitride (III-N) semiconductor device, comprising: Channel layer; a blocking layer, wherein electrons are formed at an interface between the channel layer and the blocking layer; A source electrode disposed in the source region and a drain electrode disposed in the drain region; a gate electrode disposed in the gate region and between the source electrode and the drain electrode; a capping layer disposed between at least a portion of the gate electrode and the barrier layer; and a heavily doped n++ layer disposed on either side of the capping layer; The source electrode and the drain electrode each contact at least a portion of a corresponding heavily doped n++ layer.

2. The semiconductor structure according to claim 1, wherein: The heavily doped n++ layer has a higher n-type doping density than the capping layer.

3. The semiconductor structure according to claim 1, wherein: The heavily doped n++ layer has a doping strength of at least 1e18 cm -3 The n-type doping density.

4. The semiconductor structure according to claim 1, wherein: The heavily doped n++ layer has a different n-type doping profile in the vertical direction than the capping layer.

5. The semiconductor structure according to claim 1, wherein: A top surface of the heavily doped n++ layer is flush with a top surface of the capping layer.

6. The semiconductor structure according to claim 1, wherein: A top surface of the heavily doped n++ layer is not flat, and a portion of the top surface adjacent to the capping layer is flush with a top surface of the capping layer.

7. The semiconductor structure according to claim 6, wherein: The portion has a length between 0 nm and 2000 nm.

8. The semiconductor structure according to claim 1, wherein: A portion of the gate electrode is disposed on the heavily doped n++ layer in the source region.

9. The semiconductor structure according to claim 8, wherein: A portion of the gate electrode is disposed on the heavily doped n++ layer in the drain region.

10. The semiconductor structure according to claim 1, wherein: The heavily doped n++ layer is disposed on top of the barrier layer.

11. The semiconductor structure according to claim 1, wherein: The heavily doped n++ layer is at least partially disposed in the barrier layer.

12. The semiconductor structure according to claim 1, wherein: The heavily doped n++ layer is disposed on top of the channel layer.

13. The semiconductor structure according to claim 1, wherein: The heavily doped n++ layer is at least partially disposed in the channel layer.

14. A semiconductor structure for use in a III-nitride (III-N) semiconductor device, comprising: Channel layer; a blocking layer, wherein electrons are formed at an interface between the channel layer and the blocking layer; A source electrode disposed in the source region and a drain electrode disposed in the drain region; a capping layer disposed on top of the barrier layer in the gate region; a gate recess, disposed in the gate region, between the source electrode and the drain electrode, and passing through the cover layer; a gate electrode disposed in the gate recess; and a heavily doped n++ layer disposed on either side of the capping layer; The source electrode and the drain electrode each contact at least a portion of a corresponding heavily doped n++ layer.

15. The semiconductor structure according to claim 14, wherein: The gate recess extends to a top surface of the barrier layer.

16. The semiconductor structure according to claim 14, wherein: The gate recess extends through at least a portion of the barrier layer.

17. The semiconductor structure according to claim 14, wherein: A gate dielectric layer is disposed along a bottom and a wall of the gate recess, and the gate electrode is disposed on the gate dielectric layer.

18. The semiconductor structure according to claim 14, wherein: The gate recess extends through a portion of one or more of the heavily doped n++ layers.

19. The semiconductor structure according to claim 14, wherein: The heavily doped n++ layer has a higher n-type doping density than the capping layer.

20. The semiconductor structure of claim 14, wherein: The heavily doped n++ layer has a different n-type doping profile in the vertical direction than the capping layer.

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