Local heat dissipation FinFET and manufacturing method thereof

Abstract

One example discloses a FinFET semiconductor device, and discloses a corresponding method of manufacture, the device comprising: a substrate having a body region therein, a plurality of elongated fins at a first major surface and within the body region; an oxide layer on the first major surface and partially surrounding a lower portion of the elongated fin; a gate contact extending across and partially surrounding an upper portion of the plurality of elongated fins; a dielectric material between the fin and the gate region; a plurality of elongated partial fins parallel to the plurality of elongated fins and having a height less than that of the plurality of elongated fins; an elongated metal contact extending into the substrate and in electrical contact with the portion of the fins, and forming a body contact; wherein the elongated metal contact extends between two of the elongated partial fins and below an upper surface of the two elongated partial fins, and fills a space between the two elongated partial fins.

Description

Technical Field

[0001] The present disclosure relates to FinFETs. Background Art

[0002] FinFET is a topological configuration of a field effect transistor (FET) in which the channel between the source and drain comprises an elevated structure or "fin" and the gate is typically wrapped around three surfaces of the fin. This structure can provide high channel width values, typically corresponding to the height of the fin plus roughly twice its width, while still allowing a relatively short gate length.

[0003] FinFETs are becoming increasingly important for high frequency and high power devices. As with other 3D topologies, device self-heating is particularly problematic in FinFETs because the primary heat dissipation path is through the substrate and heat from the transistor to the substrate flows through the narrow silicon fins, which is impeded by the 3D nature of the device.

[0004] Conventional FinFETs rely on techniques such as introducing gate dummies or other metal dummies around heat sources, however, this can result in increased parasitic capacitance and increase the area of ​​the device. Summary of the invention

[0005] According to a first aspect of the present disclosure, a FinFET semiconductor device is provided, comprising: a substrate having a main body region, a plurality of elongated fins at a first main surface of the substrate and within the main body region; an oxide layer on the first main surface and partially surrounding the lower portion of the elongated fins; a gate contact extending across the upper portion of the plurality of elongated fins and partially surrounding the upper portion; a dielectric material providing electrical isolation between the fins and the gate region and between the fins and the gate region; a plurality of elongated partial fins parallel to the plurality of elongated fins and having a height less than the height of the plurality of elongated fins; and an elongated metal contact extending into the substrate and in electrical contact with the plurality of elongated partial fins and forming a main body contact of the FinFET; wherein the elongated metal contact extends between two of the plurality of elongated partial fins and below the upper surfaces of the two elongated partial fins, and fills the space between the two elongated partial fins. By replacing a portion of the material between the fins (which is typically a dielectric, such as an oxide with low thermal conductivity) with a metal with high thermal conductivity, heat dissipation from the active area of ​​the device can be improved, thereby reducing the operating temperature of the device.

[0006] In one or more embodiments, the FinFET semiconductor device further includes at least one elongated column between two elongated partial fins of the plurality of elongated partial fins; wherein the elongated metal contact extends to the at least one elongated column between two elongated partial fins of the plurality of elongated partial fins. Removing one or more partial fins and replacing the one or more partial fins with a metal having a relatively high thermal conductivity can further improve the flow of heat away from the active portion of the device. Although in other embodiments, two elongated partial fins of the plurality of elongated partial fins can be two adjacent elongated partial fins, embodiments in which the two elongated partial fins are not adjacent but have an elongated column therebetween can allow for higher conductance into the substrate, and in embodiments in which no column is included between two adjacent partial fins, can help prevent epitaxial silicon (or SiGe) from sealing any gap between the two adjacent partial fins. In yet other embodiments, there can be more than two elongated partial fins with a metal contact therebetween.

[0007] In one or more embodiments, the surfaces of the plurality of elongated portion fins and the surface of at least one elongated column include metal silicide. It should be understood by those skilled in the art that the metal silicide provides good electrical and thermal connections between the metal layer and the elongated portion fins.

[0008] In one or more embodiments, the elongated metal contact includes a first seed metal in contact with the metal silicide and a second metal at other locations. The use of a seed metal may be beneficial to ensure good adhesion and avoid voids or micro-voids within the device.

[0009] In one or more embodiments, a FinFET semiconductor device (wherein the body region has a first conductivity type) further includes an elongated drain region of a second conductivity type opposite to the first conductivity type extending across and electrically connected to the plurality of elongated fins.

[0010] In one or more such embodiments, the elongated drain region is one of a plurality of such drain regions, the plurality of elongated drain regions has a plurality of such drain regions, and the gate contact is one of a plurality of such gate contacts, arranged as a sequence of separated regions in a drain-gate-source-gate-drain-gate-source configuration. The use of multiple fingers arranged staggered between source and drain with a gate therebetween can increase the gate width of the device and can facilitate increasing the power capability of the device.

[0011] In one or more embodiments, the elongated metal contact is adjacent to but spaced apart from the outermost separation region in the sequence.This may be a particularly suitable positioning of the metal to substrate body contact.

[0012] In one or more embodiments, a FinFET semiconductor device (wherein the body region has a first conductivity type) further includes an elongated source region of a second conductivity type opposite to the first conductivity type extending across and electrically connected to the plurality of elongated fins.

[0013] In one or more embodiments, the FinFET device further includes a stack of metal connection layers with interlayer dielectric layers therebetween, wherein the elongated metal contacts extend upward through the lower two of the interlayer dielectric layers.

[0014] In one or more embodiments, the body contact of the FinFET is electrically connected to the source of the FinFET, and the elongated metal contact forms the source contact of the FinFET. The co-location of the body contact and the source contact can allow for a more compact device design, or provide improved electrical stability across multiple circuits.

[0015] According to a second aspect of the present disclosure, a method for manufacturing a FinFET device is provided, the method comprising: providing a substrate having a main body region of a first conductivity type and having a plurality of elongated fins at a first main surface of the substrate and within the main body region; providing an oxide, the oxide being on the first main surface and partially surrounding a lower portion of the elongated fins; providing a gate contact, the gate contact extending across the plurality of elongated fins and partially surrounding the plurality of elongated fins; providing a dielectric material, the dielectric material providing electrical isolation between the fins and the gate region and between the fins and the gate region; etching the elongated fins; a subset of the slender partial fins to form a plurality of elongated partial fins, wherein the height of the plurality of elongated partial fins is less than the height of the plurality of elongated partial fins and the upper surface is at the same height as the upper surface of the oxide layer; removing the oxide layer between two of the plurality of elongated partial fins; and depositing an elongated metal contact, which extends into the substrate and is in electrical contact with the plurality of elongated partial fins to form a body contact of the FinFET, wherein the elongated metal contact extends between two of the plurality of elongated partial fins and below the upper surfaces of the two elongated partial fins and fills the space between the two elongated partial fins.

[0016] In one or more embodiments, the method further includes etching a subset of the plurality of elongated partial fins between two of the plurality of elongated partial fins to form at least one elongated column; and wherein the elongated metal contact extends to the at least one elongated column between two of the plurality of elongated partial fins.

[0017] In one or more embodiments, the method further includes forming a metal silicide at surfaces of the plurality of elongated portion fins and a surface of the at least one elongated pillar.

[0018] In one or more embodiments, the method further includes depositing an elongated metal contact as a first seed metal in contact with the metal silicide and a second metal at other locations.

[0019] In one or more embodiments, the method further includes forming an elongated drain region of a second conductivity type opposite to the first conductivity type extending across and electrically connected to the plurality of elongated fins.

[0020] In one or more embodiments, the method further includes forming an elongated source region of a second conductivity type opposite to the first conductivity type extending across and electrically connected to the plurality of elongated fins.

[0021] In one or more such embodiments, the elongated drain region is one of a plurality of such drain regions, the plurality of elongated drain regions has a plurality of such drain regions, and the gate contact is one of a plurality of such gate contacts, arranged as a sequence of separated regions in a drain-gate-source-gate-drain-gate-source configuration.

[0022] In one or more embodiments, the elongated metal contact is adjacent to but spaced apart from the outermost separation region in the sequence.

[0023] In one or more embodiments, the method further includes forming a stack of metal connection layers with interlayer dielectric layers therebetween, wherein the elongated metal contacts extend upwardly through lower two of the interlayer dielectric layers.

[0024] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Embodiments will be described, by way of example only, with reference to the accompanying drawings, in which:

[0026] Figure 1A , 1B schematically illustrates a cross section through a portion of a FinFET device including a metal trench to a substrate according to an embodiment of the present disclosure;

[0027] Figure 2A shows the heat dissipation flow through the contacts in a conventional FinFET;

[0028] Figure 2B illustrates heat dissipation flow through a contact according to an embodiment of the present disclosure;

[0029] Figures 3A to 3Xshows a schematic cross section through a portion of a FinFET device according to an embodiment of the present disclosure at various stages of fabrication;

[0030] Figure 4 A schematic diagram showing a portion of a partially fabricated FinFET;

[0031] Figure 5 The conventional FinFET is shown Figure 4 The cross section of B-B';

[0032] Figure 6 FIG. 1 shows a FinFET according to one or more embodiments of the present disclosure. Figure 4 The cross section of B-B';

[0033] Figure 7 The conventional FinFET is shown Figure 4 A-A' cross section;

[0034] Figure 8 FIG. 1 shows a FinFET according to one or more embodiments of the present disclosure. Figure 4 A-A' cross section;

[0035] Fig.9A Shown in Figure 3W a schematic cross section through a conventional FinFET device at corresponding stages;

[0036] Fig. 9B Shown in Figure 3X a schematic cross section through a conventional FinFET device at the same stage of fabrication;

[0037] Fig. 10A shows a schematic cross section through a FinFET device according to one or more other embodiments of the present disclosure; and

[0038] Fig. 10B A schematic cross section through a conventional FinFET is shown.

[0039] It should be noted that the figures are diagrammatic and not drawn to scale. For clarity and convenience in the drawings, the relative sizes and proportions of the various parts of these figures have been shown by being exaggerated or reduced in size. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments. DETAILED DESCRIPTION

[0040] Figure 1AA schematic cross section orthogonal to the direction of the fins through a portion of a conventional FinFET 100 is shown. The FinFET 100 includes a substrate having a well 110 of a first conductivity type adjacent to a first major surface. For the sake of clarity and without limitation, the well will be considered to be an N-type well, also referred to as an N-well. A plurality of elongated fins 120 are formed in the N-well. The fins protrude above the surface of the substrate. Typically, as will be discussed in more detail below, the fins are defined by providing a patterned mask on top of the substrate and etching in the substrate material, thereby removing material between the fins and causing the fins to protrude above the newly defined surface. Figure 1A , the fins extend into the page. Two such fins are shown. In the space between and around the fins, there is an oxide layer as shown, which is generally referred to as field oxide 130. The fin protrudes above the surface of the field oxide. The protruding portion of the fin is covered by a dielectric 140, which may generally include a dielectric layer stack, including a grown thermal oxide 142 and a high-k dielectric 144. The protruding portion of the fin is covered by a barrier metal 146, a work function metal 148, and a gate electrode metal 150. The dielectric 140 separates the fin from the gate 150. Alternatively, a gate metal stack consisting of a barrier metal 146, a work function metal 148, and a gate electrode metal 150 can be formed using polysilicon. The gate can be electrically connected to the outside of the device through a multilayer stack of metal tracks isolated from each other, the layers being separated by an interlayer dielectric (ILD). Figure 1B A lowermost ILD ILDO 162 and a first ILD ILDI 164 are shown, but one skilled in the art will recognize that in a typical device there may be five to fifteen such metal layers in the stack.

[0041] Although Figure 1AThe cross section in shows the location of the gate, further into the page and therefore not shown, but the drain similarly crosses and surrounds the fin, and is in contact with the fin. The drain (which may also be referred to as a drain finger) is directly electrically connected to the fin, and is therefore not separated by the dielectric 140. In addition, and also not shown, the device includes a source, which also crosses and surrounds the fin, and is in contact with the fin. The source (which may also be referred to as a source finger) is also in direct electrical contact with the fin, and is therefore not separated by the dielectric 140. A typical device has multiple source and drain regions or fingers, and these source and drain regions or fingers are arranged to be separated by multiple gates, in a spacing sequence of (extending into the page, extending outside the page) drain-gate-source-gate-drain-gate... (and so on). As those skilled in the art will be familiar with, electrical connections are provided to the source and drain, and the channel between the source and the drain is formed by the fin. The electrical "gate length" parameter is therefore defined by the width of the physical gate contact (into the page), and the electrical "gate width" parameter is defined by the height of the fin and (twice) its width. Since a larger gate width can thereby be achieved, such FinFETs can be used as high power devices.

[0042] Figure 1A A conventional body contact is also shown in the figure: As shown, the device includes a plurality of partial fins 151. These partial fins correspond to partially etched fins, so that their top surfaces are roughly coplanar with the surface of the field oxide 130. The partial fins 151 are spaced apart from the plurality of fins 120 and separated from the plurality of fins by one or more columns 160. Each column 160 corresponds to a fin that has been completely or substantially etched to its bottom. The gaps between the partial fins are filled with field oxide 130. The fins are located in the N-well and typically have the same doping level as the rest of the N-well. However, partial fins are provided to be electrically connected to the n-well itself (commonly referred to as body contacts). In order to reduce the resistivity of the electrical contact, another n-type dopant is injected into the upper portion of the partial fin (as will be discussed in more detail below), and then the upper portion is annealed to increase its conductivity. The n+ upper surface of the resulting partial fin is electrically connected to the contact metal 170. The contact metal is connected to the outside world through a metal stack. A metal track ("DT") 172 is shown passing through the first level interlayer dielectric (ILD1).

[0043] As already discussed in the introduction, self-heating is a problem with high-power FinFETs, and the problem is exacerbated as miniaturization continues. The challenge grows with smaller manufacturing "nodes" such as 16nm, 14nm, 12nm, 10nm, 7nm, 6nm, 5nm, 4nm, and 3nm.

[0044] Go to Figure 2A , showing that Figure 1A Typical thermal path of a FinFET shown. The metal layer provides high thermal conductivity and therefore efficiently draws heat away from the active portion of the device. However, the effectiveness of heat dissipation from the substrate is limited by the device structure. Specifically, the source, drain or body contact (metal or polysilicon) extends downward to the field oxide, which, in addition to being an electrical insulator, is also a good thermal insulator. Very little heat can be conducted away through the interface 210. Therefore, as shown by arrow 220, the heat is directed to the top 230 of the portion of the fin and is collected by the portion of the fin.

[0045] According to an embodiment of the present disclosure, a FinFET structure and a method for manufacturing the same are provided, which can overcome or alleviate the conduction or collection of heat and thus improve the cooling of the device.

[0046] Figure 1B A schematic cross-section orthogonal to the direction of the fins through a portion of a FinFET 101 is shown in accordance with one or more embodiments of the present disclosure. The structures of the portions of the device associated with the fins and gate are the same or similar to those described above, and therefore will not be described in detail. However, the body contact area of ​​the device is different. The body contact 170 includes a groove 174 extending between the partial fins 151 and into the substrate. Although grooves can be provided between adjacent partial fins, the spacing between the partial fins is typically relatively close, approximately 10nm to 20nm at the base of the partial fins. The volume of metal included in the groove can be increased by removing (typically by etching, as will be discussed in more detail below) one or more fins between the partial fins to leave only the pillars 162. With Figure 1A Compared to the conventional device shown in FIG. 1 , the body contact extends further into the silicon substrate. Figure 1A Compared to the conventional device shown, the metal track 176 in ILD1 that forms part of the electrical connection between the body contact and the outside world can be wider. In addition, the portion of the fins and the pillars that are in electrical contact with the metal body contact layer 174 can have an epitaxial layer 152, which can typically be silicon or SiC, at their outer surfaces, and can additionally include a metal silicide layer 154. As will be described in more detail below, the silicide of the portion of the fins and the pillars can occur during and simultaneously with existing process steps. In addition, the body contact metal can include a seed metal layer 178. The thickness of the seed metal can typically be between 2nm and 5nm.

[0047] Now go to Figure 2B , showing that Figure 1BTypical thermal path for a FinFET shown. Compared to the heat flow of conventional structures, it is apparent from arrow 225 that heat can flow from the metal body contact not only directly to the top end 230 of the portion of the finger, but also directly into the substrate area above a relatively large area of ​​the interface between the body contact and the silicon, which relatively large area covers not only the side surface 240 of the portion of the fin, but also one or more pillars 250 and the space therebetween. In addition, it will be appreciated by those skilled in the art that by using the body contact as a metal heat sink for the substrate, there is little or no increase in the device area or so-called "silicon footprint." Thus, improved thermal performance can be provided without the added cost associated with dedicated heat dissipation structures or additional gates or non-functional metals that have been proposed elsewhere, which add parasitic capacitance, which is generally undesirable and can be critical for high performance high frequency applications.

[0048] Now refer to Figures 3A to 3X A typical process flow of FinFET according to an embodiment of the present disclosure is described.

[0049] N-well and P-well implants.

[0050] In a first manufacturing stage, N-wells and P-wells are implanted into a silicon base layer. The silicon base layer may be a silicon substrate, or may include an epitaxial layer over an oxide layer for silicon-on-insulator (SOI) or buried oxide (BOX) devices. Figure 3A A cross section of the completed device is shown, with the p-well 302 visible.

[0051] Pad oxide growth

[0052] At the next manufacturing stage, an oxide layer 304, often referred to as a pad oxide, is grown across the surface of the device. The thickness of the oxide may be about 5 nm to 25 nm, and is typically approximately 10 nm.

[0053] Low stress nitride deposition.

[0054] In the next manufacturing stage, a nitride layer 306 is deposited on the pad oxide. The nitride can be pure silicon nitride or silicon oxynitride, and is often referred to as a low stress nitride. The thickness of the nitride layer is typically in the range between 200nm and 600nm, and can be approximately 400nm thick. Figure 3A A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these manufacturing steps.

[0055] Fin Lithography

[0056] The next manufacturing stage is fin formation. To provide relatively narrow fins, a range of different lithography-based processes can be used. One such process is "self-aligned double patterning," also known as SADP.

[0057] Fabrication of etching mask

[0058] The next stage of fabrication is to create an etch mask. The etch mask may be patterned using photoresist produced by fin lithography, or more typically may be a hard mask, such as that defined by SADP.

[0059] Fin silicon etching

[0060] The next manufacturing stage is to etch the unmasked areas of nitride, oxide, and silicon to form a plurality of silicon fins 310. The silicon fins are typically in the range of 5nm to 30nm in width, 30nm to 200nm in height, and extend along all or most of the device (not shown in the figure as this direction extends into the page). Figure 3B A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these manufacturing steps.

[0061] Stripping the Etch Mask

[0062] The next manufacturing stage is to strip the etch mask. In embodiments where the etch mask is a hard mask, this typically involves a wet etch that is selective to both nitride and silicon. In embodiments where the etch mask is a photoresist, the etch mask can be easily removed using an appropriate solvent.

[0063] “Fin removal” lithography

[0064] Next, another photolithography phase is performed in which some of the fins are unmasked.

[0065] Etch the silicon fins in the locations defined by the "fin removal" mask

[0066] Next, the exposed fins are removed, leaving gaps 312, 314 between the fin groups. However, as will be discussed in more detail below, this stage is common to both conventional process flows and process flows according to embodiments of the present invention, and the photolithography mask itself is different from the conventional mask. Specifically, while in the conventional process flow, the fin groups are removed to leave gaps 312 to isolate different transistors, in accordance with embodiments of the present invention, additional fins may be removed, as shown at 314, which will help to subsequently define metal trenches toward the silicon base layer, which, as described above, is typically an epitaxial layer above a substrate or oxide. The gap 314 may be formed by, for example, Figure 3C The single removed fin shown provides, or may include, the space left by removing multiple adjacent fins. Figure 3CA schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0067] It should be understood by those skilled in the art that, at least in theory, Figure 3D The structure shown can be produced using only one lithography platform, where the desired fins are protected and the fins that would normally pass through are removed during the first fin definition lithography. Figure 3C The fins are removed by the photolithography platform shown. However, it will be appreciated by those skilled in the art that, using currently available photolithography techniques, the size of the fins that can be achieved is larger than the size of the fins that can be achieved by state-of-the-art techniques such as self-aligned double patterning (SADP). Therefore, the process stage for making the fins is preferably separated from the photolithography stage for removing the unwanted fins.

[0068] Stripping off the "fin removal" mask

[0069] In the next stage of the process, the fins are peeled off to remove the mask.

[0070] Growing silicon oxide

[0071] In the next stage of the process, a silicon oxide layer is grown over the exposed base layer material, including any residual stamp after the fins are removed. This silicon oxide layer is typically shallow, but sufficient to remove any surface layers from the silicon that may have been damaged by the etching process. Typically, a layer between 5nm and 10nm thick is grown, which is sufficient for this purpose.

[0072] Deposition of oxide

[0073] In the next stage of the process, the photolithography mask is removed and an oxide is deposited. The oxide is often called a field oxide and can be deposited, for example, starting from a TEOS (tetraethylorthosilicate) precursor. Figure 3D A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0074] Chemical Mechanical Polishing of Oxides

[0075] In the next stage of the process, the wafer is polished in chemical-mechanical polishing (also known as "chemical mechanical polishing" (CMP)) to planarize the surface. A low stress nitride layer may be conveniently deployed as a "stop layer" to detect the endpoint of the CMP process. Figure 3E A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0076] Etch oxide to recess field oxide

[0077] In the next stage of the process, the field oxide is partially etched to recess it relative to the silicon fins so that the upper portion 318 of each silicon fin is exposed above the recessed field oxide. Anisotropic etching (usually dry etching) is suitable for this process. Since nitride 306 is still present on top of each silicon fin, an etchant with low selectivity between silicon oxide and silicon itself can be used for this process. Nitride 306 acts as an etch stop layer.

[0078] Removal of low stress nitrides

[0079] In the next stage of the process, the nitride is removed from over the top of the silicon fin. Figure 3F A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0080] Growth Thermal Oxide

[0081] In the next stage of the process, an oxide layer is grown above the exposed upper portion of the silicon fin. This oxide layer is usually grown as a thermal oxide to allow precise control of thickness. According to this process, this oxide will be used as the first gate dielectric layer (HV gate dielectric #1) in a high voltage transistor. The suitable thickness range of the oxide is between 4nm and 10nm, and the thickness of the layer can be between 5nm and 7nm in particular. As shown in the figure, the growth consumes part of the width of the thin fin, so that the exposed upper portion 318 (now encapsulated by the grown thermal oxide) is a few nanometers thinner than the lower portion 322 embedded in the field oxide 316. Figure 3G A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0082] Etching HV transistor gate dielectric #1

[0083] In the next stage of the process, the thermally grown oxide layer is removed by etching from areas of the device where it is not needed as a gate dielectric. This includes, for example, parts of the device that are intended to subsequently become low voltage transistors and therefore require a thinner gate oxide.

[0084] Pre-cleaning silicon surfaces

[0085] In the next stage of the process, the silicon surface exposed by the above-mentioned etching process is pre-cleaned.

[0086] Growth Thermal Oxide

[0087] In the next stage of the process, a thermal oxide is grown (321) which will serve as the first gate dielectric layer (LV gate dielectric #1) for the low voltage transistor. Controlling the thickness and uniformity of this oxide is important for proper performance of the transistor, and the oxide layer can be only a few atoms thick, with a thickness of arrive within the range of arrive within the range.

[0088] Deposition of high-K dielectric layer

[0089] In the next stage of the process, a dielectric layer having a high dielectric constant is deposited (324). In this case, the high dielectric constant corresponds to a higher dielectric constant relative to silicon dioxide. Although a range of values ​​may be considered to correspond to a high dielectric constant, in practice any dielectric constant value greater than 10 is suitable. The thickness of this layer is typically in the range of 1 nm to 10 nm, and specifically, its thickness may be between 2 nm and 7 nm. This layer may be referred to as "LV transistor gate dielectric #2".

[0090] Deposition of barrier metal

[0091] In the next stage of the process, a barrier metal 326 is deposited across the device. The barrier metal is typically a refractory metal such as tungsten (W), tantalum (Ta), or titanium (Ti). However, those skilled in the art will appreciate that other suitable metals or alloys may be used instead, and the embodiments are not limited to these specific metals.

[0092] Deposition of polysilicon

[0093] In the next stage of the process, a polysilicon layer 328 is deposited over the device. The polysilicon layer typically covers the entire device and has a thickness in the range between 50nm and 200nm, and specifically may be between 80nm and 120nm thick. As is familiar to those skilled in the art, the polysilicon may be referred to as a "(temporary) transistor gate" layer, since it will be replaced by a metal gate later.

[0094] Deposition of low stress nitride

[0095] In the next stage of the process, a nitride layer 330 is deposited over the device. The nitride layer may be referred to as a "low stress" nitride. Figure 3H A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0096] Making the Etch Mask

[0097] At the next stage of the process, an etch mask 332 is provided over the silicon fins (which will ultimately provide the channels for the transistors). This mask may conveniently be a soft mask, such as photoresist on the lithography platform itself.

[0098] Forming the transistor gate

[0099] In the next stage of the process, the nitride 330 and polysilicon layer 328 are etched to form the transistor gate. Fig. 3I A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0100] Removal of gate etch mask

[0101] In the next stage of the process, the etch mask is removed.

[0102] Deposition of oxide / nitride stack

[0103] In the next stage of the process, a relatively thin stack of oxide layer 334 and nitride layer 336 is deposited. Each layer can typically be a few nanometers thick. These layers will then be removed from over most of the device to serve as spacer layers.

[0104] Etching oxide / nitride stack to form spacers

[0105] In the next stage of the process, the oxide and nitride stacks are etched from the bulk of the device. Specifically, an anisotropic etch (usually in a dry etch process) is used to remove these layers from the exposed horizontal surfaces of the device and leave these layers only on the sidewalls of the transistor gate stack including polysilicon 328 and nitride 330. Figure 3J A schematic cross section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process. Figure 3J Only a single oxide layer and a single nitride layer are shown in FIG. 1 , but in other embodiments, multiple layers of oxides and nitrides may be included.

[0106] N-type and P-type extension implants

[0107] In the next stage of the process, a photolithography platform is used to provide a patterned mask over the device, through which n-type dopant atoms are implanted to provide n-type extension regions. These extension regions are part of the geometric layout of the device and help to form appropriate electrical connections between the transistor channel region and the source-drain region. Similarly, another photolithography platform is used to provide another patterned mask over the device, through which p-type dopant atoms are implanted to provide p-type extension regions.

[0108] N-type and P-type source-drain implants (masked)

[0109] In the next stage of the process, a photolithography platform is used to provide a patterned mask over the device through which n-type dopant atoms are implanted to provide n+ type source 338 and drain (not shown) regions. Similarly, another photolithography platform is used to provide another patterned mask over the device through which p-type dopant atoms are implanted to provide p+ type source and drain regions.

[0110] Deposition of oxide / nitride stack

[0111] In the next stage of the process, another stack of oxide layer 340 and nitride layer 342 is deposited over the device. Figure 3K A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0112] Patterned P-type source-drain epitaxial silicon growth mask

[0113] In the next stage of the process, another etch mask 344 is provided over the silicon fins and source-drain epitaxial growth areas. It should be noted that the mask exposes the areas that will eventually contain the metal heat sink trenches, which are particularly relevant to the present disclosure. This mask can be suitably a soft mask, such as a photoresist of the lithography platform itself. Figure 3L A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0114] Etching the silicon fins in the P-type epitaxial silicon growth openings

[0115] In the next stage of the process, a portion of the exposed silicon fin in the opening in the P-type epitaxial silicon growth mask is removed by etching. This process stage includes etching the high-k (high dielectric constant) dielectric layer 324 and the oxide layer 320 protecting the fin 338. The silicon etch for removing a portion of the exposed silicon fin needs to have high selectivity to the field oxide 130. Figure 3M A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of a “conventional” manufacturing process.

[0116] Etching oxide in P-type epitaxial silicon growth openings

[0117] A step not present in conventional processes but included in the present disclosure is etching the field oxide 130 to expose the silicon fin sidewalls and substrate silicon, and in the next stage of the process according to the present disclosure, removing the field oxide between and around the pillars remaining from the removed silicon fins 346 by etching. Figure 3NA schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0118] Removal of etching mask

[0119] In the next stage of the process, etch mask 344 is removed.

[0120] P-type doped SiGe epitaxial growth on exposed silicon surface

[0121] In the next stage of the process, P-type doped SiGe is epitaxially grown onto the exposed silicon surface. It should be understood that this process step also exists in conventional processes. Epitaxial SiGe grows on the exposed silicon surface. This epitaxial material fills the gap between the pillars 346 and the unetched oxide 316. In other embodiments, silicon can be grown instead of SiGe.

[0122] Removal of P-type source-drain epitaxial silicon growth mask

[0123] In the next stage of the process, portions of the oxide layer 340 and the nitride layer 342 patterned using the mask 344 are removed.

[0124] N-type source-drain epitaxial silicon growth steps

[0125] In the next stage of the process, steps 31 to 37 are repeated, but this time for N-type epitaxial silicon growth. During the N-type version of process steps 31 to 37, the P-type fins with P-type SiGe grown on the top and sides of the partially etched silicon fins 346 and exposed areas of the substrate silicon will be protected by the oxide 340 and nitride 342 hard masks, which will expose only the N-type silicon fins that require substrate trench contacts. Therefore, during the N-type version of process steps 31 to 37, N-doped epitaxial silicon will only grow on the N-type partially etched silicon fins 346 and exposed areas of the substrate silicon. Fig.3O A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after those steps of the manufacturing process related to a P-type silicon fin.

[0126] Dopant activation annealing

[0127] In the next stage of the process, the device is thermally treated using a conventional annealing process to activate the implanted dopants in the silicon material.

[0128] Deposition of metal thin films

[0129] In the next stage of the process, a thin film of metal (usually on the order of tens of nanometers) is deposited over the entire device. As should be understood from the next step, this metal will form the source and drain silicides, and typically includes one of titanium and cobalt.

[0130] A first anneal is performed to form metal silicide on the exposed source-drain regions.

[0131] In the next stage of the process, a heat treatment or anneal is applied to the device at a temperature sufficient to react the metal with the exposed epitaxial silicon or SiGe or SiC 348 grown on the exposed pillars 346 to form a metal silicide 350. The time and temperature of this heat treatment should generally be sufficient to fully or at least mostly silicide the deposited metal film.

[0132] Removal of unreacted metals

[0133] In the next stage of the process, any unreacted metal (eg, metal on exposed oxide or exposed nitride portions of the device) is removed, typically by etching.

[0134] Second annealing to change the silicide into a stable phase

[0135] In the next stage of the process, another heat treatment or anneal is applied to the device at a certain temperature and time to change the metal silicide 350 from the first phase or mixed phase to a second phase that is more stable and has lower film resistivity, which in turn causes lower contact resistance between the metal and the silicide. Figure 3P A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0136] Deposition of (initial) interlayer dielectric

[0137] In the next stage of the process, an initial interlayer dielectric 352 is deposited across the device, which may also be referred to as an interlayer dielectric “ILDO.” ILD0 is typically formed of an oxide.

[0138] Polishing oxide.

[0139] In the next stage of the process, the device is polished by a chemical mechanical polishing (CMP) step to planarize the oxide. As will be familiar to those skilled in the art, the exposed nitride can be suitably used as an etch stop layer for a chemical-mechanical etching process. Figure 3Q A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0140] Polishing oxide and polysilicon

[0141] In the next stage of the process, another polishing, usually by chemical-mechanical polishing (CMP), is performed to planarize the device. This process removes all nitride and a limited portion of the polysilicon of the transistor gate. Figure 3RA schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0142] Removing gate polysilicon

[0143] In the next stage of the process, the polysilicon in the transistor gates is removed.

[0144] Deposition of N-type transistor work function (WF) metal

[0145] In the next stage of the process, metal 354 is deposited across the device. This metal is the work function metal for the N-type transistor. This metal defines the threshold voltage (Vt) of the N-type transistor of the device.

[0146] Metal removal

[0147] In the next stage of the process, a photolithographically defined mask is formed to protect the N-type transistor region. The deposited metal is removed from other areas of the device, specifically the P-type transistor region.

[0148] Deposition of P-type transistor work function (WF) metal

[0149] In the next stage of the process, another metal is deposited across the device. This metal is the work function metal for the P-type transistor. This metal defines the threshold voltage (Vt) of the device's P-type transistor.

[0150] Metal removal

[0151] In the next stage of the process, a photolithographically defined mask is formed to protect the P-type transistor region. The deposited metal is removed from other areas of the device, specifically the N-type transistor region. Figure 3S A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0152] Deposition of gate metal

[0153] In the next stage of the process, gate electrode metal 356 is deposited across the device.

[0154] Polishing gate metal

[0155] In the next stage of the process, the device is polished, typically by CMP, to remove the gate electrode metal 356 from unwanted areas. Interlayer dielectric 0 (ILD0) may be suitably used as a polish stop for this process. Figure 3TA schematic cross section through a FinFET device according to an embodiment of the present disclosure is shown after these steps in the manufacturing process. The device shown is an N-type transistor gate with a P-type substrate contact, and it should be understood that P-type transistor gates with N-type substrate contacts are also manufactured at other locations on the wafer or circuit.

[0156] Deposition of interlayer dielectric “1” (ILD1)

[0157] In the next stage of the process, the next interlayer dielectric (ILD1) 358 is deposited across the entire device.

[0158] Polishing oxide to planarize the wafer surface

[0159] In the next stage of the process, the oxide of ILD1 is polished, typically by CMP, to planarize the wafer surface. Figure 3U A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0160] Etching of gate connection trench contacts (GT)

[0161] In the next stage of the process, a mask 358 is defined across the device, and the ILD1 layer 358 is etched through the mask to provide a gate connection trench (GT). Compared to conventional processes, for the embodiments of the present disclosure, the ILD1 layer 358 is etched at a location away from the gate above the SiGe covered by the metal silicide 350. It should be understood that the ILD0 layer 352 may be etched slightly to ensure complete removal of the ILD1 layer 358 in the gate connection trench. Figure 3V A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0162] Removal of gate connection trench etch mask

[0163] In the next stage of the process, the etch mask used to define the gate connection trench is removed.

[0164] Etching of source-drain connection trench contacts (DT)

[0165] In the next stage of the process, another mask (360) is defined across the wafer to expose areas where epitaxial silicon or SiGe or SiC and subsequent metal silicide are formed on the top of the partially etched silicon fins, the sidewalls of the silicon fins, and the substrate silicon surface. These areas may also be referred to as diffusion contact trenches (DT). Compared to conventional processes, according to the process flow of one or more embodiments of the present disclosure, this mask also exposes the areas above and between the pillars 346 and the overlying SiGe 348 and metal silicide 350. It should be noted that the exposed area at the beginning of the device is narrower than the area exposed for etching the ILD1 layer 358. Layer ILD0 352 is removed from the diffusion contact. During this etching of the ILD 0 layer 352, the ILD 0 layer 352 is also removed from the metal silicide 350 and SiGe 348, above and between the pillars 346. It should be appreciated that since in conventional processes, gate trench etching and diffusion contact trench etching include a certain amount of overetching to ensure complete removal of oxide in the ILD0 oxide, trench-to-substrate according to the present disclosure can be achieved with substantially no or little adjustment to conventional etching steps. Figure 3W A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0166] Now go to Fig.9A , showing that in Figure 3W Schematic cross section through a conventional FinFET device at corresponding stages and after corresponding steps of the manufacturing process. The device is generally similar to Figure 3W However, in the conventional partially processed device shown, the epitaxial SiGe 348 grown on the exposed pillars 346 is coalesced into a single continuous region.

[0167] In addition, Figure 3V During the gate connection trench etching step 37 ("GT") shown, the source-drain trench (DT) region has not been previously etched. Figure 3W The subsequent photolithography mask 960 corresponding to the mask 360 in does not include the stepped region around DT because the ILD1 layer 358 has not been previously etched in this region. In other words, the etching step after the deposition of the mask 360 etches the ILD1 358 in this region for the first time.

[0168] Now return to the process description of the method according to the embodiment of the present disclosure.

[0169] Removal of "DT" etch mask

[0170] In the next stage of the process, the source-drain trench (DT) etch mask is removed.

[0171] Depositing the “seed” metal layer

[0172] In the next stage of the process, a seed metal layer 362 is deposited across the device. The seed metal layer may be formed, for example, of ruthenium, tantalum or titanium and their nitrides. The seed metal layer will suitably be a thin layer, for example in the range of 3nm to 20nm in thickness.

[0173] Depositing trench contact metal

[0174] In the next stage of the process, trench metal contacts 364 are deposited across the device, which can be typically formed of copper, tungsten, or cobalt. Those skilled in the art will appreciate that in conventional devices, trench metal contacts need to fill all exposed trenches, which are typically only as deep as the depth of ILD1 358. However, according to embodiments of the present disclosure, trench metal fills not only the trenches in ILD1 layer 360, but also the trenches in ILD0 layer 352 and the spaces between pillars 346. Therefore, the thickness of the deposited trench metal can be significantly greater than that of conventional devices.

[0175] Polished Metal

[0176] In the next stage of the process, trench metal 364 is polished, typically by using a CMP process. ILD1 layer 358 may suitably serve as a polish stop layer. Figure 3X A schematic cross-section through a FinFET device according to an embodiment of the present disclosure is shown after these steps of the manufacturing process.

[0177] Additional process steps

[0178] As will be familiar to those skilled in the art, further processing steps of the device follow conventional processing for subsequent ILD and metal layers.

[0179] Now go to Fig. 9B , showing the embodiment of the present disclosure in Figure 3X Schematic cross section through a conventional FinFET device at the same stage of fabrication. Fig. 9B and Figure 3X By comparison, it is obvious that in conventional devices, Fig. 9B The trench metal, depicted as 964 in the figure, does not go deeper into the device than ILD0 352. The trench metal contacts the epitaxial SiGe through the silicide surface region 350, but this is much shallower in the device than in the disclosed embodiments. In addition, in the conventional device shown, a field oxide 316, which acts as a thermal insulator as well as an electrical insulator, is located between the trench metal 964 and the substrate. The primary thermal conduction path from the trench metal 964 to the substrate is through the epitaxial SiGe 348, which has been silicided, and from there through the portions of the fins (322) separated by the field oxide regions 316.

[0180] Fig. 10A shows a schematic cross section through a FinFET device according to one or more other embodiments of the present disclosure, and Fig. 10B Schematic cross-sections through a conventional FinFET are shown. These figures show Figure 3W and Fig.9A The corresponding stages and the manufacturing after the corresponding steps of the manufacturing process.

[0181] Fig. 10A and Figure 3W The main difference between Fig. 10A A portion of the processing device in N well 1002 is depicted, and Figure 3W A portion of the processing device in the P-well 302 is depicted. Fig. 10A (Embodiments of the present disclosure) and Fig. 10B (depicting the corresponding conventional device), the fin is therefore N-type. The upper portion 1018 of the portion of the fin is implanted as heavy N-type. In addition, the device in the N well ( Fig. 10A The embodiments of the present disclosure shown and Fig. 10B The conventional device shown in Figure 100 has epitaxial silicon (rather than Si-Ge) grown onto the exposed top ends of the upper portions 1018 of the portions of the fins. It will be observed that the epitaxial silicon does not form such a pronounced "angled" shape at the top ends (that is, the preferential growth of n-type silicon 1048 along certain crystal surfaces is less pronounced than that of p-type SiGe 348).

[0182] As just mentioned, Fig. 10B A conventional device in an N-well is shown. Again, in this conventional partially processed device shown, the epitaxial Si 1048 grown on the exposed pillars 346 is coalesced into a single continuous region. And the subsequently deposited trench metal is separated from the portion of the fin 1018. The portion of the fin is separated by the field oxide 316, which, as stated above, is a thermal insulator. Therefore, the primary heat conduction in the completed device is through the epitaxial silicon 1048 and the portion of the fin 1018, which provides a much lower thermal conduction path than provided by the embodiments of the present disclosure, in which the field oxide in this area is replaced by additional trench metal.

[0183] Now go to Figure 4 , shows a schematic diagram of a portion of a partially fabricated FinFET 400. The FinFET 400 includes a plurality of elongated fins 410 as described above. As shown, the elongated fins intersect with a plurality of staggered source fingers S 420 and drain fingers D 430. Figure 4The feature of FIG. 4 is that source fingers 420 and drain fingers 430 are shown, which correspond to the metal in typical layers M1 and M2 of the metal layer stack. However, between each source and drain finger there is a gate finger (not shown) which also crosses the fin, as shown in FIG. Figures 5 to 8 As will be more apparent, the gate fingers are visible at the surface of the device, but not at the M0 or M2 metal layers, and therefore are not visible at the M0 or M2 metal layers. Figure 4 Not shown.

[0184] Figure 5 The conventional FinFET is shown Figure 4 The cross section of B-B'. Figure 6 FIG. 1 shows a FinFET according to one or more embodiments of the present disclosure. Figure 4 The cross section of B-B'.

[0185] These figures show metal regions 510 of metal layer M2, metal regions 520 of metal layer M1, and metal regions 530 of metal layer M0. The metal regions of each layer are separated and isolated from each other by dielectrics, and the layers are separated by interlayer dielectrics ILD. Metal regions 530 are connected to staggered or alternating source and drain regions. In addition, at the same level of the device as M0, a gate 540 is shown that is staggered between alternating source and drain fingers. In addition, in Figure 6 , a metal connection to the substrate 535 is shown on the outermost area. Figures 3A-3X As described in detail in , a heat sink metal connection to the substrate connects the body region to the substrate. The upper and lower surfaces of the field oxide are shown at 550 and 560, respectively.

[0186] The isotherms corresponding to the example set of operating conditions are indicated by the various shading in the figure. It can be clearly seen from the figure that the hottest part of the device is located around and near the gate. Figure 5 The isotherms shown are Figure 6 By comparing the isotherms in Figure 6 The isotherms in are slightly smaller, which corresponds to an embodiment of the present disclosure and indicates more efficient cooling, and Figure 6 The structures operate at cooler temperatures (usually down to between 10K and 20K).

[0187] Figure 7 The conventional FinFET is shown Figure 4 A-A' cross section. Figure 8 FIG. 1 shows a FinFET according to one or more embodiments of the present disclosure. Figure 4510, M1 520, and M0 530, vias 715 and 725 through the ILD are shown. A gate 770 is also shown, partially surrounding an upper portion of a fin 780. The fin extends through the field oxide between surfaces 550 and 560 (extent of extension not shown laterally) and protrudes thereon, such that the upper portion is partially surrounded by the gate 770. It should be understood that in this cross section, the heat sink metal connection to the substrate is not visible.

[0188] Comparing again the isotherms corresponding to the same operating conditions in each figure, it is clear that Figure 7 Compared with the conventional device shown in FIG. Figure 8 There are fewer isotherms in , and in this case, at least one isotherm is missing. This corresponds to Figure 7 Compared with the operating temperature of conventional devices, Figure 8 The device of the embodiments has a lower operating temperature.

[0189] Other variations and modifications will be apparent to those skilled in the art from reading this disclosure.Such variations and modifications may involve equivalent and other features that are known in the art of FinFET fabrication and may be used as a substitute or in addition to the features described herein.

[0190] Although the attached claims are directed to specific feature combinations, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel feature combination or any generalization of the novel features disclosed explicitly or implicitly herein, regardless of whether the novel feature relates to the same invention as the present invention currently claimed in any claim and whether the novel feature alleviates any or all of the same technical problems as the technical problems alleviated by the present invention.

[0191] It should be noted that one or more embodiments described above have been described with reference to different subject matters. In particular, some embodiments may have been described with reference to method-type claims, while other embodiments may have been described with reference to apparatus-type claims. However, a person skilled in the art will conclude from the above that, unless otherwise indicated, any combination of features relating to different subject matters, in addition to any combination of features belonging to one type of subject matter, in particular a combination of features of method-type claims and features of apparatus-type claims, is also considered to be disclosed by this document.

[0192] Features described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.

[0193] For the sake of completeness, it is also provided that the term "comprising" does not exclude other elements or steps, the term "one" or "an" does not exclude a plurality, a single processor or other unit may satisfy the functions of several components recited in the claims [deleted if irrelevant], and the figure marks in the claims should not be interpreted as limiting the scope of the claims. In addition, the word "may" is used in a permissive sense (i.e., meaning having the possibility of...) rather than a mandatory sense (i.e., meaning must). Similarly, the words "include", "including" and "includes" mean including but not limited to.

Claims

1. A FinFET semiconductor device, characterized in that: include: a substrate having a main region of a first conductivity type, a plurality of elongated fins at the first major surface of the substrate and within the body region; an oxide layer on the first major surface and partially surrounding a lower portion of the elongated fin; a gate contact extending across and partially surrounding an upper portion of the plurality of elongated fins; a dielectric material that provides electrical isolation between and between the fins and the gate region; a plurality of elongated partial fins parallel to the plurality of elongated fins and having a height less than the height of the plurality of elongated fins; as well as an elongated metal contact extending into the substrate and in electrical contact with the plurality of elongated partial fins and forming a body contact of the FinFET; The elongated metal contact extends between two elongated partial fins of the plurality of elongated partial fins and below upper surfaces of the two elongated partial fins, and fills a space between the two elongated partial fins.

2. The FinFET semiconductor device according to claim 1, characterized in that additionally including at least one elongated post between two of said elongated portion fins of said plurality of elongated portion fins; Wherein the elongated metal contact extends between the two elongated portion fins of the plurality of elongated portion fins to the at least one elongated post.

3. The FinFET semiconductor device according to claim 1, characterized in that Surfaces of the plurality of elongated portion fins and a surface of the at least one elongated pillar include metal silicide.

4. The FinFET semiconductor device according to claim 1, characterized in that The elongated metal contact includes a first seed metal in contact with the metal silicide and a second metal at other locations.

5. The FinFET semiconductor device according to claim 4, characterized in that The body region has a first conductivity type, Also included is an elongated drain region of a second conductivity type opposite to the first conductivity type extending across and electrically connected to the plurality of elongated fins.

6. The FinFET semiconductor device according to claim 5, characterized in that The elongated drain region is one of a plurality of such drain regions, a plurality of the elongated drain regions having a plurality of such drain regions, and the gate contact is one of a plurality of such gate contacts, arranged as a sequence of separated regions in a drain-gate-source-gate-drain-gate-source configuration.

7. The FinFET semiconductor device according to claim 1, wherein: The main body region has a first conductivity type, Also included is an elongated source region of a second conductivity type opposite to the first conductivity type extending across and electrically connected to the plurality of elongated fins.

8. The FinFET semiconductor device according to claim 1, characterized in that Also included is a stack of metal connection layers with interlayer dielectric layers therebetween, wherein the elongated metal contact extends upwardly through the lowermost two of the interlayer dielectric layers.

9. The FinFET semiconductor device according to claim 1, characterized in that The body contact of the FinFET is electrically connected to a source of the FinFET, and the elongated metal contact forms a source contact of the FinFET.

10. A method for manufacturing a FinFET device, characterized in that: The method comprises: providing a substrate having a body region of a first conductivity type therein and a plurality of elongated fins at a first major surface of the substrate and within the body region; providing an oxide layer on the first major surface and partially surrounding a lower portion of the elongated fin; providing a gate contact extending across and partially surrounding the plurality of elongated fins; providing a dielectric material that provides electrical isolation between and between the fin and the gate region; etching a subset of the elongated fins to form a plurality of elongated partial fins having a height less than the height of the plurality of elongated fins and having an upper surface at the same height as an upper surface of the oxide layer; removing an oxide layer between two elongated portion fins of the plurality of elongated portion fins; and Depositing an elongated metal contact extending into the substrate and electrically contacting the plurality of elongated partial fins to form a body contact of the FinFET, wherein the elongated metal contact extends between two of the plurality of elongated partial fins and below the upper surfaces of the two elongated partial fins and fills the space between the two elongated partial fins.

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