Anti-surge low-barrier silicon carbide MOSFET structure and preparation method thereof
By introducing the Nbase region and gate/source polycrystalline plug finger distribution structure in the silicon carbide MOSFET, the on-voltage drop and energy loss problems of traditional devices during reverse free-flow are solved, and the device's surge resistance and service life are significantly improved.
Patent Information
- Application Number
- CN202510145056.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-10
- Publication Date
- 2025-05-13
AI Technical Summary
The existing silicon carbide MOSFETs have problems such as high conduction voltage drop, increased energy loss, and bipolar degradation during reverse free flow, especially in surge situations that affect the device's operating power consumption and long-term reliability.
A low-barrier silicon carbide MOSFET structure is adopted to resistant surges. By providing different doping regions on the epitaxial layer, a JFET region, a P well region and a channel region that penetrates the transverse epitaxial layer, and a gate/source polycrystalline finger distribution structure is used to replace some traditional P-type channels with an Nbase region to achieve the reverse monopole conduction effect.
It significantly improves the current conduction ability of the device, reduces the conduction loss, improves the surge resistance of the device under surge conditions, extends the service life and reduces the operating cost of the system.
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Figure CN119997560A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a surge-resistant low-barrier silicon carbide MOSFET structure and a preparation method thereof. Background Art
[0002] Silicon carbide MOSFET (metal-oxide-semiconductor field-effect transistor), as an important semiconductor power device, plays a key role in the field of modern power electronics.
[0003] Silicon carbide MOSFET works based on the field effect principle. In its structure, the drain and source are separated by an insulating oxide layer. When a suitable voltage is applied to the gate, a conductive channel is formed in the channel region, thereby controlling the current conduction between the source and drain. Its main function is to achieve efficient conversion and control of electric energy, and it is widely used in many fields such as power systems, electric vehicles, and industrial automation. Compared with traditional devices, silicon carbide MOSFET has many significant advantages. Since silicon carbide materials themselves have wide bandgap, high breakdown electric field, high thermal conductivity and other characteristics, silicon carbide MOSFET can operate at higher temperatures, voltages and frequencies, greatly improving power density and conversion efficiency, while also reducing the size and weight of the device, making it possible to miniaturize and lightweight the system.
[0004] However, existing SiC MOSFETs expose a series of serious problems when using the body diode for reverse freewheeling. The high on-state voltage drop leads to a significant increase in energy loss during reverse conduction, which not only reduces the efficiency of the entire circuit, but also generates excessive heat, affecting the stability of the device. High conduction losses further exacerbate energy waste and increase the operating cost of the system. Even more problematic is the bipolar degradation phenomenon, which gradually reduces the performance and reliability of the device and shortens its service life. Especially in surge conditions, the instantaneous high current and high voltage shocks can make these problems worse, greatly affecting the device's operating power consumption and long-term reliability.
[0005] In order to solve these problems, the existing technology attempts to solve various problems. For example, some studies reduce the on-resistance by optimizing the device structure, thereby alleviating the on-voltage drop and conduction loss problems to a certain extent; others use new material systems to improve the performance of the body diode. However, these methods often have limitations. For example, structural optimization may increase the complexity and cost of the manufacturing process, and the application of new materials may face challenges in compatibility and stability. At present, there is still a lack of an ideal solution that can effectively solve the reverse freewheeling problem of traditional silicon carbide MOSFETs while taking into account cost and process feasibility. Summary of the invention
[0006] In view of the problems existing in the prior art, the present invention provides a low-barrier silicon carbide MOSFET structure and a preparation method thereof which have a simple structure, low process cost and surge resistance.
[0007] To achieve the above purpose, the technical solution adopted by the present invention is as follows:
[0008] On the one hand, the present invention provides a surge-resistant low-barrier silicon carbide MOSFET structure, which mainly includes at least one MOSFET unit; the MOSFET unit is provided with a substrate and an epitaxial layer; different doping regions are provided on the epitaxial layer;
[0009] The epitaxial layer is provided with a JFET region that penetrates the lateral epitaxy;
[0010] P-well regions and channel regions are provided on both sides of the JFET region;
[0011] An N-type doping region is provided on the P-well region; the N-type doping region is provided with an Nbase region and an N+ region, the Nbase region is located at the front and rear sides of the channel region; the N+ region is located at a side of the Nbase region and the channel region away from the JFET region, and the N+ region is in contact with the Nbase region and the channel region;
[0012] A P+ region is also provided on the P well region;
[0013] A gate structure is also arranged on the epitaxial layer; gate polysilicon and source polysilicon are arranged in the gate structure; the gate polysilicon and the source polysilicon are separated by a gate oxide layer and present an interdigitated structure.
[0014] Optionally, the Nbase region is laterally aligned with the edge of the channel region on the side in contact with the N+ region.
[0015] Optionally, the gate polysilicon covers the channel region;
[0016] The source polysilicon covers at least a portion of the Nbase region.
[0017] Optionally, a thickened oxide layer is further provided on the gate structure.
[0018] Optionally, a metal contact window is provided on the thickened oxide layer;
[0019] A source metal layer is provided on the front side of the thickened oxide layer;
[0020] A drain metal layer is disposed on the back side of the substrate.
[0021] Optionally, the P+ region is located on a side of the N+ region away from the channel region and the Nbase region.
[0022] On the other hand, the present invention also provides a method for preparing a surge-resistant low-barrier silicon carbide MOSFET, which mainly comprises the following steps:
[0023] preparing a substrate and growing an epitaxial layer on the substrate;
[0024] Implanting N ions on the epitaxial layer through a first photomask to form a JFET region;
[0025] Implanting Al ions on the epitaxial layer through a second photomask to form a P-well region and a channel region;
[0026] N ions are injected into the upper layer of the P-well region through the third photomask to form an N-type doped region; Al ions are injected into the upper layer of the P-well region through the fifth photomask to form a P-type doped region.
[0027] Optionally, the doping concentration range of the JFET region formed by implanting N ions into the epitaxial layer through the first photomask is 1e 16 -2e 17 .
[0028] Optionally, the following steps are also included:
[0029] The N-type doping region includes an Nbase region and an N+ region; N ions are injected into the upper layer of the P-well region through a third photomask to form the Nbase region, and N ions are injected into the upper layer of the P-well region through a fourth photomask to form the N+ region;
[0030] A gate oxide layer is generated on the epitaxial layer by a thermal growth process, and gate polysilicon and source polysilicon are etched out by a sixth photolithography plate;
[0031] Generating a thickened oxide layer on the gate oxide layer, and etching a metal contact window through a seventh photolithography plate;
[0032] The source metal layer and the drain metal layer are processed by a sputtering process.
[0033] Optionally, the gate oxide layer has a growth thickness ranging from 30 nm to 80 nm.
[0034] Compared with the prior art, the present invention has the following beneficial effects:
[0035] The present invention has a simple structure and low process cost. By changing part of the traditional P-type channel into the Nbase region, the reverse unipolar conduction effect is achieved. At the same time, compared with the traditional low-barrier diode, the gate / source polycrystalline finger distribution structure is utilized to significantly improve the current conduction capability of the device and reduce the conduction loss, so that the device has better current distribution under surge conditions, thereby improving the surge resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0037] Figure 1 A three-dimensional diagram of a device in a specific embodiment of the present invention;
[0038] Figure 2 It is a three-dimensional diagram of a device in a specific embodiment of the present invention (excluding the top structure);
[0039] Figure 3 A top view of a device in a specific embodiment of the present invention (excluding the top structure);
[0040] Figure 4 It is a schematic diagram of the top structure of the device in a specific embodiment of the present invention;
[0041] Figure 5 It is a top view of the top structure of the device in a specific embodiment of the present invention.
[0042] In the figure: 1. substrate, 2. drift region, 3. P-well region, 4. P+ region, 5. N+ region, 6. Nbase region, 7. channel region, 8. JFET region, 9. drain metal layer, 21. gate structure, 210. source polysilicon, 211. gate oxide layer, 212. gate polysilicon, 22. thickened oxide layer. DETAILED DESCRIPTION
[0043] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0044] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0045] In the description of the present invention, “plurality” means two or more than two, unless otherwise clearly and specifically defined.
[0046] It is worth noting that the methods used in the present invention are all conventional methods unless otherwise specified; the raw materials and devices used are all conventional commercially available products, and their sources are not specifically limited unless otherwise specified.
[0047] It should also be noted that in order to facilitate understanding in the specific embodiments of the present invention, the method steps are described in a certain order, but those skilled in the art can change the order of the steps according to actual needs, and therefore this cannot be used as a limiting condition.
[0048] This embodiment provides a surge-resistant low-barrier silicon carbide MOSFET structure, such as Figure 1 As shown, it mainly includes at least one MOSFET unit. In this embodiment, for the convenience of description, a MOSFET unit is taken as an example, which is provided with a substrate 1 and an epitaxial layer. Figure 2 and Figure 3 As shown, different doping regions are provided on the epitaxial layer on the substrate 1, and at least part of the region layer is doped to form a drift region 2, which is used to withstand the high voltage of the device in the blocking state to ensure the voltage resistance performance of the device.
[0049] The upper layer of the epitaxial layer is provided with a JFET region 8 that penetrates the lateral epitaxy. P well regions 3 and channel regions 7 are provided on both sides of the JFET region 8.
[0050] An N-type doped region is provided on the P-well region 3, and the N-type doped region of the present embodiment includes an Nbase region 6 and an N+ region 5. Among them, on either side of the JFET region 8, the Nbase region 6 is divided into two blocks, which are located on the front and rear sides of the channel region 7 and in contact with it; the Nbase region 6 is also in contact with the JFET region 8. The N+ region 5 is located on the side of the Nbase region 6 and the channel region 7 away from the JFET region 8, and is in contact with the Nbase region 6 and the channel region 7. Among them, the Nbase region 6 and the channel region 7 are laterally aligned at the edge of the side in contact with the N+ region 5, so that the N+ region 5 presents a relatively regular long strip shape when viewed from above. The Nbase region 6 is used to replace part of the traditional P-type channel to achieve the effect of reverse unipolar conduction.
[0051] A P+ region 4 is further provided on the P-well region 3 , and is optionally located at a side of the N+ region 5 away from the channel region and the Nbase region.
[0052] Combination Figure 1 , Figure 4 and Figure 5As shown, a gate structure 21 is also provided on the epitaxial layer. The gate structure 21 includes a gate oxide layer 211. A gate polysilicon 212 and a source polysilicon 210 are also provided. The gate polysilicon 212 is separated from the source polysilicon 210 by the gate oxide layer 211 and is in an interdigitated structure. Further, the interdigitated structure is a structure in which convex portions are alternately interlaced and joined in the top view direction; specifically, in the present embodiment, the source polysilicon 210 is in a U-shaped structure when viewed from above, the gate polysilicon 212 is in a T-shaped structure, and the convex portion of the gate polysilicon 212 is inserted into the empty area in the middle of the source polysilicon 210, and the two blocks are separated by the gate oxide layer and do not contact each other. Furthermore, in the present embodiment, the gate polysilicon 212 completely covers the channel region 7 on both sides of the JFET region 8, and the source polysilicon 210 covers at least part of the Nbase region 6. Compared with the traditional low-barrier diode, this design significantly improves the current conduction capability of the device and reduces the conduction loss by using the gate / source polycrystalline interdigital distribution structure and the highly doped JFET region. Under surge conditions, the interdigital distribution polysilicon of the device enables better current distribution of the device and improves the device's surge resistance.
[0053] Optionally, a thickened oxide layer 22 is further provided on the gate oxide layer. Specifically, a metal contact window is provided on the thickened oxide layer 22, and a source metal layer is provided on the front side of the thickened oxide layer 22, while a drain metal layer 9 is provided on the back side of the substrate 1.
[0054] Based on the above-mentioned surge-resistant low-barrier silicon carbide MOSFET structure, this embodiment also provides a corresponding preparation method, which mainly includes the following steps:
[0055] S1, preparing a substrate and growing an epitaxial layer on the substrate;
[0056] First, the raw materials are selected: high-purity silicon carbide single crystal materials are selected as the starting materials for crystal growth, and the methods can be conventional physical vapor transport (PVT) and the like; taking PVT as an example, in the PVT process, the silicon carbide raw materials are placed in a high-temperature zone, and under the action of the temperature gradient and airflow, the silicon carbide molecules will be deposited and grown on the seed crystals in the low-temperature zone. By controlling the growth temperature, pressure, gas flow and other parameters, for example, the growth temperature is generally above 2000°C, and the pressure is between several hundred and several thousand Pascals, which needs to be adjusted according to the specific growth equipment and process; then the grown crystals are cut and ground: the grown silicon carbide single crystal ingots need to be cut and cut into thin slices of a certain thickness. The surface of the substrate sheet after cutting is relatively rough, and it needs to be ground to obtain a flat and smooth surface to meet the requirements of subsequent epitaxial growth and other processes. Finally, the substrate is cleaned and inspected: After cutting and grinding, the substrate needs to be thoroughly cleaned to remove impurities and contaminants on the surface. Common cleaning methods include chemical cleaning and plasma cleaning. The quality of the substrate is then inspected using a variety of detection methods, such as X-ray diffraction (XRD) for detecting crystal structure and lattice constants, atomic force microscopy (AFM) for detecting surface roughness, and electrical testing for detecting electrical parameters such as resistivity of the substrate. Only substrates that meet quality standards can enter the subsequent device preparation process.
[0057] An epitaxial layer is grown on the substrate by methods such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) for use in subsequent processes. The thickness and doping concentration of the epitaxial layer can be changed according to the withstand voltage specifications.
[0058] S2. After the epitaxial layer is formed, N ions are implanted into the epitaxial layer through the first photomask to form a JFET region; wherein the doping concentration range of the formed JFET region is 1e 16 -2e 17 .
[0059] S3. Al ions with different energies are injected into the epitaxial layer through a second photomask to form a P-well region and a channel region. The doping concentration is determined according to actual needs.
[0060] S4. N ions are injected into the upper layer of the P-well region through the third photolithography plate to form an Nbase region, wherein the doping concentration is determined according to actual needs; and then N ions are injected into the upper layer of the P-well region through the fourth photolithography plate to form an N+ region with a high doping concentration, wherein the N+ doping concentration and morphology pattern are determined by specific parameter requirements.
[0061] S5. Al ions are injected into the upper layer of the P-well region through a fifth photomask to form a P+ region; wherein the morphology of the P+ region is determined by specific parameter requirements.
[0062] S6. Generate a gate oxide layer on the epitaxial layer by a thermal growth process, and control the growth thickness of the gate oxide layer to be in the range of 30 nm to 80 nm.
[0063] S7, performing an in-situ polysilicon deposition process on the gate oxide layer, and then etching out the gate polysilicon and the source polysilicon through the sixth photolithography board; wherein the two polysilicons do not touch each other, and the gate polysilicon completely covers the channel area, the source polysilicon partially covers the Nbase area, the gate / source polysilicon do not touch each other, and the oxide layer is filled in between.
[0064] S8. Generate a thickened oxide layer on the gate oxide layer, and etch a metal contact window through a seventh photolithography board.
[0065] S9. Form a source metal layer and a drain metal layer on the front side and the back side respectively by sputtering process.
[0066] Working principle:
[0067] Traditional MOSFET faces the problem of large body diode loss. Although a low-barrier device structure is proposed, in its structure, the source polysilicon covers most of the JFET area, causing the on-resistance of the device to degrade by more than one time. Therefore, compared with the new structure of the traditional low-barrier device structure, the silicon carbide MOSFET provided in this embodiment utilizes the alternatingly distributed channel region / Nbase region and the interdigitated polysilicon structure to effectively improve the power density of the device while retaining the excellent reverse characteristics of the device, so that the device has a better quality factor. Specifically, the Nbase region structure is adopted, so that the device has a smaller on-state voltage drop than the body diode when working in reverse, and at the same time avoids the quality problems caused by the gate oxide layer being too thin. In addition, the low-barrier Nbase region structure allows the device to pass current through the Nbase region and the body diode at the same time under surge conditions. The impact of high temperature and high current on the reliability of the gate oxide layer of the present invention is much smaller than that of the traditional embedded channel diode structure (the structure of replacing Nbase with Pbase requires a significant reduction in the thickness of the upper oxide layer). Compared with the device with integrated Schottky diode, the leakage degradation of Schottky contact at high temperature is avoided. Therefore, the dual-channel + high gate oxide layer reliability characteristics of this structure make it more surge-resistant.
[0068] Finally, it should be noted that the above content is only used to illustrate the technical solution of the present invention, rather than to limit the scope of protection of the present invention. Simple modifications or equivalent substitutions of the technical solution of the present invention by ordinary technicians in this field do not deviate from the essence and scope of the technical solution of the present invention.
Claims
1. A surge-resistant low-barrier silicon carbide MOSFET structure, characterized in that: The invention comprises at least one MOSFET unit; the MOSFET unit is provided with a substrate and an epitaxial layer; and different doping regions are provided on the epitaxial layer; The epitaxial layer is provided with a JFET region that penetrates the lateral epitaxy; P-well regions and channel regions are provided on both sides of the JFET region; An N-type doping region is provided on the P-well region; the N-type doping region is provided with an Nbase region and an N+ region, the Nbase region is located at the front and rear sides of the channel region; the N+ region is located at a side of the Nbase region and the channel region away from the JFET region, and the N+ region is in contact with the Nbase region and the channel region; A P+ region is also provided on the P well region; A gate structure is also arranged on the epitaxial layer; gate polysilicon and source polysilicon are arranged in the gate structure; the gate polysilicon and the source polysilicon are separated by a gate oxide layer and present an interdigitated structure.
2. The surge-resistant low-barrier silicon carbide MOSFET structure according to claim 1, characterized in that: The Nbase region is laterally aligned with an edge of the channel region on a side in contact with the N+ region.
3. The surge-resistant low-barrier silicon carbide MOSFET structure according to claim 2, characterized in that: The gate polysilicon covers the channel region; The source polysilicon covers at least a portion of the Nbase region.
4. The surge-resistant low-barrier silicon carbide MOSFET structure according to any one of claims 1 to 3, characterized in that: A thickened oxide layer is also provided on the gate structure.
5. The surge-resistant low-barrier silicon carbide MOSFET structure according to claim 4, characterized in that: A metal contact window is provided on the thickened oxide layer; A source metal layer is provided on the front side of the thickened oxide layer; A drain metal layer is disposed on the back side of the substrate.
6. The surge-resistant low-barrier silicon carbide MOSFET structure according to claim 1, characterized in that: The P+ region is located at a side of the N+ region away from the channel region and the Nbase region.
7. A method for preparing a surge-resistant low-barrier silicon carbide MOSFET, characterized in that: The steps include: preparing a substrate and growing an epitaxial layer on the substrate; Implanting N ions on the epitaxial layer through a first photomask to form a JFET region; Implanting Al ions on the epitaxial layer through a second photomask to form a P-well region and a channel region; Injecting N ions into the upper layer of the P-well region through a third photomask to form an N-type doped region; Al ions are implanted into the upper layer of the P-well region through a fifth photomask to form a P-type doped region.
8. The method for preparing a surge-resistant low-barrier silicon carbide MOSFET according to claim 7, characterized in that: The doping concentration range of the JFET region formed by implanting N ions into the epitaxial layer through the first photomask is 1e 16 -2e 17 .
9. The method for preparing a surge-resistant low-barrier silicon carbide MOSFET according to claim 7 or 8, characterized in that: The following steps are also included: The N-type doping region includes an Nbase region and an N+ region; N ions are injected into the upper layer of the P-well region through a third photomask to form the Nbase region, and N ions are injected into the upper layer of the P-well region through a fourth photomask to form the N+ region; A gate oxide layer is generated on the epitaxial layer by a thermal growth process, and gate polysilicon and source polysilicon are etched out by a sixth photolithography plate; Generating a thickened oxide layer on the gate oxide layer, and etching a metal contact window through a seventh photolithography plate; The source metal layer and the drain metal layer are processed by a sputtering process.
10. The method for preparing a surge-resistant low-barrier silicon carbide MOSFET according to claim 9, characterized in that: The gate oxide layer has a growth thickness ranging from 30 nm to 80 nm.