Novel groove type silicon carbide device structure and manufacturing method thereof
By implanting the shielded gate oxide layer deep P+ in the bottom and side walls of the gate trench of the silicon carbide trench device, and distributing doping regions, precipitation dielectric layer and source and drain electrodes around it, forming a three-dimensional three-dimensional enclosing structure, the problem of high-off state oxide electric field is solved, and the durability and switching performance of the device are improved.
Patent Information
- Application Number
- CN202510363815.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2025-05-13
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Silicon carbide trench devices face high shutdown oxide electric field problems in wide bandgap applications, resulting in reduced device durability and the existing p-shield layer is difficult to effectively ground, affecting the switching performance of the device.
A new trench type silicon carbide device structure is designed, and a three-dimensional three-dimensional enclosure structure is formed by implanting a shielded gate oxide layer deep P+ in the bottom and side walls of the gate trench, and distributing doped regions, precipitated dielectric layers and source and drain electrodes around the gate oxide layer to form a three-dimensional enclosure structure to improve the protection of the gate oxide layer.
It effectively reduces the influence of the high-off state drain voltage, improves the durability of the silicon carbide device structure, reduces the JFET resistance, and improves the switching performance of the device.
Smart Images
Figure CN119997563A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a novel trench-type silicon carbide device structure and a manufacturing method thereof. Background Art
[0002] Trench MOSFET is a mature technology for silicon-based power devices. When used in wide-bandgap SiC devices, trench MOSFET faces a problem that is critical to its commercial success: high off-state oxide electric field at the bottom / corner of the trench. For long-term reliability, it is generally desirable to keep the maximum oxide electric field below 3 MV / cm. It has been proposed to set a p-shield layer under the trench gate as oxide protection. However, the p-shield layer needs to be well grounded to the source contact, otherwise it will damage the safe operating area of the device and reduce the switching performance of the device. At present, the etching process of silicon carbide trenches is relatively complex and difficult to control, and the etching of deep trenches is more difficult; the gate oxide layer at the bottom of the superimposed trench needs special protection, otherwise it will lead to a decrease in the durability of the silicon carbide device structure. Summary of the invention
[0003] In view of the above problems, the present invention provides a novel trench-type silicon carbide device structure, comprising an N-drift region, a P-body region is provided on the top of the N-drift region, a doping region is provided on the top of the P-body region; an upper P+ shielding region is provided around the P-body region; A gate oxide layer is provided at the center of the top of the doped region, and the bottom of the gate oxide layer extends into the P body region; an epitaxial layer is provided around the top of the gate oxide layer; a source and drain are provided at the top of the doped region, a polysilicon portion is provided in the gate oxide layer, the top of the polysilicon portion extends above the doped region, and a precipitation dielectric layer is provided between the inner wall of the source and drain; An N+ substrate is provided at the bottom of the N-drift region, and a drain region is provided at the bottom of the N+ substrate.
[0004] Furthermore, a P+ shielding region 1 is provided at the junction center of the N-drift region and the P body region, and upper and lower ends of the P+ shielding region 1 extend into the N-drift region and the P body region respectively.
[0005] Furthermore, the bottom of the gate oxide layer extends into the P body region, and a second P+ shielding region is provided.
[0006] Furthermore, the bottom of the gate oxide layer extends into the P body region, and a P+ shielding region three is provided.
[0007] A method for preparing a novel trench-type silicon carbide device structure, the method comprising: Front injection work: inject to obtain the P body region and doping region, and inject around the P body region to obtain the upper P+ shielding region, and then use mask exposure to form the gate trench; P-type injection work: P-type injection is performed into the gate trench to obtain a P+ shielding region 1; N-type implantation work: fill and etch to obtain a polysilicon portion, and set a gate oxide layer at the junction of the polysilicon portion and the inner wall of the gate trench; Molding work: set the precipitation dielectric layer, source and drain to obtain the finished silicon carbide device structure.
[0008] Furthermore, the P-type implantation process includes: P-type implantation is performed at the junction of the N-drift region and the P body region to form a P+ shielding region 1; The distance between the bottom deep P+ injection and the bottom of the trench is 0.2~1um.
[0009] A method for preparing a novel trench-type silicon carbide device structure, the method further comprising: Front injection work: inject to obtain the P body region and doping region, and inject around the P body region to obtain the upper P+ shielding region, and then use mask exposure to form the gate trench; P-type injection work: P-type injection is performed on the gate trench to obtain P+ shielding area 1 and P+ shielding area 2; N-type implantation work: fill and etch to obtain a polysilicon portion, and set a gate oxide layer at the junction of the polysilicon portion and the inner wall of the gate trench; Molding work: set the precipitation dielectric layer, source and drain to obtain the finished silicon carbide device structure.
[0010] Furthermore, the P-type injection process further includes: P-type implantation is performed at the bottom of the gate trench and at the junction of the N-drift region and the P body region to form a P+ shielding region 1 and a P+ shielding region 2; The distance between the P+ shielding area 1 and the P+ shielding area 2 is 0.2-1 um.
[0011] A method for preparing a novel trench-type silicon carbide device structure, the method further comprising: Front injection work: inject to obtain the P body region and doping region, and inject around the P body region to obtain the upper P+ shielding region, and then use mask exposure to form the gate trench; P-type injection work: P-type injection is performed on the gate trench to obtain P+ shielding area three; N-type implantation work: fill and etch to obtain a polysilicon portion, and set a gate oxide layer at the junction of the polysilicon portion and the inner wall of the gate trench; Molding work: set the precipitation dielectric layer, source and drain to obtain the finished silicon carbide device structure.
[0012] Furthermore, the P-type injection process further includes: P-type implantation is performed at the bottom of the gate trench to form a P+ shielding region 3; The depth of the P+ shielding region 3 is 1.2 um.
[0013] The beneficial effects of the present invention are: 1. By deeply implanting P+ at the bottom and sidewall of the gate trench to shield the gate oxide layer at the bottom of the gate trench, and distributing the doping region, dielectric layer, source and drain around the gate oxide layer, the gate oxide layer is surrounded in three dimensions, which reduces the influence of the high off-state drain voltage, improves the protection of the gate oxide layer, and thus improves the durability of the silicon carbide device structure.
[0014] 2. First, a high-concentration N-type JFET is implanted in the P body region, and then a P-type implant is performed in the dielectric layer and the bottom of the gate trench, or at the junction of the N-drift region and the P body region to form a P+ shielding region. This improves the protection of the gate oxide layer from the bottom and reduces the JFET resistance.
[0015] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0017] Figure 1 A schematic structural diagram of a silicon carbide device structure according to Embodiment 1 of the present invention is shown.
[0018] Figure 2 A schematic structural diagram of a silicon carbide device structure according to Embodiment 2 of the present invention is shown.
[0019] Figure 3 A schematic structural diagram of a silicon carbide device structure according to Embodiment 3 of the present invention is shown.
[0020] Figure 4 A flowchart of a method for preparing a silicon carbide device structure according to Embodiment 1 of the present invention is shown.
[0021] Figure 5 A flowchart of a method for preparing a silicon carbide device structure according to Embodiment 2 of the present invention is shown.
[0022] Figure 6A flowchart of a method for preparing a silicon carbide device structure according to Embodiment 3 of the present invention is shown.
[0023] In the figure: 100, N-drift region; 110, N+ substrate; 120, drain region; 200, P+ shielding region 1; 210, P+ shielding region 2; 220, P+ shielding region 3; 300, P body region; 400, doped region; 500, polysilicon part; 600, source and drain; 700, gate oxide layer; 800, precipitated dielectric layer. DETAILED DESCRIPTION
[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0025] Example 1
[0026] The embodiment of the present invention provides a novel trench-type silicon carbide device structure, including an N-drift region 100, exemplarily, as Figure 1 As shown, an N+ substrate 110 is disposed at the bottom of the N− drift region 100 , and a drain region 120 is disposed at the bottom of the N+ substrate 110 .
[0027] Exemplarily, a P body region 300 is provided on the top of the N-drift region 100, and a doping region 400 is provided on the top of the P body region 300; a P+ shielding region 200 is provided at the center of the junction of the N-drift region 100 and the P body region 300, and an upper P+ shielding region is provided around the P body region 300. The upper and lower ends of the P+ shielding region 200 extend into the N-drift region 100 and the P body region 300, respectively.
[0028] A gate oxide layer 700 is disposed at the center of the top of the doped region 400, and the bottom of the gate oxide layer 700 extends into the P body region 300. An epitaxial layer is disposed around the top of the gate oxide layer 700.
[0029] Exemplarily, a source and drain 600 is provided on the top of the doped region 400 , a polysilicon portion 500 is provided in the gate oxide layer 700 , the top of the polysilicon portion 500 extends above the doped region 400 , and a precipitation dielectric layer 800 is provided between the inner wall of the source and drain 600 .
[0030] Specifically, the doping concentration of the N-drift region 100 is , the epitaxial layer thickness is 13µm; Specifically, the gap width between the gate oxide layer 700 and the doped regions 400 on both sides is WG = 0.2~1.5 μm, the gap width between the gate oxide layer 700 and the bottom P body region 300 is 0.8~2 μm, and the doping concentration of the P+ shielding region 200 at the bottom of the P body region 300 is The thickness of the P+ shielding region 200 is 0.3-1 um.
[0031] Embodiment 2: The embodiment of the present invention also provides a novel trench-type silicon carbide device structure, exemplarily, as Figure 2 As shown, it includes an N-drift region 100 , an N+ substrate 110 is disposed at the bottom of the N-drift region 100 , and a drain region 120 is disposed at the bottom of the N+ substrate 110 .
[0032] Exemplarily, a P body region 300 is provided on the top of the N-drift region 100, and a doping region 400 is provided on the top of the P body region 300; a P+ shielding region 200 is provided at the center of the junction of the N-drift region 100 and the P body region 300, and an upper P+ shielding region is provided around the P body region 300. The upper and lower ends of the P+ shielding region 200 extend into the N-drift region 100 and the P body region 300, respectively.
[0033] A gate oxide layer 700 is disposed at the center of the top of the doped region 400. The bottom of the gate oxide layer 700 extends into the P body region 300 and is provided with a P+ shielding region 210. An epitaxial layer is disposed around the top of the gate oxide layer 700.
[0034] Exemplarily, a source and drain 600 is provided on the top of the doped region 400 , a polysilicon portion 500 is provided in the gate oxide layer 700 , the top of the polysilicon portion 500 extends above the doped region 400 , and a precipitation dielectric layer 800 is provided between the inner wall of the source and drain 600 .
[0035] Specifically, the thickness of the second P+ shielding region 210 is 0.2-1 um.
[0036] Specifically, the parameters and sizes of the gate oxide layer 700 , the doped region 400 , the P body region 300 , the upper P+ shielding region, and the P+ shielding region 1 200 are the same as those in the first embodiment.
[0037] Embodiment 3: The embodiment of the present invention also provides a novel trench-type silicon carbide device structure, exemplarily, as Figure 3 As shown, it includes an N-drift region 100 , an N+ substrate 110 is disposed at the bottom of the N-drift region 100 , and a drain region 120 is disposed at the bottom of the N+ substrate 110 .
[0038] Exemplarily, a P body region 300 is disposed on the top of the N-drift region 100 , and a doping region 400 is disposed on the top of the P body region 300 ; and an upper P+ shielding region is disposed around the P body region 300 .
[0039] A gate oxide layer 700 is disposed at the center of the top of the doped region 400. The bottom of the gate oxide layer 700 extends into the P body region 300 and is provided with a P+ shielding region 3 220. An epitaxial layer is disposed around the top of the gate oxide layer 700.
[0040] Exemplarily, a source and drain 600 is provided on the top of the doped region 400 , a polysilicon portion 500 is provided in the gate oxide layer 700 , the top of the polysilicon portion 500 extends above the doped region 400 , and a precipitation dielectric layer 800 is provided between the inner wall of the source and drain 600 .
[0041] Specifically, the parameter dimensions of the gate oxide layer 700 , the doped region 400 , the P body region 300 , the upper P+ shielding region, and the P+ shielding region 1 200 are the same as those in Example 1, and the thickness dimension of the P+ shielding region 3 220 is the same as that of the P+ shielding region 2 210 in Example 2.
[0042] The present invention shields the gate oxide layer 700 at the bottom of the gate trench by deep P+ implantation at the bottom and sidewalls of the gate trench, and distributes the doping region 400, the precipitation dielectric layer 800, and the source and drain 600 around the gate oxide layer 700, so as to surround the gate oxide layer 700 in three dimensions, thereby reducing the influence of the high off-state drain voltage, improving the protection of the gate oxide layer 700, and thus improving the durability of the silicon carbide device structure.
[0043] At the same time, the change of the PN junction barrier layer generated by the change of the potential in the P body region 300 will affect the current, and the P body region 300 is injected through the N-type JFET, and the injected N-type concentration is , so as to reduce the JFET resistance. At the same time, the electric field strength of the gate oxide layer 700 does not exceed 3.5MV / cm.
[0044] For a novel trench-type silicon carbide device structure in Example 1, the present invention also provides a method for preparing the silicon carbide device structure, illustratively, as follows: Figure 4 As shown, the preparation method includes: front injection work, P-type injection work, N-type injection work and molding work; Exemplarily, the pre-injection work includes: S101: JFET and N+ source are implanted into the N-drift region according to the designed area to form a P body region; Specifically, the JFET and N+ source in the P body region can share a single photomask or can be implanted separately; S102: injecting fifth-order elements around the P body region to form a doped region; Preferably, the bottom of the doped region overlaps with the surface of the P body region; the fifth-order elements include but are not limited to phosphorus and arsenic; S103: Setting an upper P+ shielding area around the P body area; S104: forming a gate groove by using a mask exposure; Specifically, the bottom of the gate trench should go deep into the P body region; Exemplarily, the P-type implantation process includes: S105: forming a lower P+ shielding region by performing P-type implantation at the junction of the N-drift region and the P body region; Specifically, the distance between the bottom deep P+ implantation and the bottom of the trench is preferably 0.2-1 um; Exemplarily, the N-type implantation operation includes: S106: stripping the trench mask layer and the sputtered carbon film protective layer on the top of the P body region and the upper P+ shielding region, and annealing and activating the ion implantation; S107: filling the gate trench with polysilicon to form a polysilicon portion after etching, and forming a gate oxide layer in the gap between the polysilicon portion and the gate trench by thermal oxidation; Exemplarily, the molding process includes: S108: forming a dielectric layer around the polysilicon portion located outside the gate trench; Specifically, the material of the dielectric layer is preferably a silicon dioxide layer formed by phosphosilicate glass or borophosphosilicate glass doped with boron and phosphorus; S109: forming source and drain electrodes on the top of the dielectric layer; The source electrode is an Al layer with a thickness of 4-5um, and the drain electrode is made of materials including but not limited to titanium, nickel, and silver, with a thickness of 0.2-2um, preferably 0.2, 0.3, and 2um; Furthermore, before processing the source and drain electrodes, the dielectric layer and the top of the surrounding P+ shielding area need to be ground and thinned, and then laser annealed and sputtered with metal alloys of different thicknesses.
[0045] For a novel trench-type silicon carbide device structure in Example 2, the present invention also provides a method for preparing the silicon carbide device structure, illustratively, as follows: Figure 5 As shown, the preparation method includes: front injection work, P-type injection work, N-type injection work and molding work; Exemplarily, the pre-injection work includes: S201: JFET and N+ source are implanted on the N-drift region according to the designed area to form a P body region; Specifically, the JFET and N+ source in the P body region can share a single photomask or can be implanted separately; S202: injecting fifth-order elements around the P body region to form a doped region; Preferably, the bottom of the doped region overlaps with the surface of the P body region; the fifth-order elements include but are not limited to phosphorus and arsenic; S203: Setting an upper P+ shielding area around the P body area; S204: forming a gate groove by using a mask exposure; Specifically, the bottom of the gate trench should go deep into the P body region; Exemplarily, the P-type implantation process includes: S205: performing P-type implantation at the bottom of the gate trench and at the junction of the N-drift region and the P body region to form a P+ shielding region 1 and a P+ shielding region 2; Specifically, the distance between the P+ shielding region 1 and the P+ shielding region 2 is preferably 0.2-1 um; Exemplarily, the N-type implantation operation includes: S206: stripping the trench mask layer and the sputtered carbon film protective layer on the top of the P body region and the surrounding P+ shielding region, and annealing and activating the ion implantation; S207: filling the gate trench with polysilicon to form a polysilicon portion after etching, and forming a gate oxide layer in the gap between the gate trench and the polysilicon portion by thermal oxidation; Exemplarily, the molding process includes: S208: forming a dielectric layer around the portion of the polysilicon portion located outside the gate trench; Specifically, the material of the dielectric layer is preferably a silicon dioxide layer formed by phosphosilicate glass or borophosphosilicate glass doped with boron and phosphorus; S209: forming source and drain electrodes on the top of the dielectric layer; The source electrode is an Al layer with a thickness of 4-5um, and the drain electrode is made of materials including but not limited to titanium, nickel, and silver, with a thickness of 0.2-2um, preferably 0.2, 0.3, and 2um; Furthermore, before processing the source and drain electrodes, the dielectric layer and the top of the surrounding P+ shielding area need to be ground and thinned, and then laser annealed and sputtered with metal alloys of different thicknesses.
[0046] For a novel trench-type silicon carbide device structure in Example 3, the present invention also provides a method for preparing the silicon carbide device structure, illustratively, as follows: Figure 6 As shown, the preparation method includes: front injection work, P-type injection work, N-type injection work and molding work; Exemplarily, the pre-injection work includes: S301: JFET and N+ source are implanted on the N-drift region according to the designed area to form a P body region; Specifically, the JFET and N+ source in the P body region can share a single photomask or can be implanted separately; S302: injecting fifth-order elements around the P body region to form a doped region; Preferably, the bottom of the doped region overlaps with the surface of the P body region; the fifth-order elements include but are not limited to phosphorus and arsenic; S303: Setting an upper P+ shielding area around the P body area; S304: forming a gate groove by using a mask exposure; Specifically, the bottom of the gate trench should go deep into the P body region; Exemplarily, the P-type implantation process includes: S305: implanting P-type at the bottom of the gate trench to form a P+ shielding region 3; Specifically, the depth of the P+ shielding region is preferably 1.2 um; Exemplarily, the N-type implantation operation includes: S306: stripping the trench mask layer and the sputtered carbon film protective layer on the top of the P body region and the surrounding P+ shielding region, and annealing and activating the ion implantation; S307: filling the gate trench with polysilicon to form a polysilicon portion after etching, and forming a gate oxide layer in the gap between the polysilicon portion and the gate trench by thermal oxidation; Exemplarily, the molding process includes: S308: forming a dielectric layer around the portion of the polysilicon portion outside the gate trench; Specifically, the material of the dielectric layer is preferably a silicon dioxide layer formed by phosphosilicate glass or borophosphosilicate glass doped with boron and phosphorus; S309: forming source and drain electrodes on the top of the dielectric layer; The source electrode is an Al layer with a thickness of 4-5um, and the drain electrode is made of materials including but not limited to titanium, nickel, and silver, with a thickness of 0.2-2um, preferably 0.2, 0.3, and 2um; Furthermore, before processing the source and drain electrodes, the dielectric layer and the top of the surrounding P+ shielding area need to be ground and thinned, and then laser annealed and sputtered with metal alloys of different thicknesses.
[0047] First, a high-concentration N-type JFET is implanted in the P body region, and then a P-type implant is performed in the dielectric layer and the bottom of the gate trench, or at the junction of the N-drift region and the P body region to form a P+ shielding region. This improves the protection of the gate oxide layer from the bottom and reduces the JFET resistance.
[0048] Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A novel trench-type silicon carbide device structure, comprising an N-drift region (100), characterized in that: A P body region (300) is provided on the top of the N-drift region (100), and a doping region (400) is provided on the top of the P body region (300); upper P+ shielding regions are provided around the P body region (300); A gate oxide layer (700) is provided at the center of the top of the doped region (400), and the bottom of the gate oxide layer (700) extends into the P body region (300); an epitaxial layer is provided around the top of the gate oxide layer (700); a source and drain electrode (600) is provided at the top of the doped region (400), a polysilicon portion (500) is provided in the gate oxide layer (700), the top of the polysilicon portion (500) extends above the doped region (400), and a precipitation dielectric layer (800) is provided between the polysilicon portion (500) and the inner wall of the source and drain electrode (600); An N+ substrate (110) is provided at the bottom of the N-drift region (100), and a drain region (120) is provided at the bottom of the N+ substrate (110).
2. A novel trench-type silicon carbide device structure according to claim 1, characterized in that: A P+ shielding region 1 (200) is provided at the junction center of the N-drift region (100) and the P body region (300), and the upper and lower ends of the P+ shielding region 1 (200) extend into the N-drift region (100) and the P body region (300) respectively.
3. A novel trench-type silicon carbide device structure according to claim 2, characterized in that: The bottom of the gate oxide layer (700) extends into the P body region (300), and a P+ shielding region 2 (210) is provided.
4. A novel trench-type silicon carbide device structure according to claim 1, characterized in that: The bottom of the gate oxide layer (700) extends into the P body region (300), and a P+ shielding region three (220) is provided.
5. A method for preparing the novel trench-type silicon carbide device structure according to claim 1-2, characterized in that: The preparation method comprises: Front injection work: inject to obtain the P body region and doping region, and inject around the P body region to obtain the upper P+ shielding region, and then use mask exposure to form the gate trench; P-type injection work: P-type injection is performed into the gate trench to obtain a P+ shielding region 1; N-type implantation work: fill and etch to obtain a polysilicon portion, and set a gate oxide layer at the junction of the polysilicon portion and the inner wall of the gate trench; Molding work: set the precipitation dielectric layer, source and drain to obtain the finished silicon carbide device structure.
6. The method for preparing a novel trench-type silicon carbide device structure according to claim 5, characterized in that: The P-type injection work includes: P-type implantation is performed at the junction of the N-drift region and the P body region to form a P+ shielding region 1; The distance between the bottom deep P+ injection and the bottom of the trench is 0.2~1um.
7. A method for preparing the novel trench-type silicon carbide device structure according to claims 1-3, characterized in that: The preparation method further comprises: Front injection work: inject to obtain the P body region and doping region, and inject around the P body region to obtain the upper P+ shielding region, and then use mask exposure to form the gate trench; P-type injection work: P-type injection is performed on the gate trench to obtain P+ shielding area 1 and P+ shielding area 2; N-type implantation work: fill and etch to obtain a polysilicon portion, and set a gate oxide layer at the junction of the polysilicon portion and the inner wall of the gate trench; Molding work: set the precipitation dielectric layer, source and drain to obtain the finished silicon carbide device structure.
8. The method for preparing a novel trench-type silicon carbide device structure according to claim 7, characterized in that: The P-type injection work also includes: P-type implantation is performed at the bottom of the gate trench and at the junction of the N-drift region and the P body region to form a P+ shielding region 1 and a P+ shielding region 2; The distance between the P+ shielding area 1 and the P+ shielding area 2 is 0.2-1 um.
9. A method for preparing the novel trench-type silicon carbide device structure as claimed in claims 1 and 4, characterized in that: The preparation method further comprises: Front injection work: inject to obtain the P body region and doping region, and inject around the P body region to obtain the upper P+ shielding region, and then use mask exposure to form the gate trench; P-type injection work: P-type injection is performed on the gate trench to obtain P+ shielding area three; N-type implantation work: fill and etch to obtain a polysilicon portion, and set a gate oxide layer at the junction of the polysilicon portion and the inner wall of the gate trench; Molding work: set the precipitation dielectric layer, source and drain to obtain the finished silicon carbide device structure.
10. The method for preparing a novel trench-type silicon carbide device structure according to claim 9, characterized in that: The P-type injection work also includes: P-type implantation is performed at the bottom of the gate trench to form a P+ shielding region 3; The depth of the P+ shielding region 3 is 1.2 um.