Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof. An N-type epitaxial layer in the device is arranged on a substrate in an epitaxial manner; the P-well region is arranged in the upper region of the N-type epitaxial layer in an ion implantation manner, and the plurality of N + regions are arranged in the upper region of the P-well region at intervals along the first direction; the plurality of P + masking regions are arranged at intervals along the first direction and are respectively positioned on two sides of the N + region; any P + masking region extends from the upper edge of the P-well region to the middle region of the N-type epitaxial layer along a second direction perpendicular to the first direction to form a deep masking structure; the TBI region is connected to two adjacent P + masking regions and is arranged in the N-type epitaxial layer through ion implantation; and the grid electrode penetrates through the N + region and the P-well region into the N-type epitaxial layer. The P + masking region in the structure can protect the angular position of the gate oxide groove and prevent the gate oxide groove from being broken down in advance due to electric field concentration; the TBI region forms resistance modulation in the middle of the P + masking region, and the problem that the JFET resistance formed by the P + masking region is increased when the cell size is reduced is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] Power semiconductor devices are core components of power electronics. With the development of new energy vehicles and other industries, market demand has increased significantly. The third-generation semiconductor SiC materials have significant advantages and are in line with the development trend of power electronics systems. Research on SiC power devices began in the 1980s. SiC diodes and MOSFET transistors are widely used and have high industrial maturity. SiC vertical power MOSFETs are planar and trench types. Among them, planar MOSFETs are limited by the resistance of the JFET neck region and it is difficult to reduce the on-resistance.

[0003] Trench MOSFET turns the conductive channel to the vertical crystal plane, eliminates the JFET region, and has low on-resistance, high cell density, low parasitic inductance, and fast switching speed. However, SiC trench MOSFET has many problems in process preparation and application: First, the high electric field in the SiC drift region leads to a high electric field on the gate oxide layer. This problem is exacerbated at the groove corners, causing the gate oxide layer to break down quickly under high drain voltages. At the same time, the electrostatic effects of harsh environments and the ability to withstand high-voltage spikes in the circuit are poor; Second, in order to protect the gate oxide, the trench MOSFET needs to add a P-type region in the design so that the electric field is shielded away from the trench when the device withstands reverse voltage, reducing the electric field in the gate oxide. However, the P-type region will introduce a JFET region into the device, increasing the on-resistance of the device, making it difficult to further reduce the on-resistance of the device even if the cell size of the trench MOSFET continues to decrease. Third, when high voltage, high frequency and high current are used, the parasitic parameters in the circuit cause spikes and surge voltages. The device lacks the ability to suppress surge voltages and protect against overvoltages, which can easily lead to breakdown failures in the device channel region and gradual failures in the gate structure and electrode ohmic contact region, resulting in poor reliability. Fourth, the ion implantation depth is limited, which makes it difficult to implement targeted trench gate protection structure and surge protection design from a process perspective.

[0004] In view of the current state of the art, the present invention provides a new semiconductor device and a method for preparing the same. Summary of the invention

[0005] Based on the above description, the present invention provides a semiconductor device and a method for preparing the same to solve the problems existing in the prior art of trench MOSFET, namely, rapid breakdown of the gate oxide layer under high drain voltage, poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in circuits, poor conduction performance, and poor reliability.

[0006] The technical solution of the present invention to solve the above technical problems is as follows: In a first aspect, the present invention provides a semiconductor device, comprising: a substrate, an N-type epitaxial layer, a P-well region, an N+ region, a P+ masking region, a TBI region, a gate, a source, and a drain; The N-type epitaxial layer is epitaxially arranged on the substrate; The P-well region ion implantation is arranged in the upper region of the N-type epitaxial layer, and a plurality of N+ regions are arranged in the upper region of the P-well region at intervals along the first direction; A plurality of P+ masking regions are arranged at intervals along the first direction and are respectively located on both sides of the N+ region; any of the P+ masking regions extends from the upper edge of the P-well region along a second direction perpendicular to the first direction to the middle region of the N-type epitaxial layer to form a deep masking structure; The TBI region is connected to two adjacent P+ shielding regions and is disposed in the N-type epitaxial layer by ion implantation; the gate penetrates the N+ region and the P-well region to the N-type epitaxial layer; The source is arranged at the top of the N+ region and the P+ shielding region; the drain is arranged at the bottom of the substrate.

[0007] Based on the above technical solution, the present invention can also be improved as follows.

[0008] Furthermore, the TBI region includes a plurality of TBI layers sequentially stacked and arranged along the second direction; Two ends of any one of the TBI layers are in contact with two adjacent P+ shielding regions respectively; Alternatively, the length of any one of the TBI layers is smaller than the spacing width between two adjacent P+ masking regions.

[0009] Furthermore, the widths of the plurality of TBI layers increase sequentially from the surface to the substrate, and the cross-section is trapezoidal.

[0010] Furthermore, the widths of the plurality of TBI layers decrease sequentially from the surface to the substrate, and the cross-section is in an inverted trapezoidal shape.

[0011] Furthermore, any of the TBI layers is formed by ion implantation.

[0012] Furthermore, the ion implantation of the TBI layer is full N-type implantation; or partial N-type implantation and partial P-type implantation.

[0013] Furthermore, the gate includes a gate trench, a gate dielectric layer and polysilicon; The gate trench penetrates the N+ region and the P-well region along the second direction to the N-type epitaxial layer and contacts the top of the TBI region. The gate dielectric layer is arranged on the inner wall side and top of the gate trench, and the polysilicon is arranged in a groove formed by the gate dielectric layer.

[0014] Furthermore, the MOSFET device also includes a P protection zone; The P protection zone is disposed at the bottom of the gate trench.

[0015] In a second aspect, the present invention further provides a method for preparing the semiconductor device as described in the first aspect, comprising: Growing an N-type epitaxial layer on a substrate; Forming a P-well region and an N+ region by photolithography and ion implantation; Forming a plurality of P+ masking regions by photolithography and ion implantation; Forming the TBI region by photolithography and ion implantation; Dry etching to form a gate trench; Growing and etching a gate dielectric layer and gate polysilicon at the gate trench to form a gate; Depositing source metal on the N+ region and the P+ masking region to form a source; A drain metal is deposited at the bottom of the substrate to form a drain.

[0016] Based on the above technical solution, the present invention can also be improved as follows.

[0017] Furthermore, the forming of the TBI region by photolithography and ion implantation specifically includes: forming a first TBI layer by photolithography and ion implantation, retaining the hard mask; Wet etching is used to expand the hard mask opening, and then self-aligned ion implantation is performed to form multiple TBI layers whose width increases from the surface to the substrate and whose cross-section is trapezoidal; or, sidewall deposition is used to reduce the hard mask opening, and then self-aligned ion implantation is performed to form multiple TBI layers whose width decreases from the surface to the substrate and whose cross-section is inverted trapezoidal.

[0018] Compared with the prior art, the technical solution of this application has the following beneficial technical effects: The semiconductor device and the method for manufacturing the same provided by the present invention have the following beneficial effects compared with the prior art: (1) Use P+ injection on both sides to construct a deep P masking structure - the P+ masking area, to protect the corner position of the gate oxide groove and prevent it from breaking down prematurely due to electric field concentration.

[0019] (2) Multiple ion implantations are used to construct the TBI region, forming resistance modulation in the middle of the P+ masking region, thereby alleviating the problem of increased JFET resistance formed in the P+ masking region when the cell size is reduced.

[0020] Specifically, during the formation of the TBI region, when multiple ion implantations are all N-type, the resistance of the JFET region is adjusted by multiple ion implantations. While retaining the electric field masking effect of the deep P+ regions on both sides, the influence of the JFET regions formed by the P+ on both sides on the device on-resistance is reduced, thereby improving the contradiction between the device JFET resistance and the cell size in the deep P masked trench MOSFET structure on both sides; when part of the multiple ion implantations are N-type and part of them are P-type, the P-type TBI is intermittently distributed in space, and the current is conducted from both sides of the TBI at the location where the P-type TBI ions are implanted, and the current can be conducted directly from the bottom of the trench at the location where the N-type TBI ions are implanted; when the device is in a reverse withstand voltage state, the P-type TBI further shields the strong electric field in the device and increases the reliability of the device gate oxide.

[0021] (3) The TBI region can connect the P+ masking regions on both sides, so that the entire P+ masking region forms a mesh structure. Under a large surge voltage, the depletion regions on both sides can be automatically expanded to increase the on-resistance of the JFET region, which is equivalent to a buffer circuit structure that suppresses surge spikes by itself.

[0022] (4) During the device preparation process, after the first ion implantation (the first TBI layer) of the TBI region is completed, the ion implanted hard mask is retained. The opening of the hard mask can be enlarged by wet etching, and then self-aligned implantation can be performed to increase the width of the subsequent TBI layer. The opening of the hard mask can also be reduced by depositing a sidewall, thereby reducing the width of the subsequent TBI layer. This self-aligned implantation method makes the TBI design more flexible and the preparation process simple. TBI regions of different widths can be achieved without adding a photomask, which can improve device performance while having a smaller impact on device preparation costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the structure of a semiconductor device provided in Embodiment 1 of the present invention; Figure 2 Three MOSFET devices provided for the prior art; Figure 3 A schematic diagram of the structure of a semiconductor device provided in Embodiment 2 of the present invention; Figure 4A schematic diagram of the preparation process of a semiconductor device provided in Embodiment 3 of the present invention; Figure 5 A schematic diagram of the structure of a semiconductor device provided in Embodiment 4 of the present invention; Figure 6 , Figure 7 and Figure 8 A schematic structural diagram of a semiconductor device provided in Embodiment 5 of the present invention; Fig. 9 A schematic diagram of the structure of a semiconductor device provided in Embodiment 6 of the present invention; Fig.10 and Fig.11 A schematic structural diagram of a semiconductor device provided in Embodiment 7 of the present invention; Fig.12 A schematic structural diagram of a semiconductor device provided in Embodiment 8 of the present invention; Fig.13 A schematic diagram of the structure of a semiconductor device provided in Embodiment 9 of the present invention; Fig.14 A schematic diagram of the structure of a semiconductor device provided in Embodiment 10 of the present invention; Fig.15 A schematic diagram of the preparation process of a semiconductor device provided in Example 11 of the present invention; Fig.16 SEM cross-sectional views of semiconductor devices provided in Embodiment 1 and Embodiment 11 of the present invention; Fig.17 A schematic diagram of a method for preparing a semiconductor device provided in Embodiment 12 of the present invention; In the accompanying drawings, the components represented by the reference numerals are listed as follows: 1. Substrate; 2. N-type epitaxial layer; 3. TBI region; 4. P+ masking region; 5. Gate; 6. P-well region; 7. N+ region; 8. Source; 9. Drain. DETAILED DESCRIPTION

[0024] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0025] In the prior art, in order to better protect the gate oxide layer of the trench MOSFET, especially the bottom and the trench corners, there are mainly three technical solutions and device structures for silicon carbide trench MOSFET in the industry. Figure 2 As shown, Infineon Technologies of Germany adopts "P+ semi-wrapped asymmetric trench structure" ( Figure 2In a), Sumitomo of Japan uses a p+ shielding structure constructed on both sides of the bottom of the trench gate and connected to the source ( Figure 2 b) and Japan Rohm uses a double source trench structure on both sides of the gate trench to shield the bottom of the middle gate trench ( Figure 2 c) in.

[0026] Although there are three mainstream silicon carbide trench MOSFET device structures and products in the prior art, it is still difficult to resolve the contradiction between the gate oxide electric field and the device on-resistance: in order to protect the gate oxide, the trench MOSFET needs to add a P-type region in the design so that the electric field is shielded away from the trench when the device is reversely withstand voltage, thereby reducing the electric field in the gate oxide. However, the P-type region will introduce a JFET region into the device, increasing the on-resistance of the device.

[0027] Therefore, there is an intractable contradiction between the device gate oxide electric field and the JFET resistance (on-resistance), which makes it difficult to further reduce the device on-resistance even if the cell size of the trench MOSFET continues to shrink.

[0028] For example, Infineon's "half-wrapped trench" structure uses a P-type region to wrap the trench on one side, greatly reducing the gate oxide electric field in the corner of the trench. However, it will cause the trench MOSFET to only conduct electricity through one side of the channel. The other side is used to construct a P+ shielding layer at the expense of the conduction trench, thereby increasing the on-resistance of the device unit.

[0029] Sumitomo's "grounded double mask" structure The width of the JFET region determines the strength of the gate oxide electric field and the on-resistance of the device. If the width is too large, the gate oxide layer will quickly break down under high drain voltage. If the width is too small, the serious JFET effect will cause the device resistance to increase significantly. The contradictory relationship between the two will bring design difficulties.

[0030] Rohm's "double trench" structure is similar to Sumitomo's, and both have difficulty resolving the contradiction between JFET resistance and gate oxide electric field, making it difficult for trench MOSFET to further reduce cell size and on-resistance.

[0031] Based on this, the present invention provides a new semiconductor device.

[0032] The following embodiments of the present invention are further described in detail in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention but cannot be used to limit the scope of the present invention.

[0033] It should be noted that the terms "first" and "second" and the like in the specification, claims and drawings of this application are used to distinguish different objects rather than to limit a specific order.

[0034] The TBI (trench bottom implantation) region in the present invention refers to a doping buffer region in a semiconductor device.

[0035] Example 1 like Figure 1 As shown, this embodiment provides a semiconductor device, including: a substrate 1, an N-type epitaxial layer 2, a P-well region 6, an N+ region 7, a P+ masking region 4, a TBI region 3, a gate 5, a source 8 and a drain 9.

[0036] The N-type epitaxial layer 2 is epitaxially arranged on the substrate 1 .

[0037] In an optional example, the substrate 1 is a wide bandgap semiconductor material, which may be SiC, GaN, Ga2O3, AlN, etc. This is not limited here, and can be selected according to actual needs.

[0038] Specifically, the P-well region 6 is ion-implanted and arranged in the upper region of the N-type epitaxial layer 2 , and a plurality of N+ regions 7 are arranged in the upper region of the P-well region 6 at intervals along the first direction.

[0039] A plurality of P+ shielding regions 4 are arranged at intervals along the first direction and are respectively located on both sides of the N+ region 7; any P+ shielding region 4 extends from the upper edge of the P-well region 6 along a second direction perpendicular to the first direction to the middle region of the N-type epitaxial layer 2 to form a deep shielding structure. The deep P shielding structure can protect the corner position of the gate oxide groove and prevent it from being broken down prematurely due to electric field concentration.

[0040] The multiple P+ masking regions 4 herein refer to three or more P+ masking regions 4. Figure 1 There are 3 examples in this article for demonstration and introduction.

[0041] The TBI region 3 is connected to two adjacent P+ shielding regions 4 and is arranged in the N-type epitaxial layer 2 by ion implantation; the gate 5 penetrates the N+ region 7 and the P-well region 6 to the N-type epitaxial layer 2, and the bottom contacts the top of the TBI region 3.

[0042] The TBI region 3 includes a plurality of TBI layers sequentially stacked and arranged along the second direction.

[0043] Two ends of any TBI layer are in contact with two adjacent P+ shielding regions 4 respectively.

[0044] In this embodiment, the widths of the multiple TBI layers may increase sequentially from the surface to the substrate 1 , and the cross-section may be trapezoidal.

[0045] In an example, Figure 1As shown, three TBI layers are stacked one after another, with increasing width from top to bottom and a trapezoidal cross section. In this arrangement, since the spacing between the bottom P+ masking regions 4 is larger, the resistance of the formed JFET region is smaller, which reduces the impact on the forward on-resistance of the device.

[0046] The width of the TBI region 3 for multiple ion implantations can be freely selected and is not specifically limited here.

[0047] In addition, the number of ion implantations, that is, the number of layers of the formed TBI layer n is greater than or equal to 2. In this embodiment, Figure 1 The exemplary MOSFET device has 3 TBI layers.

[0048] In summary, the TBI region 3 can form resistance modulation in the middle of the P+ masking region 4 domain, alleviating the problem of increased resistance of the JFET formed by the P+ masking region 4 domain when the cell size is reduced.

[0049] Any TBI layer is formed by ion implantation. Multiple ion implantations in the TBI region 3 can all be N-type ion implantations, which reduces the influence of the JFET regions formed by the P+ on both sides on the on-resistance of the device.

[0050] The gate 5 mentioned above includes a gate 5 trench, a gate 5 dielectric layer and polysilicon.

[0051] The gate 5 trench penetrates the N+ region 7 and the P-well region 6 along the second direction to the N-type epitaxial layer 2 and contacts the top of the TBI region 3. The gate 5 dielectric layer is arranged on the inner wall side and top of the gate 5 trench, and the polysilicon is arranged in the groove formed by the gate 5 dielectric layer.

[0052] The source 8 is disposed on the top of the N+ region 7 and the P+ shielding region 4 ; the drain 9 is disposed on the bottom of the substrate 1 .

[0053] Example 2 Based on Example 1, the difference from Example 1 is that: In this embodiment, the widths of the multiple TBI layers may also decrease sequentially from the surface to the substrate, and the cross-section may be in an inverted trapezoidal shape.

[0054] In one example, Figure 3 The exemplary MOSFET device has three TBI layers, which are stacked one after another, with the width decreasing from top to bottom and the cross section being an inverted trapezoid.

[0055] In this setting, since the P+ spacing on both sides of the trench has a greater impact on the on-resistance of the device, a wider TBI area is constructed on both sides of the trench and at the bottom of the trench to reduce the on-resistance of the device. At the same time, a closer distance is maintained at the bottom of the P+ masking area so that the P+ masking area has a better effect on electric field shielding when the device is reversely withstand voltage.

[0056] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0057] Example 3 Based on Example 2, the difference from Example 2 is that: In this embodiment, if Figure 4 As shown, the TBI region in the MOSFET device is composed of two TBI layers.

[0058] In combination with Examples 1 to 3, it can be seen that the number of TBI layers n in the present invention can be greater than or equal to 2, without specific limitation, and all fall within the protection scope of the present application.

[0059] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0060] Example 4 On the basis of Example 1, the difference from Example 1 is that: Figure 5 As shown, the length of the TBI layer is smaller than the spacing width between two adjacent P+ masking regions.

[0061] Combining Example 1 and Example 4, it can be seen that in the present invention, the width of the TBI area can be freely adjusted according to design requirements.

[0062] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0063] Example 5 Based on Example 1, the difference from Example 1 is that in this embodiment, Figure 6 and Figure 7 As shown, some TBI layers in the TBI region are N-type ion implanted, and some TBI layers are P-type ion implanted. The P-type TBI layer is spatially intermittently distributed, and the current is conducted from both sides of the TBI layer at the location where the P-type TBI ions are implanted, and the current can be conducted directly from the bottom of the trench at the location where the N-type TBI layer ions are implanted.

[0064] It should be noted that in this embodiment, the TBI layer cannot be entirely P-type injected. If it is entirely P-type injected, the device will have no current conduction path because the device in the embodiment of the present invention is conductive in the N-type region and non-conductive in the P-type region.

[0065] like Figure 8 As shown, it is a schematic diagram of the layout of the P-type TBI. The P-type area TBI can connect the P+ masking areas on both sides, so that the entire P+ masking area forms a mesh structure, and at the same time, the various areas of the P+ masking area are connected to each other.

[0066] The P-type TBI region is grounded through the P+ shielding region. Under a large surge voltage, the depletion regions on both sides can be automatically expanded to increase the on-resistance of the JFET region, which is equivalent to a buffer circuit structure that suppresses surge spikes by itself. At the same time, when the surge voltage is too large, the depletion regions on both sides continue to expand and overlap each other, playing a blocking effect, protecting the internal trench gate oxide, and playing a certain role in spike voltage overvoltage protection. It can increase the device's self-suppression resistance to surge voltage and overvoltage, and avoid device damage and reliability reduction caused by the actual delay of the overvoltage protection circuit and the overcurrent protection circuit. Moreover, it can also buffer the spikes in the circuit switching process, reduce switching losses, reduce the buffer circuit / buffer circuit structure in the circuit design, and reduce discrete components, thereby reducing costs, reducing the actual module volume, and enhancing the reliability of the SiC module.

[0067] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0068] Example 6 On the basis of Example 5, the difference from Example 5 is that the P-type TBI region can be of different shapes or a combination of different shapes.

[0069] Above Figure 8 The cross section of the TBI region shown is a square. In this embodiment, Fig. 9 As shown, the cross-section of the TBI region is hexagonal.

[0070] In a specific embodiment, the area ratio and shape of the P-type TBI region can be designed in combination with specific requirements, and the on-resistance and surge and short-circuit resistance can be adjusted, so that the design of the device is more flexible.

[0071] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0072] Example 7 Based on Example 1, the difference from Example 1 is that the TBI area can be distributed continuously or as Fig.10 The distribution is discontinuous as shown. Fig.11 The distribution is periodic.

[0073] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0074] Example 8 On the basis of Example 1, the difference from Example 1 is that: Fig.12 As shown, the MOSFET device also includes a P protection area; the P protection area is arranged at the bottom of the gate trench to better protect the trench gate oxide.

[0075] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0076] Example 9 On the basis of Example 1, the difference from Example 1 is that: Fig.13 As shown, in this embodiment, the bottom of the gate trench of the MOSFET device does not contact the TBI region, and there is a certain distance between them.

[0077] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0078] Example 10 On the basis of Example 1, the difference from Example 1 is that: Fig.14 As shown, in this embodiment, the bottom of the gate trench of the MOSFET device extends into the TBI region, and the arrangement of this embodiment has a stronger effect on improving the on-resistance.

[0079] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0080] Embodiment 11 This embodiment provides a method for preparing the semiconductor device provided in Embodiment 1, such as Fig.15 As shown, the operation is as follows: Step S1: growing an N-type epitaxial layer on a substrate; Step S2: forming a P-well region and an N+ region by photolithography and ion implantation; Step S3: forming a plurality of P+ masking regions by photolithography and ion implantation; Step S4: forming a TBI region by photolithography and ion implantation; Specifically, a first TBI layer is formed by photolithography and ion implantation, and a hard mask is retained; The hard mask opening is enlarged by wet etching, and then self-aligned ion implantation is performed to form multiple TBI layers whose width increases from the surface to the substrate and whose cross-section is trapezoidal.

[0081] Step S5: dry etching to form a gate trench; Step S6: growing and etching a gate dielectric layer and gate polysilicon at the gate trench to form a gate; Step S7: depositing source metal on the N+ region and the P+ masking region to form a source; Step S8: depositing drain metal at the bottom of the substrate to form a drain, thereby obtaining a semiconductor device.

[0082] The obtained SEM cross-sectional image of the semiconductor device is as follows: Fig.16 shown.

[0083] Since the preparation method is used to prepare the semiconductor device provided in Example 1, the beneficial effects of the semiconductor device are also applicable to the preparation method. The beneficial effects can be referred to the above description and will not be elaborated here.

[0084] Example 12 Based on the above embodiment 11, the difference of this embodiment is that: Fig.17 As shown, step S4: forming a TBI region by photolithography and ion implantation; specifically comprising: forming a first TBI layer by photolithography and ion implantation, retaining a hard mask; depositing a sidewall to reduce the hard mask opening, and then performing self-aligned ion implantation to form a plurality of TBI layers whose widths decrease in sequence from the surface to the substrate and whose cross-sections are inverted trapezoidal. For the remaining identical preparation steps, refer to the introduction of Example 11, which will not be repeated here.

[0085] In summary, the semiconductor devices and corresponding manufacturing methods provided in the above-mentioned embodiments 1 to 12 have the following technical effects: (1) Use P+ injection on both sides to construct a deep P masking structure - the P+ masking area, to protect the corner position of the gate oxide groove and prevent it from breaking down prematurely due to electric field concentration.

[0086] (2) Multiple ion implantations are used to construct the TBI region, forming resistance modulation in the middle of the P+ masking region, thereby alleviating the problem of increased JFET resistance formed in the P+ masking region when the cell size is reduced.

[0087] Specifically, during the formation of the TBI region, when multiple ion implantations are all N-type, the resistance of the JFET region is adjusted by multiple ion implantations. While retaining the electric field masking effect of the deep P+ regions on both sides, the influence of the JFET regions formed by the P+ on both sides on the device on-resistance is reduced, thereby improving the contradiction between the device JFET resistance and the cell size in the deep P masked trench MOSFET structure on both sides; when part of the multiple ion implantations are N-type and part of them are P-type, the P-type TBI is intermittently distributed in space, and the current is conducted from both sides of the TBI at the location where the P-type TBI ions are implanted, and the current can be conducted directly from the bottom of the trench at the location where the N-type TBI ions are implanted; when the device is in a reverse withstand voltage state, the P-type TBI further shields the strong electric field in the device and increases the reliability of the device gate oxide.

[0088] (3) The TBI region can connect the P+ masking regions on both sides, so that the entire P+ masking region forms a mesh structure. Under a large surge voltage, the depletion regions on both sides can be automatically expanded to increase the on-resistance of the JFET region, which is equivalent to a buffer circuit structure that suppresses surge spikes by itself.

[0089] (4) During the device preparation process, after the first ion implantation (the first TBI layer) of the TBI region is completed, the ion implanted hard mask is retained. The opening of the hard mask can be enlarged by wet etching, and then self-aligned implantation can be performed to increase the width of the subsequent TBI layer. The opening of the hard mask can also be reduced by depositing a sidewall, thereby reducing the width of the subsequent TBI layer. This self-aligned implantation method makes the TBI design more flexible and the preparation process simple. TBI regions of different widths can be achieved without adding a photomask, which can improve device performance while having a smaller impact on device preparation costs.

[0090] In the description of this specification, the description with reference to the terms "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of the present invention. In this specification, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: Substrate, N-type epitaxial layer, P-well region, N+ region, P+ masking region, TBI region, gate, source and drain; The N-type epitaxial layer is epitaxially arranged on the substrate; The P-well region ion implantation is arranged in the upper region of the N-type epitaxial layer, and a plurality of N+ regions are arranged in the upper region of the P-well region at intervals along the first direction; A plurality of P+ masking regions are arranged at intervals along the first direction and are respectively located on both sides of the N+ region; any of the P+ masking regions extends from the upper edge of the P-well region along a second direction perpendicular to the first direction to the middle region of the N-type epitaxial layer to form a deep masking structure; The TBI region is connected to two adjacent P+ shielding regions and is disposed in the N-type epitaxial layer by ion implantation; the gate penetrates the N+ region and the P-well region to the N-type epitaxial layer; The source is arranged at the top of the N+ region and the P+ shielding region; the drain is arranged at the bottom of the substrate.

2. The semiconductor device according to claim 1, wherein: The TBI region includes a plurality of TBI layers sequentially stacked and arranged along the second direction; Two ends of any one of the TBI layers are in contact with two adjacent P+ shielding regions respectively; Alternatively, the length of any of the TBI layers is smaller than the spacing width between two adjacent P+ masking regions.

3. The semiconductor device according to claim 2, characterized in that The widths of the multiple TBI layers increase sequentially from the surface to the substrate, and the cross-section is trapezoidal.

4. The semiconductor device according to claim 2, characterized in that The widths of the multiple TBI layers decrease sequentially from the surface to the substrate, and the cross-section is in an inverted trapezoidal shape.

5. The semiconductor device according to any one of claims 2 to 4, characterized in that: Any of the TBI layers is formed by ion implantation.

6. The semiconductor device according to claim 5, characterized in that The ion implantation of the TBI layer is full N-type implantation; or partial N-type implantation and partial P-type implantation.

7. The semiconductor device according to claim 1, wherein: The gate comprises a gate trench, a gate dielectric layer and polysilicon; The gate trench penetrates the N+ region and the P-well region along the second direction to the N-type epitaxial layer and contacts the top of the TBI region. The gate dielectric layer is arranged on the inner wall side and top of the gate trench, and the polysilicon is arranged in a groove formed by the gate dielectric layer.

8. The semiconductor device according to claim 7, characterized in that The MOSFET device also includes a P protection zone; The P protection zone is disposed at the bottom of the gate trench.

9. A method for preparing a semiconductor device according to any one of claims 1 to 8, characterized in that: include: Growing an N-type epitaxial layer on a substrate; Forming a P-well region and an N+ region by photolithography and ion implantation; Forming a plurality of P+ masking regions by photolithography and ion implantation; Forming the TBI region by photolithography and ion implantation; Dry etching to form a gate trench; Growing and etching a gate dielectric layer and gate polysilicon at the gate trench to form a gate; Depositing source metal on the N+ region and the P+ masking region to form a source; A drain metal is deposited at the bottom of the substrate to form a drain.

10. The preparation method according to claim 9, characterized in that: The forming of the TBI region by photolithography and ion implantation specifically includes: forming a first TBI layer by photolithography and ion implantation, retaining the hard mask; Wet etching is used to expand the hard mask opening, and then self-aligned ion implantation is performed to form multiple TBI layers whose width increases from the surface to the substrate and whose cross-section is trapezoidal; or, sidewall deposition is used to reduce the hard mask opening, and then self-aligned ion implantation is performed to form multiple TBI layers whose width decreases from the surface to the substrate and whose cross-section is inverted trapezoidal.

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