A semiconductor device and a method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same. In the above device, an N-type epitaxial layer is epitaxially grown on a substrate; a P-well region is formed by ion implantation in the upper region of the N-type epitaxial layer, and a plurality of N+ regions are arranged at intervals along a first direction in the upper region of the P-well region; a plurality of P+ masking regions are arranged at intervals along the first direction and are respectively located on both sides of the N+ regions; any one of the P+ masking regions extends from the upper edge of the P-well region to the middle region of the N-type epitaxial layer along a second direction perpendicular to the first direction to form a deep masking structure; a TBI region is connected to two adjacent P+ masking regions and is formed by ion implantation in the N-type epitaxial layer; a gate penetrates through the N+ region and the P-well region into the N-type epitaxial layer. In this structure, the P+ masking region can protect the corner position of the gate oxide, preventing it from being prematurely broken down due to electric field concentration; the TBI region forms a resistance modulation in the middle of the P+ masking region, alleviating the problem of the increase in the JFET resistance formed by the P+ masking region when the cell size is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a semiconductor device and a preparation method thereof. Background Art

[0002] Power semiconductor devices are the core components of power electronics. With the development of industries such as new energy vehicles, the market demand has increased greatly; the third-generation semiconductor SiC material has significant advantages and conforms to the development trend of power electronic systems. The research on SiC power devices began in the 1980s. SiC diodes and MOSFET transistors are widely used and have a high degree of industrial maturity. SiC vertical power MOSFETs have planar and trench types. Among them, the planar MOSFET is limited by the resistance of the JFET neck region and it is difficult to reduce the on-resistance.

[0003] The trench MOSFET transfers the conductive channel to the vertical crystal plane, eliminates the JFET region, has a low on-resistance, a high cell density, a low parasitic inductance, and a fast switching speed. However, SiC trench MOSFETs have many problems in process preparation and application:

[0004] First, the high electric field in the SiC drift region causes a very high electric field on the gate oxide layer. This problem is aggravated at the trench corners, resulting in the rapid breakdown of the gate oxide layer under high drain voltages. At the same time, it has poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit.

[0005] Second, in order to protect the gate oxide, the trench MOSFET needs to add a P-type region in the design to shield the electric field away from the trench when the device withstands reverse voltage, reducing the electric field in the gate oxide. However, the P-type region will introduce a JFET region in the device, increasing the on-resistance of the device, resulting in difficulty in further reducing the on-resistance of the device even if the cell size of the trench MOSFET is continuously reduced.

[0006] Third, when applied at high voltage, high frequency, and large current, the parasitic parameters in the circuit cause spike burrs and surge voltages. The device lacks the ability to self-suppress surge voltages and overvoltage protection, easily leading to the breakdown failure of the device channel region and the gradual failure of the gate structure and the electrode ohmic contact region, with poor reliability.

[0007] Fourth, the ion implantation depth is limited, making it difficult to implement a targeted trench gate protection structure and surge protection design from a process perspective.

[0008] Combined with the development status of the existing technology, the present invention provides a new semiconductor device and a preparation method thereof. Summary of the Invention

[0009] Based on the above description, the present invention provides a semiconductor device and a method for manufacturing the same, so as to solve the problems existing in the trench MOSFET in the prior art, such as the rapid breakdown of the gate oxide layer under high drain voltage, poor tolerance to the electrostatic effect of the harsh environment and high-voltage spikes in the circuit, as well as poor conduction performance and reliability.

[0010] The technical solution of the present invention to solve the above technical problems is as follows:

[0011] In a first aspect, the present invention provides a semiconductor device, including: a substrate, an N-type epitaxial layer, a P-well region, N+ regions, P+ masking regions, a TBI region, a gate, a source electrode and a drain electrode;

[0012] The N-type epitaxial layer is epitaxially disposed on the substrate;

[0013] The P-well region is ion-implanted in the upper region of the N-type epitaxial layer, and a plurality of the N+ regions are arranged at intervals in the upper region of the P-well region along a first direction;

[0014] A plurality of the P+ masking regions are arranged at intervals along the first direction and are respectively located on both sides of the N+ regions; any one of the P+ masking regions extends from the upper edge of the P-well region to the middle region of the N-type epitaxial layer along a second direction perpendicular to the first direction to form a deep masking structure;

[0015] The TBI region is connected to two adjacent P+ masking regions and is ion-implanted in the N-type epitaxial layer; the gate penetrates through the N+ regions and the P-well region to the N-type epitaxial layer;

[0016] The source electrode is disposed on the tops of the N+ regions and the P+ masking regions; the drain electrode is disposed at the bottom of the substrate.

[0017] On the basis of the above technical solution, the present invention can be further improved as follows.

[0018] Further, the TBI region includes a plurality of TBI layers arranged in sequence and stacked along the second direction;

[0019] Both ends of any one of the TBI layers are in contact with two adjacent P+ masking regions respectively;

[0020] Or, the length of any one of the TBI layers is less than the interval width between two adjacent P+ masking regions.

[0021] Further, the widths of the plurality of TBI layers increase sequentially from the surface to the direction of the substrate, and the cross section is trapezoidal.

[0022] Further, the widths of the multiple TBI layers decrease successively in the direction from the surface to the substrate, and the cross-section is an inverted trapezoid.

[0023] Further, any one of the TBI layers is formed by ion implantation.

[0024] Further, the ion implantation of the TBI layer is all N-type implantation; or partial N-type implantation and partial P-type implantation.

[0025] Further, the gate includes a gate trench, a gate dielectric layer, and polysilicon;

[0026] The gate trench penetrates through the N+ region and the P-well region along the second direction to contact the top of the TBI region in the N-type epitaxial layer. The gate dielectric layer is disposed on the inner wall side and the top of the gate trench, and the polysilicon is disposed in the groove formed by the gate dielectric layer.

[0027] Further, the MOSFET device further includes a P protection region;

[0028] The P protection region is disposed at the bottom of the gate trench.

[0029] In a second aspect, the present invention further provides a manufacturing method for manufacturing a semiconductor device as described in the first aspect, including:

[0030] Growing an N-type epitaxial layer on a substrate;

[0031] Forming a P-well region and an N+ region by photolithography and ion implantation;

[0032] Forming a plurality of P+ masking regions by photolithography and ion implantation;

[0033] Forming a TBI region by photolithography and ion implantation;

[0034] Dry etching to form a gate trench;

[0035] Growing and etching a gate dielectric layer and gate polysilicon at the gate trench to form a gate;

[0036] Depositing source metal on the N+ region and the P+ masking regions to form a source;

[0037] Depositing drain metal at the bottom of the substrate to form a drain, thus obtaining.

[0038] On the basis of the above technical solutions, the present invention can be further improved as follows.

[0039] Further, the forming of the TBI region by photolithography and ion implantation specifically includes:

[0040] Form the first TBI layer by photolithography and ion implantation, and retain the hard mask;

[0041] Wet-etch to enlarge the hard mask opening, and then perform self-aligned ion implantation to form multiple TBI layers with widths increasing sequentially from the surface to the substrate and trapezoidal cross-sections; or, deposit sidewalls to reduce the hard mask opening, and then perform self-aligned ion implantation to form multiple TBI layers with widths decreasing sequentially from the surface to the substrate and inverted trapezoidal cross-sections.

[0042] Compared with the prior art, the technical solution of the present application has the following beneficial technical effects:

[0043] The semiconductor device and its manufacturing method provided by the present invention have the following beneficial effects compared with the prior art:

[0044] (1) Construct a deep P masking structure - P+ masking region by using P+ implantation on both sides to protect the corner positions of the gate oxide and prevent premature breakdown due to electric field concentration.

[0045] (2) Use multiple ion implantations to construct the TBI region, forming a resistance modulation in the middle of the P+ masking region to alleviate the problem of increased JFET resistance formed in the P+ masking region when reducing the cell size.

[0046] Specifically, during the formation of the TBI region, when all multiple ion implantations are N-type implantations, the resistance of the JFET region is adjusted by using multiple ion implantations. While retaining the electric field masking effect of the deep P+ regions on both sides, the influence of the JFET regions formed by the P+ on both sides on the on-resistance of the device is alleviated, thereby improving the contradiction between the JFET resistance of the device and the cell size in the deep P masking trench MOSFET structure on both sides; when some of the multiple ion implantations are N-type and some are P-type, the P-type TBI is discontinuously distributed in space. At the positions where the P-type TBI ion implantation occurs, the current conducts from both sides of the TBI, and at the positions where the N-type TBI ion implantation occurs, the current can directly conduct from the bottom of the trench; when the device is in the reverse breakdown voltage state, the P-type TBI further shields the strong electric field in the device, increasing the reliability of the device gate oxide.

[0047] (3) The TBI region can be connected to the P+ masking regions on both sides, enabling the entire P+ masking region to form a mesh structure, which can automatically expand the depletion regions on both sides under a large surge voltage, thereby increasing the on-resistance of the JFET region, equivalent to a buffer circuit structure that self-suppresses surge spikes.

[0048] (4) During the device fabrication process, after the first ion implantation (the first TBI layer) in the TBI region, the hard mask of the ion implantation is retained. The opening of the hard mask can be enlarged by wet etching, and then self-aligned implantation is carried out to increase the width of the subsequent TBI layer; or the opening of the hard mask can be reduced by depositing sidewalls, thereby reducing the width of the subsequent TBI layer. This self-aligned implantation method makes the design of TBI more flexible, and the fabrication process is simple. Without adding a photomask, TBI regions with different widths can be achieved, which can improve the device performance while having a relatively small impact on the device fabrication cost. Description of the Drawings

[0049] Figure 1 Schematic structural diagram of the semiconductor device provided in Embodiment 1 of the present invention;

[0050] Figure 2 Three MOSFET devices provided by the prior art;

[0051] Figure 3 Schematic structural diagram of the semiconductor device provided in Embodiment 2 of the present invention;

[0052] Figure 4 Schematic preparation flow diagram of the semiconductor device provided in Embodiment 3 of the present invention;

[0053] Figure 5 Schematic structural diagram of the semiconductor device provided in Embodiment 4 of the present invention;

[0054] Figure 6 , Figure 7 and Figure 8 Schematic structural diagram of the semiconductor device provided in Embodiment 5 of the present invention;

[0055] Figure 9 Schematic structural diagram of the semiconductor device provided in Embodiment 6 of the present invention;

[0056] Figure 10 and Figure 11 Schematic structural diagram of the semiconductor device provided in Embodiment 7 of the present invention;

[0057] Figure 12 Schematic structural diagram of the semiconductor device provided in Embodiment 8 of the present invention;

[0058] Figure 13 Schematic structural diagram of the semiconductor device provided in Embodiment 9 of the present invention;

[0059] Figure 14 Schematic structural diagram of the semiconductor device provided in Embodiment 10 of the present invention;

[0060] Figure 15Schematic diagram of the preparation process of the semiconductor device provided in Embodiment 11 of the present invention;

[0061] Figure 16 SEM cross-sectional view of the semiconductor device provided in Embodiment 1 and Embodiment 11 of the present invention;

[0062] Figure 17 Schematic diagram of the preparation method of the semiconductor device provided in Embodiment 12 of the present invention;

[0063] In the drawings, the list of components represented by each reference numeral is as follows:

[0064] 1. Substrate; 2. N-type epitaxial layer; 3. TBI region; 4. P+ masking region; 5. Gate; 6. P-well region; 7. N+ region; 8. Source; 9. Drain. Detailed implementation manners

[0065] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0066] In the prior art, in order to better protect the gate oxide layer of the trench MOSFET, especially the bottom and the trench corners, there are mainly three technical solutions and device structures for the silicon carbide trench MOSFET in the industry. As Figure 2 shown, it includes "P+ semi-wrapped asymmetric trench structure" adopted by Infineon Technologies AG of Germany ( Figure 2 a in), the p+ masking structure constructed on both sides under the bottom of the trench gate and connected to the source adopted by Sumitomo Electric Industries, Ltd. of Japan ( Figure 2 b in) and the source double trench structure constructed on both sides of the gate trench to shield the bottom of the middle gate trench adopted by Rohm Co., Ltd. of Japan ( Figure 2 c in).

[0067] Although there are already three mainstream silicon carbide trench MOSFET device structures and products in the prior art, it is still difficult to solve the contradiction between the gate oxide electric field and the device on-resistance: in order to protect the gate oxide, the trench MOSFET needs to increase the P-type region in the design so as to shield the electric field at a position far from the trench when the device withstands reverse voltage and reduce the electric field in the gate oxide. However, the P-type region will introduce a JFET region in the device and increase the on-resistance of the device.

[0068] Therefore, there is a contradiction that is difficult to solve between the device gate oxide electric field and the JFET resistance (on-resistance), resulting in it being difficult to further reduce the device on-resistance even if the cell size of the trench MOSFET is continuously reduced.

[0069] For example, Infineon's "semi-packaged trench" structure uses a P-type region to wrap one side of the trench, greatly reducing the gate oxide electric field at the trench corner. However, it causes the trench MOSFET to conduct electricity only through one side channel, and the other side is used to construct a P+ shielding layer, sacrificing the conducting trench, thus increasing the on-resistance of the device unit.

[0070] In the "grounded double masking" structure of Sumitomo, the width of the JFET region determines the strength of the gate oxide electric field and the on-resistance of the device. If the width is too large, the gate oxide layer will break down rapidly under high drain voltage. If the width is too small, the severe JFET effect will cause a significant increase in the device resistance. The contradictory relationship between the two will bring difficulties in design.

[0071] Rohm's "double trench" structure is similar to Sumitomo's, and it is difficult to solve the contradiction between the JFET resistance and the gate oxide electric field, making it difficult for the trench MOSFET to further reduce the cell size and on-resistance.

[0072] Based on this, the present invention provides a new semiconductor device.

[0073] The following further describes in detail the implementation manners of the present invention with reference to the drawings and embodiments. The following embodiments are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0074] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of this application are used to distinguish different objects, rather than to limit a specific order.

[0075] The TBI (trench bottom implantation) region in the present invention refers to the doped buffer region in a semiconductor device.

[0076] Embodiment 1

[0077] As Figure 1 shown, this embodiment provides a semiconductor device, including: a substrate 1, an N-type epitaxial layer 2, a P-well region 6, an N+ region 7, a P+ masking region 4, a TBI region 3, a gate 5, a source 8, and a drain 9.

[0078] Among them, the N-type epitaxial layer 2 is epitaxially disposed on the substrate 1.

[0079] In an optional example, the substrate 1 is a wide bandgap semiconductor material, which can be materials such as SiC, GaN, Ga2O3, AlN, etc. There is no limitation here, and it can be selected according to actual needs.

[0080] Specifically, the P-well region 6 is ion-implanted in the upper region of the N-type epitaxial layer 2, and multiple N+ regions 7 are arranged at intervals along the first direction in the upper region of the P-well region 6.

[0081] A plurality of P+ masking regions 4 are arranged at intervals along a first direction and are respectively located on both sides of the N+ region 7; any one of the P+ masking regions 4 extends from the upper edge of the P-well region 6 to the middle region of the N-type epitaxial layer 2 along a second direction perpendicular to the first direction, forming a deep masking structure. Constructing the deep P masking structure can protect the corner position of the gate oxide groove and prevent it from being prematurely broken down due to electric field concentration.

[0082] The plurality of P+ masking regions 4 herein refer to three or more P+ masking regions 4. Figure 1 In the example, 3 are shown and introduced.

[0083] The TBI region 3 is connected to two adjacent P+ masking regions 4 and is formed in the N-type epitaxial layer 2 by ion implantation; the gate 5 penetrates through the N+ region 7 and the P-well region 6 to the N-type epitaxial layer 2, and the bottom contacts the top of the TBI region 3.

[0084] Among them, the TBI region 3 includes a plurality of TBI layers arranged in sequence and stacked along the second direction.

[0085] Both ends of any one TBI layer are respectively in contact with two adjacent P+ masking regions 4.

[0086] In this embodiment, the widths of the plurality of TBI layers can increase sequentially from the surface to the substrate 1, and the cross-section is trapezoidal.

[0087] In one example, as Figure 1 shown, 3 TBI layers are stacked in sequence, and the widths increase sequentially from top to bottom, and the cross-section is trapezoidal. In this setting method, since the distance between the bottom P+ masking regions 4 is larger, the resistance of the formed JFET region is smaller, reducing the influence on the forward conduction resistance of the device.

[0088] The width of the TBI region 3 formed by multiple ion implantations can be freely selected and is not specifically limited herein.

[0089] In addition, the number of ion implantations, that is, the number n of the formed TBI layers is greater than or equal to 2. In this embodiment, Figure 1 the exemplary MOSFET device has 3 TBI layers.

[0090] In summary, the TBI region 3 can form resistance modulation in the middle of the P+ masking region 4, alleviating the problem of the increase in the JFET resistance formed in the P+ masking region 4 when reducing the cell size.

[0091] Any one TBI layer is formed by ion implantation. The multiple ion implantations in the TBI region 3 can all be N-type ion implantations, reducing the influence of the JFET regions formed by the P+ on both sides on the conduction resistance of the device.

[0092] The above-mentioned gate 5 includes a gate 5 trench, a gate 5 dielectric layer, and polysilicon.

[0093] The gate 5 trench penetrates through the N+ region 7 and the P-well region 6 in the second direction to contact the top of the TBI region 3 in the N-type epitaxial layer 2. The gate 5 dielectric layer is disposed on the inner wall side and the top of the gate 5 trench, and the polysilicon is disposed in the groove formed by the gate 5 dielectric layer.

[0094] The source electrode 8 is disposed on the tops of the N+ region 7 and the P+ masking region 4; the drain electrode 9 is disposed at the bottom of the substrate 1.

[0095] Embodiment 2

[0096] Based on Embodiment 1, the difference from Embodiment 1 is as follows:

[0097] In this embodiment, the widths of multiple TBI layers can also decrease sequentially from the surface to the substrate direction, and the cross-section is an inverted trapezoid.

[0098] In one example, Figure 3 The MOSFET device in the example has 3 TBI layers, and the 3 TBI layers are stacked in sequence, with the widths decreasing sequentially from top to bottom and the cross-section being an inverted trapezoid.

[0099] In this setting method, since the P+ spacing on both sides of the trench has a great influence on the on-resistance of the device, a wider TBI region is constructed on both sides and at the bottom of the trench to reduce the on-resistance of the device. At the same time, a relatively close distance is reserved at the bottom of the P+ masking region, so that the P+ masking region has a better effect on electric field shielding when the device is reverse biased.

[0100] For the remaining same structures, refer to the introduction in Embodiment 1, and details will not be repeated here.

[0101] Embodiment 3

[0102] Based on Embodiment 2, the difference from Embodiment 2 is as follows:

[0103] In this embodiment, as Figure 4 shown, the TBI region in the MOSFET device has 2 TBI layers.

[0104] Combining Embodiments 1 to 3, it can be seen that in the present invention, the number n of the layers of the TBI layer is greater than or equal to 2, without specific limitation, and all can fall within the protection scope of this application.

[0105] For the remaining same structures, refer to the introduction in Embodiment 1, and details will not be repeated here.

[0106] Embodiment 4

[0107] Based on Embodiment 1, the difference from Embodiment 1 is as follows: As Figure 5As shown, the length of the TBI layer is less than the interval width between two adjacent P+ masking regions.

[0108] Combining Example 1 and Example 4, it can be seen that in the present invention, the width of the TBI region can be freely adjusted according to design requirements.

[0109] For the remaining same structures, refer to the introduction in Example 1 and will not be elaborated here.

[0110] Example 5

[0111] Based on Example 1, the difference from Example 1 is that in this example, as Figure 6 and Figure 7 shown, some of the TBI layers in the TBI region are N-type ion implanted, and some of the TBI layers are P-type ion implanted. The P-type TBI layers are discontinuously distributed in space. At the positions of P-type TBI ion implantation, the current conducts from both sides of the TBI layer, and at the positions of N-type TBI layer ion implantation, the current can directly conduct from the bottom of the trench.

[0112] It should be noted that in this example, not all of the TBI layers can be P-type implanted. If all are P-type implanted, there will be no current conduction path for the device because in the embodiments of the present invention, the device is conductive in the N-type region and non-conductive in the P-type region.

[0113] As Figure 8 shown, it is a layout schematic diagram of P-type TBI. The P-type TBI in the P-type region can be connected to the P+ masking regions on both sides, so that the entire P+ masking region forms a mesh structure, and at the same time, all regions of the P+ masking region are interconnected.

[0114] The P-type TBI region is grounded through the P+ masking region. Under a large surge voltage, it can automatically expand the depletion regions on both sides, thereby increasing the on-resistance of the JFET region, which is equivalent to a buffer circuit structure that self-suppresses surge spikes. At the same time, when the surge voltage is too large, the depletion regions on both sides continue to expand and overlap with each other, playing a blocking effect to protect the internal trench gate oxide, playing a certain overvoltage protection role for spike voltage, and can increase the self-suppression resistance of the device to surge voltage and overvoltage, avoiding device damage and reduction in reliability caused by the time delay in the actual operation of the overvoltage protection circuit and overcurrent protection circuit. Moreover, it can also buffer the spikes during the circuit switching process, reduce the switching loss, can reduce the buffer circuit / buffer circuit structure in the circuit design, reduce discrete components, thereby reducing costs, and also reducing the actual module volume and enhancing the reliability of the SiC module.

[0115] For the remaining same structures, refer to the introduction in Example 1 and will not be elaborated here.

[0116] Example 6

[0117] Based on Embodiment 5, the difference from Embodiment 5 is that the P-type TBI region can be of different shapes or a combination of different shapes.

[0118] The above Figure 8 The cross-section of the TBI region shown is square. In this embodiment, as Figure 9 shown, the cross-section of the TBI region is hexagonal.

[0119] In a specific embodiment, the area ratio and shape of the P-type TBI region can be designed according to specific requirements to adjust the on-resistance, surge resistance, and short-circuit resistance, making the device design more flexible.

[0120] For the remaining same structures, refer to the description of Embodiment 1, which will not be elaborated here.

[0121] Embodiment 7

[0122] Based on Embodiment 1, the difference from Embodiment 1 is that the TBI region can be continuously distributed, or as Figure 10 shown, discontinuously distributed, or as Figure 11 shown, periodically distributed.

[0123] For the remaining same structures, refer to the description of Embodiment 1, which will not be elaborated here.

[0124] Embodiment 8

[0125] Based on Embodiment 1, the difference from Embodiment 1 is that as Figure 12 shown, the MOSFET device further includes a P protection region; the P protection region is provided at the bottom of the gate trench to provide better protection for the trench gate oxide.

[0126] For the remaining same structures, refer to the description of Embodiment 1, which will not be elaborated here.

[0127] Embodiment 9

[0128] Based on Embodiment 1, the difference from Embodiment 1 is that as Figure 13 shown, in this embodiment, the bottom of the gate trench of the MOSFET device does not contact the TBI region and there is a certain distance.

[0129] For the remaining same structures, refer to the description of Embodiment 1, which will not be elaborated here.

[0130] Embodiment 10

[0131] Based on Embodiment 1, the difference from Embodiment 1 is that as Figure 14 shown, in this embodiment, the bottom of the gate trench of the MOSFET device extends into the TBI region, and this setting method has a stronger improvement effect on the on-resistance.

[0132] For the remaining same structures, refer to the description in Embodiment 1 and details are not repeated here.

[0133] Embodiment 11

[0134] This embodiment provides a method for manufacturing the semiconductor device provided in Embodiment 1. As Figure 15 shown, the operations are as follows:

[0135] Step S1: Grow an N-type epitaxial layer on the substrate;

[0136] Step S2: Form a P-well region and an N+ region through photolithography and ion implantation;

[0137] Step S3: Form a plurality of P+ masking regions through photolithography and ion implantation;

[0138] Step S4: Form a TBI region through photolithography and ion implantation;

[0139] Specifically, form a first TBI layer through photolithography and ion implantation, and retain the hard mask;

[0140] Wet-etch to expand the hard mask opening, and then perform self-aligned ion implantation to form a plurality of TBI layers with widths increasing sequentially from the surface to the substrate and trapezoidal cross-sections.

[0141] Step S5: Dry-etch to form a gate trench;

[0142] Step S6: Grow and etch a gate dielectric layer and gate polysilicon at the gate trench to form a gate;

[0143] Step S7: Deposit source metal on the N+ region and the P+ masking regions to form a source;

[0144] Step S8: Deposit drain metal at the bottom of the substrate to form a drain, thus obtaining the semiconductor device.

[0145] The SEM cross-sectional view of the obtained semiconductor device is as Figure 16 shown.

[0146] Since this manufacturing method is used to manufacture the semiconductor device provided in Embodiment 1, the beneficial effects of the semiconductor device also apply to this manufacturing method. For its beneficial effects, refer to the above effect description and details are not repeated here.

[0147] Embodiment 12

[0148] Based on the above Embodiment 11, the difference in this embodiment is that as Figure 17As shown, step S4: forming a TBI region by photolithography and ion implantation; specifically including: forming a first TBI layer by photolithography and ion implantation, and retaining the hard mask; depositing a sidewall to reduce the hard mask opening, and then performing self-aligned ion implantation to form a plurality of TBI layers with widths decreasing sequentially from the surface to the substrate and having an inverted trapezoidal cross-section. For the remaining same preparation steps, refer to the introduction in Embodiment 11, which will not be elaborated here.

[0149] In summary, the semiconductor devices and corresponding preparation methods provided by the above Embodiments 1 to 12 have the following technical effects:

[0150] (1) Constructing a deep P masking structure - a P+ masking region by using P+ implantation on both sides to protect the corner position of the gate oxide and prevent it from being prematurely broken down due to electric field concentration.

[0151] (2) Using multiple ion implantations to construct a TBI region to form a resistance modulation in the middle of the P+ masking region, and alleviating the problem of the increase in the JFET resistance formed in the P+ masking region when reducing the cell size.

[0152] Specifically, during the formation of the TBI region, when all multiple ion implantations are N-type implantations, the resistance of the JFET region is adjusted by using multiple ion implantations. While retaining the electric field masking effect of the deep P+ regions on both sides, the influence of the JFET regions formed by the P+ on both sides on the on-resistance of the device is alleviated, thereby improving the contradiction between the JFET resistance of the device and the cell size in the deep P masking trench MOSFET structure on both sides; when some of the multiple ion implantations are N-type and some are P-type, the P-type TBI is discontinuously distributed in space. At the position of the P-type TBI ion implantation, the current conducts from both sides of the TBI, and at the position of the N-type TBI ion implantation, the current can directly conduct from the bottom of the trench; when the device is in the reverse breakdown voltage state, the P-type TBI further shields the strong electric field in the device, increasing the reliability of the device gate oxide.

[0153] (3) The TBI region can be connected to the P+ masking regions on both sides, enabling the entire P+ masking region to form a mesh structure, which can automatically expand the depletion regions on both sides under a large surge voltage, thereby increasing the on-resistance of the JFET region, equivalent to a buffer circuit structure that self-suppresses the surge spike.

[0154] (4) During the device fabrication process, after the first ion implantation (the first TBI layer) in the TBI region, the hard mask of the ion implantation is retained. The opening of the hard mask can be enlarged by wet etching, and then self-aligned implantation is performed to increase the width of the subsequent TBI layer; or the opening of the hard mask can be reduced by depositing sidewalls, thereby reducing the width of the subsequent TBI layer. This self-aligned implantation method makes the design of TBI more flexible, and the fabrication process is simple. Without adding a photomask, TBI regions with different widths can be achieved, which can improve the device performance while having a relatively small impact on the device fabrication cost.

[0155] In the description of this specification, the description with reference to terms such as "specific example" or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples.

[0156] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: a substrate, an N-type epitaxial layer, a P-well region, N+ regions, P+ masking regions, a TBI region, a gate, a source electrode, and a drain electrode; The N-type epitaxial layer is epitaxially grown on the substrate; The P-well region is formed by ion implantation in the upper region of the N-type epitaxial layer, and a plurality of the N+ regions are arranged at intervals in the upper region of the P-well region along a first direction; A plurality of the P+ masking regions are arranged at intervals along the first direction and are respectively located on both sides of the N+ regions; any one of the P+ masking regions extends from the upper edge of the P-well region to the middle region of the N-type epitaxial layer along a second direction perpendicular to the first direction to form a deep masking structure; The TBI region is connected to two adjacent P+ masking regions and is formed by ion implantation in the N-type epitaxial layer; the gate penetrates through the N+ regions and the P-well region into the N-type epitaxial layer; The source electrode is arranged on the tops of the N+ regions and the P+ masking regions; the drain electrode is arranged at the bottom of the substrate; The TBI region includes a plurality of TBI layers arranged in sequence and stacked along the second direction; When both ends of any one of the TBI layers are in contact with two adjacent P+ masking regions respectively, the widths of the plurality of TBI layers increase sequentially from the surface to the substrate direction, and the cross section is trapezoidal, or the widths of the plurality of TBI layers decrease sequentially from the surface to the substrate direction, and the cross section is an inverted trapezoid; When the length of any one of the TBI layers is less than the interval width between two adjacent P+ masking regions, the widths of the plurality of TBI layers increase sequentially from the surface to the substrate direction, and the cross section is trapezoidal; The ion implantation of the TBI layer is partial N-type implantation and partial P-type implantation.

2. The semiconductor device according to claim 1, wherein Any one of the TBI layers is formed by ion implantation.

3. The semiconductor device according to claim 1, wherein The gate includes a gate trench, a gate dielectric layer, and polysilicon; The gate trench penetrates through the N+ regions and the P-well region along the second direction into the N-type epitaxial layer to contact the top of the TBI region, the gate dielectric layer is arranged on the inner wall side and the top of the gate trench, and the polysilicon is arranged in the groove formed by the gate dielectric layer.

4. The semiconductor device according to claim 3, wherein, The semiconductor device further includes a P protection region; The P protection region is arranged at the bottom of the gate trench.

5. A method for manufacturing a semiconductor device as described in any one of claims 1 to 4, characterized in that, Comprising: Growing an N-type epitaxial layer on a substrate; Forming a P-well region and N+ regions by photolithography and ion implantation; Forming a plurality of P+ masking regions by photolithography and ion implantation; Forming a TBI region by photolithography and ion implantation; Dry etching to form a gate trench; Growing and etching a gate dielectric layer and gate polysilicon at the gate trench to form a gate; Depositing source electrode metal on the N+ regions and the P+ masking regions to form a source electrode; Depositing drain electrode metal at the bottom of the substrate to form a drain electrode, thus obtaining.

6. The preparation method according to claim 5, wherein The forming of the TBI region by photolithography and ion implantation specifically includes: Forming a first-layer TBI layer by photolithography and ion implantation, and retaining a hard mask; Wet etching is used to expand the hard mask opening, followed by self-aligned ion implantation to form multiple TBI layers with trapezoidal cross-sections, where the width increases sequentially from the surface to the substrate; or, sidewall deposition is used to reduce the hard mask opening, followed by self-aligned ion implantation to form multiple TBI layers with inverted trapezoidal cross-sections, where the width decreases sequentially from the surface to the substrate.

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