A two-dimensional semiconductor transistor and a method of manufacturing the same

Abstract

The application relates to the field of electronic devices, in particular to a two-dimensional semiconductor transistor and a preparation method thereof. The two-dimensional semiconductor transistor comprises a substrate, a two-dimensional semiconductor layer, a semi-metal layer and a metal covering layer which are sequentially arranged on the substrate, the material of the semi-metal layer is bismuth or antimony, and the material of the metal covering layer is gold; wherein when the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal covering layer is greater than 1.05:1; and when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal covering layer is greater than 3.58:1. The thickness ratio between the semi-metal layer and the gold covering layer is designed, the atoms of the semi-metal layer are in an excess state, the semi-metal layer is still reserved after the interface alloying reaction between the semi-metal layer and the gold covering layer after heat treatment of the device, the contact of the device can still keep the semi-metal Bi / Sb-two-dimensional semiconductor material contact interface, and therefore the thermal stability of the two-dimensional semiconductor device is improved.

Description

Technical Field

[0001] This invention relates to the field of electronic devices, and more particularly to a two-dimensional semiconductor transistor and its fabrication method. Background Technology

[0002] Half-metals (bismuth (Bi) and antimony (Sb) can form good ohmic contacts with two-dimensional semiconductors, making them ideal contact materials for high-performance two-dimensional semiconductor transistors. Patent application CN115064588A proposes depositing half-metal Sb or an alloy containing half-metal Sb on a two-dimensional semiconductor layer to form an ohmic contact structure. The half-metal Sb, as a contact electrode, has strong van der Waals interactions and band hybridization with the two-dimensional semiconductor, enabling barrier-free transport of charge carriers at the contact interface. Sb has a high melting point and stability, which can enhance the reliability and stability of the device.

[0003] However, due to the low conductivity and susceptibility to oxidation of half-metals (Bi and Sb), an excess of gold with higher conductivity is typically deposited on the half-metal material to reduce parasitic resistance caused by low conductivity and prevent device oxidation, forming a two-dimensional semiconductor-half-metal-gold stacked structure. Previous studies have found that such a two-dimensional semiconductor-half-metal-gold stacked structure has poor thermal stability, and the half-metal contact performance of the device decreases after heat treatment. X-ray diffraction experiments have revealed that the two-dimensional semiconductor-Bi-Au and two-dimensional semiconductor-Sb-Au stacked structures undergo alloying reactions during heat treatment. The half-metal layer and the excess gold capping layer both undergo alloying reactions to become Au2Bi or AuSb2, without any excess half-metal remaining. This causes the half-metal Bi / Sb-two-dimensional semiconductor contact interface to become the Au2Bi / AuSb2-two-dimensional semiconductor contact interface, disrupting the ohmic contact between the two-dimensional semiconductor material and the half-metal. Two-dimensional semiconductor devices typically require many process steps including heat treatment. Therefore, it is necessary to solve the problem of poor thermal stability of two-dimensional semiconductor devices caused by the easy alloying reaction between the gold capping layer (Au) and the half-metal layers (Bi and Sb). Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a two-dimensional semiconductor transistor and its fabrication method, which aims to solve the problem of poor thermal stability of two-dimensional semiconductor devices caused by the easy alloying reaction between the gold capping layer (Au) and the half-metal layers (Bi and Sb).

[0005] The technical solution of the present invention is as follows:

[0006] A first aspect of the present invention provides a two-dimensional semiconductor transistor, comprising:

[0007] A substrate, wherein a two-dimensional semiconductor layer, a half-metal layer and a metal capping layer are sequentially disposed on the substrate, wherein the material of the half-metal layer is bismuth or antimony, and the material of the metal capping layer is gold;

[0008] When the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal capping layer is greater than 1.05:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal capping layer is greater than 3.58:1.

[0009] Optionally, when the material of the semi-metallic layer is bismuth, the thickness ratio of the semi-metallic layer to the metal capping layer is 2:1 to 10:1; when the material of the semi-metallic layer is antimony, the thickness ratio of the semi-metallic layer to the metal capping layer is 5:1 to 20:1.

[0010] Optionally, when the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal capping layer is 2:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal capping layer is 5:1.

[0011] Optionally, the thickness of the semi-metallic layer is 10nm-100nm, and the thickness of the metallic overlay layer is 5nm-50nm.

[0012] A second aspect of the present invention provides a method for fabricating a two-dimensional semiconductor transistor, comprising:

[0013] Provide a substrate with a two-dimensional semiconductor layer;

[0014] A two-dimensional semiconductor transistor is obtained by sequentially depositing a half-metal layer and a metal capping layer on a two-dimensional semiconductor layer, wherein the material of the half-metal layer is bismuth or antimony and the material of the metal capping layer is gold.

[0015] When the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal capping layer is greater than 1.05:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal capping layer is greater than 3.58:1.

[0016] Optionally, the deposition of the half-metal layer and the metal capping layer is performed using electron beam vacuum deposition technology, wherein the vacuum degree is less than or equal to 1×10⁻⁶. -4 Pa.

[0017] Optionally, the method for fabricating the two-dimensional semiconductor transistor further includes:

[0018] Before the step of sequentially depositing a half-metal layer and a metal capping layer on the two-dimensional semiconductor layer, photoresist is applied to the two-dimensional semiconductor layer, and the two-dimensional semiconductor layer is patterned using a photolithography process.

[0019] After the steps of sequentially depositing a half-metal layer and a metal capping layer on the two-dimensional semiconductor layer, the photoresist is removed.

[0020] Beneficial effects: By designing the thickness ratio between the half-metal layer and the gold capping layer, the present invention ensures that the atoms of the half-metal layer are in an excess state. This allows the half-metal layer to remain after the half-metal layer undergoes an interfacial alloying reaction with the gold capping layer following heat treatment. The device contact can still maintain the contact interface of the half-metal Bi / Sb-two-dimensional semiconductor material, thereby improving the thermal stability of the two-dimensional semiconductor device and enabling more process flows that include heat treatment steps to be used in the production of two-dimensional semiconductor devices. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of a two-dimensional semiconductor transistor provided by the present invention.

[0022] Figure 2 This is a schematic diagram of a method for fabricating a two-dimensional semiconductor transistor provided by the present invention.

[0023] Figure 3 This is a schematic diagram of the fabrication process of a two-dimensional semiconductor transistor provided by the present invention.

[0024] Figure 4 This is a TEM image of the contact interface between Bi and MoS2 in the MoS2 transistor of Example 1 before annealing.

[0025] Figure 5 This is a TEM image of the contact interface between Bi and MoS2 in the MoS2 transistor of Example 1 after annealing.

[0026] Figure 6 The TEM image shows the contact interface between Bi and MoS2 in the MoS2 transistor after annealing, as shown in Comparative Example 1.

[0027] Figure 7 The output characteristic curves of the MoS2 transistors in Example 1 and Comparative Example 1 before and after thermal annealing are shown.

[0028] Figure 8 The image shows the XRD patterns of the MoS2 transistor in Example 2 before and after annealing.

[0029] Figure 9 The XRD patterns of the MoS2 transistor in Comparative Example 2 are shown before and after annealing. Detailed Implementation

[0030] This invention provides a two-dimensional semiconductor transistor and its fabrication method. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0031] According to one embodiment of the present invention, a two-dimensional semiconductor transistor is provided, comprising:

[0032] A substrate, wherein a two-dimensional semiconductor layer, a half-metal layer and a metal capping layer are sequentially disposed on the substrate, wherein the material of the half-metal layer is bismuth or antimony, and the material of the metal capping layer is gold;

[0033] When the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal capping layer is greater than 1.05:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal capping layer is greater than 3.58:1.

[0034] This invention addresses the technical problem of poor thermal stability in existing two-dimensional semiconductor-semi-metal (Bi / Sb)-gold stacked devices. By designing the thickness ratio between the semi-metal layer and the gold capping layer, the atoms in the semi-metal layer are in an excess state. This ensures that even after heat treatment and the interfacial alloying reaction between the semi-metal layer and the gold capping layer, a semi-metal layer remains, and the device contact maintains the Bi / Sb-two-dimensional semiconductor material contact interface, thereby improving the thermal stability of the two-dimensional semiconductor device.

[0035] In the embodiments of the present invention, the thickness of the half-metal layer and the number of atoms thereon, as well as the thickness of the gold overlay layer and the number of atoms thereon, satisfy the following relationship:

[0036]

[0037] In Equation 1, n is the number of atoms in the layer, and NA is Avogadro's constant (6.02 × 10⁻⁶). 23 M represents the molar mass of the material in this layer, and m represents the mass of the material in this layer. For the half-metal layer and the gold capping layer, m can be expressed as density × area × thickness = ρSh. The relevant parameters of the half-metal layer material Bi / Sb and the capping layer material Au are shown in Table 1.

[0038] Table 1

[0039] Material Name M(g / mol) <![CDATA[ρ(g / cm 3 )]]> Gold (Au) 196.97 19.32 Bismuth(Bi) 208.98 9.78 Antimony (Sb) 121.76 6.68

[0040] During the heat treatment of two-dimensional semiconductor devices, the half-metal layer and the gold capping layer undergo an alloying reaction. Specifically, Bi in the half-metal layer alloys with Au in the capping layer to form Au₂Bi, and Sb in the half-metal layer alloys with Au in the capping layer to form AuSb₂. Therefore, for the process of Bi reacting with Au to form Au₂Bi, the atomic ratio of Bi to Au is n. Bi :n Au =1:2; Substituting the relevant parameters in Table 1 into Equation 1, we can obtain the thickness ratio of the half-metal layer Bi to the capping layer Au when they fully participate in the alloying reaction (the capping area S of the two materials is the same):

[0041]

[0042] In the process of Sb reacting with Au to form AuSb2, the atomic ratio of Sb to Au is n. Sb :n Au = 2:1; Substituting the relevant parameters in Table 1 into Equation 1, we can obtain the thickness ratio of the half-metal layer Sb to the capping layer Au when they fully participate in the alloying reaction (the capping area S of the two materials is the same):

[0043]

[0044] In this embodiment of the invention, the thickness ratio of the half-metal layer to the metal capping layer is determined based on the number of atoms in the half-metal layer and the metal capping layer. It is necessary to ensure that after the interface alloying reaction of the half-metal layer and the metal capping layer, there is still a surplus of atoms in the half-metal layer, meaning the number of atoms in the half-metal layer is relatively excessive. This ensures that the device contact can still maintain the contact interface of the half-metal Bi / Sb two-dimensional semiconductor material. Therefore, when the material of the half-metal layer is bismuth, the thickness ratio of the half-metal layer to the metal capping layer should be greater than 1.05:1; when the material of the half-metal layer is antimony, the thickness ratio of the half-metal layer to the metal capping layer should be greater than 3.58:1.

[0045] According to one embodiment of the present invention, when the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal capping layer is 2:1 to 10:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal capping layer is 5:1 to 20:1.

[0046] According to a preferred embodiment of the present invention, when the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal capping layer is 2:1 to 5:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal capping layer is 5:1 to 10:1.

[0047] In this invention, the thickness ratio of the semi-metal layer to the metal capping layer is within the range described in this invention. At this time, after annealing, the remaining semi-metal layer can maintain good contact with the two-dimensional material interface, while the metal capping layer can prevent the semi-metal layer from being oxidized, which is beneficial to maintaining the thermal stability of the device and improving the oxidation resistance of the device.

[0048] According to a more preferred embodiment of the present invention, when the material of the half-metal layer is bismuth, the thickness ratio of the half-metal layer to the metal capping layer is 2:1; when the material of the half-metal layer is antimony, the thickness ratio of the half-metal layer to the metal capping layer is 5:1. Compared with other ratios, this thickness ratio is optimal. With this thickness ratio, the two-dimensional semiconductor transistor can maintain good contact between the half-metal layer and the two-dimensional material interface after annealing, while also being more conducive to preventing oxidation of the half-metal layer, thus improving the thermal stability and oxidation resistance of the device.

[0049] According to one embodiment of the present invention, the material of the two-dimensional semiconductor layer may be selected from two-dimensional materials commonly used in the prior art, preferably two-dimensional materials such as MoS2, WSe2, and WS2, but is not limited thereto.

[0050] According to one embodiment of the present invention, the thickness of the semi-metallic layer is 10nm-100nm, for example, it can be 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 85nm, 90nm, 95nm, 100nm, etc.; the thickness of the metal capping layer is 5nm-50nm, for example, it can be 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, etc. Within this thickness range, the semi-metallic layer can form good contact with the two-dimensional material interface, and the metal capping layer can also prevent the semi-metallic layer from being oxidized. After annealing, it can also maintain good contact between the semi-metallic layer and the two-dimensional material interface. This is beneficial for improving the on-state current, thermal stability, and oxidation resistance of the device.

[0051] According to one embodiment of the present invention, when the material of the semi-metallic layer is bismuth, the thickness of the semi-metallic layer is 20 nm, and the thickness of the metal capping layer is 10 nm.

[0052] According to one embodiment of the present invention, when the material of the semi-metallic layer is antimony, the thickness of the semi-metallic layer is 50 nm, and the thickness of the metal capping layer is 10 nm.

[0053] According to one embodiment of the present invention, after the two-dimensional semiconductor transistor is heat-treated, a half-metal material-two-dimensional semiconductor material contact interface is maintained between the half-metal layer and the two-dimensional semiconductor layer.

[0054] In the two-dimensional semiconductor transistor of this invention, the material of the half-metal layer is bismuth or antimony, and the material of the metal capping layer is gold. By designing the thickness ratio between the half-metal layer and the gold capping layer, the atoms of the half-metal layer are in an excess state. After heat treatment, there is still a remainder of the half-metal layer. Therefore, the contact interface between the half-metal material and the two-dimensional semiconductor material can still be maintained, and a good ohmic contact is formed between the half-metal layer and the two-dimensional semiconductor layer, which improves the thermal stability of existing two-dimensional semiconductor devices.

[0055] According to an embodiment of the present invention, a method for fabricating a two-dimensional semiconductor transistor is provided, comprising:

[0056] Provide a substrate with a two-dimensional semiconductor layer;

[0057] A two-dimensional semiconductor transistor is obtained by sequentially depositing a half-metal layer and a metal capping layer on a two-dimensional semiconductor layer, wherein the material of the half-metal layer is bismuth or antimony and the material of the metal capping layer is gold.

[0058] When the material of the semi-metal layer is bismuth, the thickness ratio of the semi-metal layer to the metal capping layer is greater than 1.05:1; when the material of the semi-metal layer is antimony, the thickness ratio of the semi-metal layer to the metal capping layer is greater than 3.58:1.

[0059] In this invention, the two-dimensional semiconductor layer can be obtained by transferring it onto a substrate or by growing it directly on the surface of the substrate. The transfer or direct growth of two-dimensional semiconductor materials are both techniques commonly used in the art and are not limited herein. For example, the transfer of two-dimensional semiconductor materials can be achieved using a mechanical peeling method to peel off and transfer two-dimensional semiconductor materials (MoS2, WSe2, WS2) onto a substrate; or by using a mechanical transfer method to transfer a single-layer two-dimensional semiconductor material grown by chemical vapor deposition (CVD) onto a substrate.

[0060] According to one embodiment of the present invention, the deposition of the half-metal layer and the metal capping layer can be carried out using coating techniques commonly used in the art, such as thermal evaporation coating technology, magnetron sputtering coating technology, electron beam vacuum coating technology, etc.

[0061] According to a preferred embodiment of the present invention, the deposition of the half-metal layer and the metal capping layer is performed using electron beam vacuum deposition technology, wherein the vacuum degree is less than or equal to 1 × 10⁻⁶. -4 Pa.

[0062] According to one embodiment of the present invention, the method for fabricating the two-dimensional semiconductor transistor further includes:

[0063] Before the step of sequentially depositing a half-metal layer and a metal capping layer on the two-dimensional semiconductor layer, photoresist is applied to the two-dimensional semiconductor layer, and the two-dimensional semiconductor layer is patterned using a photolithography process.

[0064] After the steps of sequentially depositing a half-metal layer and a metal capping layer on the two-dimensional semiconductor layer, the photoresist is removed.

[0065] In this invention, photolithographic patterns can be fabricated at specific locations on a substrate with a two-dimensional semiconductor layer using photoresist and photolithography, according to specific needs. The specific shape of the photolithographic pattern can be set according to actual needs, and the specific shape is not limited here. After the steps of sequentially depositing a half-metal layer and a capping layer on the two-dimensional semiconductor layer, the photoresist on the two-dimensional semiconductor layer needs to be removed to form the pre-defined patterned half-metal layer and capping layer. The use of photoresist and photolithography processes (such as optical lithography, electron beam lithography, etc.) to pattern the two-dimensional semiconductor layer, as well as the subsequent removal of the photoresist, are all conventional techniques in the art and are not limited here.

[0066] Combination Figure 1 , Figure 2 and Figure 3 As shown, the two-dimensional semiconductor transistor and its fabrication method provided by the present invention include:

[0067] A substrate with a two-dimensional semiconductor layer is provided. The two-dimensional semiconductor layer is patterned using photoresist and photolithography. Then, a half-metal material is deposited on the two-dimensional semiconductor layer to form a half-metal layer. A capping layer material is deposited on the half-metal layer to form a metal capping layer. Finally, the photoresist is removed to obtain the two-dimensional semiconductor transistor of the present invention.

[0068] The present invention will be further described below through specific embodiments.

[0069] Example 1

[0070] This embodiment provides a method for fabricating a MoS2 transistor containing Bi (20nm) / Au (10nm) contacts, as detailed below:

[0071] The SiO2 / Si (285nm SiO2) substrate was ultrasonically cleaned with acetone, anhydrous ethanol, and deionized water for 5 minutes each. After drying with a nitrogen gun, residual water and oxygen on the substrate surface were removed using plasma cleaning. MoS2 was prepared on the substrate by mechanical exfoliation. A photoresist with a thickness of approximately 1 μm was spin-coated onto the substrate with the MoS2 layer. The substrate was pre-baked to evaporate the solvent in the photoresist and allow the film to dry and set. The pre-defined electrode pattern was exposed on the substrate using a laser direct-write lithography machine, and the patterned substrate was obtained after development. An electron beam evaporation coating machine was used to coat the substrate at a temperature of less than 10 nm.-4 Under a vacuum of Pa, a Bi thin film (20 nm thick) and an Au thin film (10 nm thick) were sequentially deposited to form a half-metal layer and a metal capping layer, respectively. The photoresist was removed by a lift-off process to obtain a MoS2 transistor containing Bi (20 nm) / Au (10 nm) contacts.

[0072] Comparative Example 1

[0073] The preparation method is the same as in Example 1, except that Bi thin film (thickness of 20 nm) and Au thin film (thickness of 30 nm) are deposited sequentially instead of Bi thin film and Au thin film in Example 1 to form half-metal layer and metal capping layer, so as to obtain MoS2 transistor containing Bi (20 nm) / Au (30 nm) contact.

[0074] The MoS2 transistor prepared in Example 1 was subjected to thermal annealing at 200°C for 6 hours. The interface between Bi and MoS2 before and after annealing was characterized by transmission electron microscopy (TEM). Figure 4 This is a TEM image of the interface between Bi and MoS2 before annealing. It can be seen that the interface between Bi and MoS2 is clear before annealing. Figure 5 This is a TEM image of the contact interface between Bi and MoS2 after annealing. It can be seen that Bi and Au underwent an alloying reaction after annealing to form Au2Bi. However, due to the retention of excess Bi, the contact interface between Bi and MoS2 remains intact and can form a good ohmic contact.

[0075] Similarly, the MoS2 transistor prepared in Comparative Example 1 was thermally annealed at 200°C for 6 hours, and the interface between Bi and MoS2 after annealing was characterized by transmission electron microscopy. Figure 6 This is a TEM image of the contact interface between Bi and MoS2 after annealing. It can be seen that after annealing, Bi and Au underwent an alloying reaction to completely generate Au2Bi, forming an Au2Bi-two-dimensional semiconductor contact interface, which disrupts the ohmic contact between the half-metal Bi and the two-dimensional semiconductor.

[0076] In addition, the electrical performance of the MoS2 transistors prepared in Example 1 and Comparative Example 1 before and after thermal annealing was tested using a Gell-Ray Electronics Fs-Pro semiconductor parameter analyzer at a base voltage of 10. -6 The device output characteristic curve is measured using Torr's closed probe station. The voltage range between the source and drain of the device is -0.5V to 0.5V, and the gate voltage is 60V.

[0077] Figure 7The figures show the output characteristic curves of the MoS2 transistors prepared in Example 1 and Comparative Example 1 before and after thermal annealing. The results show that the MoS2 transistor in Comparative Example 1 containing Bi (20nm) / Au (30nm) contacts experienced a significant decrease in current after annealing, with the current reduced to 25% of its original value. In contrast, the MoS2 transistor in Example 1 containing Bi (20nm) / Au (10nm) contacts experienced a smaller decrease in current after annealing, with the current reduced to 98% of its original value. This indicates a significant improvement in the thermal stability of the devices.

[0078] Example 2

[0079] This embodiment provides a method for fabricating a MoS2 transistor containing Sb (50nm) / Au (10nm) contacts, as detailed below:

[0080] The SiO2 / Si (285nm SiO2) substrate was ultrasonically cleaned with acetone, anhydrous ethanol, and deionized water for 5 minutes each. After drying with a nitrogen gun, residual water and oxygen on the substrate surface were removed using plasma cleaning. MoS2 was prepared on the substrate by mechanical exfoliation. A photoresist with a thickness of approximately 1 μm was spin-coated onto the substrate with the MoS2 layer. The substrate was pre-baked to evaporate the solvent in the photoresist and allow the film to dry and set. The pre-defined electrode pattern was exposed on the substrate using a laser direct-write lithography machine, and the patterned substrate was obtained after development. An electron beam evaporation coating machine was used to coat the substrate at a temperature of less than 10 nm. -4 Under a vacuum of Pa, Sb thin films (50 nm thick) and Au thin films (10 nm thick) are deposited sequentially to form a half-metal layer and a metal capping layer, respectively. The photoresist is removed by a lift-off process to obtain a MoS2 transistor containing Sb (50 nm) / Au (10 nm) contacts.

[0081] Comparative Example 2

[0082] The preparation method is the same as in Example 2, except that Sb thin film (thickness of 20 nm) and Au thin film (thickness of 30 nm) are deposited sequentially instead of Sb thin film and Au thin film in Example 2 to form half-metal layer and metal capping layer, so as to obtain MoS2 transistor containing Sb (20 nm) / Au (30 nm) contact.

[0083] The MoS2 transistor prepared in Example 2 was subjected to thermal annealing at 200°C for 30 min, and the X-ray diffraction (XRD) patterns before and after annealing were tested to analyze the compositional changes of the materials in the half-metal layer and the capping layer. Figure 8The images show the XRD patterns of the MoS2 transistor prepared in Example 2 before and after annealing. It can be seen that the Sb (50nm) / Au (10nm) thin film still has Sb (003) and Sb (006) characteristic peaks after annealing, which proves that there is excess half-metal Sb retained. Therefore, a good ohmic contact can be formed between the half-metal layer and the two-dimensional semiconductor layer.

[0084] Similarly, the MoS2 transistor prepared in Comparative Example 2 was subjected to thermal annealing at 200°C for 30 min, and the X-ray diffraction (XRD) patterns before and after annealing were measured. Figure 9 The XRD patterns of the MoS2 transistor prepared in Comparative Example 2 before and after annealing show that only the characteristic peaks of Au and AuSb2 alloy exist in the Sb (20nm) / Au (30nm) thin film after annealing. The half-metal Sb has completely participated in the alloying reaction, thus destroying the ohmic contact between the half-metal layer and the two-dimensional semiconductor layer.

[0085] In summary, this invention designs the thickness ratio between the half-metal layer and the gold capping layer to ensure that the atoms in the half-metal layer are in an excess state. As a result, after heat treatment, even after the half-metal layer and the gold capping layer undergo an interfacial alloying reaction, a half-metal layer is still retained, and the contact of the device can still maintain the contact interface of the half-metal Bi / Sb-two-dimensional semiconductor material, thereby improving the thermal stability of the two-dimensional semiconductor device.

[0086] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method of fabricating a two-dimensional semiconductor transistor, comprising: The application relates to a two-dimensional semiconductor transistor and a preparation method thereof. The application provides a substrate with a two-dimensional semiconductor layer; A semi-metal layer and a metal covering layer are sequentially deposited on the two-dimensional semiconductor layer, the material of the semi-metal layer is antimony, the material of the metal covering layer is gold, and the two-dimensional semiconductor transistor is obtained. The thickness ratio of the semi-metal layer to the metal covering layer is greater than 3.58:

1.

2. The method of claim 1, wherein the two-dimensional semiconductor transistor is a field effect transistor. The deposition of the semi-metal layer and the metal covering layer is performed using an electron beam vacuum coating technique, wherein the vacuum degree is less than or equal to 1 x 10 -4 Pa.

3. The method of claim 1, wherein the two-dimensional semiconductor transistor is a field effect transistor. The preparation method further comprises the following steps: Before the step of sequentially depositing the semi-metal layer and the metal covering layer on the two-dimensional semiconductor layer, photoresist is applied on the two-dimensional semiconductor layer, and the two-dimensional semiconductor layer is subjected to preset patterning treatment by using a photoetching process; After the step of sequentially depositing the semi-metal layer and the metal covering layer on the two-dimensional semiconductor layer, the photoresist is removed.

4. The method of claim 1, wherein the two-dimensional semiconductor transistor is a field effect transistor. The thickness ratio of the semi-metal layer to the metal covering layer is 5:1-20:

1.

5. The method of claim 1, wherein the two-dimensional semiconductor transistor is a field effect transistor. The thickness ratio of the semi-metal layer to the metal covering layer is 5:

1.

6. The method of producing a two-dimensional semiconductor transistor according to claim 1, wherein The thickness of the semi-metal layer is 10nm-100nm, and the thickness of the metal covering layer is 5nm-50nm.

7. A two-dimensional semiconductor transistor prepared by the preparation method in any one of claims 1-6.

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