Semiconductor mos device

Abstract

This invention discloses a semiconductor MOS device, comprising: an N-type drain region and a lightly doped N-type drift region stacked within a silicon wafer; at least two device cells spaced apart within the N-type drain region and the lightly doped N-type drift region; each device cell further includes a P-type left well region and a P-type right well region located on the upper left and right sides of the lightly doped N-type drift region; a moderately doped N-type vertical stripe is vertically disposed at the center between the P-type left well region and the P-type right well region in the lightly doped N-type drift region, the moderately doped N-type vertical stripe being equidistant from the P-type left well region and the P-type right well region in the horizontal direction; a trench is disposed between the P-type right well region of one device cell and the P-type left well region of another device cell in the lightly doped N-type drift region of two adjacent device cells. This invention avoids increasing the on-resistance of the device while reducing the reverse recovery time and losses from turn-on to turn-off.

Description

Technical Field

[0001] This invention relates to the field of MOS device technology, and more particularly to a semiconductor MOS device. Background Technology

[0002] Lateral power LDMOS devices, or lateral double-diffused metal-oxide-semiconductor devices, are widely used in power integration. Lateral high-voltage MOS devices offer high voltage withstand capability and are easy to integrate, making them commonly used in high-voltage and power integrated circuits. However, lateral MOS devices currently exhibit relatively large reverse recovery currents, which hinders further loss reduction. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor MOS device that avoids reducing the breakdown voltage while reducing the reverse recovery current, thereby reducing the overall loss of the device.

[0004] To achieve the above objectives, the technical solution adopted by the present invention is: a semiconductor MOS device, comprising: an N-type drain region and a lightly doped N-type drift region stacked within a silicon wafer, at least two device cells being disposed spaced apart within the N-type drain region and the lightly doped N-type drift region, wherein each device cell further comprises a left portion and a right portion located above the lightly doped N-type drift region having a P-type left well region and a P-type right well region respectively, and the upper portion of each of the P-type left well region and the P-type right well region having a first source region and a second source region respectively;

[0005] A gate electrode is disposed directly above the region between the lightly doped N-type drift region and the P-type left well region. The left end of the gate electrode extends above the region between the first source region and the lightly doped N-type drift region, and the right end of the gate electrode extends above the region between the second source region and the lightly doped N-type drift region.

[0006] There is a gate oxide layer between the gate electrode and the lightly doped N-type drift region. The lightly doped N-type drift region has a medium-doped N-type vertical stripe vertically disposed at the center between the P-type left well region and the P-type right well region. The medium-doped N-type vertical stripe is equidistant from the P-type left well region and the P-type right well region in the horizontal direction.

[0007] A first upper metal layer is located on the upper surface of the first source region and the second source region, a second upper metal layer is located on the upper surface of the gate electrode, and a lower metal layer is located on the lower surface of the N-type drain region; a trench is provided between the P-type right well region of one device cell and the P-type left well region of the other device cell in the two adjacent device cells, and an insulating dielectric pillar is filled in the trench.

[0008] The following are further improvements to the above technical solution:

[0009] 1. In the above scheme, the depth of the trench is greater than the depth of the P-type left well region and the P-type right well region respectively.

[0010] 2. In the above scheme, the insulating dielectric column is a low dielectric constant insulating dielectric column.

[0011] 3. In the above scheme, the width between the P-type left well region and the P-type right well region is 4 to 8 times the width of the medium-doped N-type vertical stripe.

[0012] 4. In the above scheme, the height of the doped N-type vertical stripe is lower than the height of the P-type left well region and the P-type right well region.

[0013] 5. In the above scheme, the first upper metal layer covers the central region of the first source region and the second source region, respectively.

[0014] 6. In the above scheme, an insulating dielectric layer is located around the first upper metal layer and covers the edge of the P-type left well region.

[0015] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art:

[0016] The semiconductor MOS device of the present invention has a P-type left well region and a P-type right well region on the left and right sides of the upper part of the lightly doped N-type drift region, respectively. The lightly doped N-type drift region has a medium-doped N-type vertical stripe in the region between the P-type left well region and the P-type right well region. The width of the medium-doped N-type vertical stripe is equal to that of the lightly doped N-type drift region between the P-type left well region and the P-type right well region. The addition of the medium-doped N-type vertical stripe at the center of the current path avoids reducing the breakdown voltage and reduces the reverse recovery current, thereby reducing the overall loss of the device. Attached Figure Description

[0017] Appendix Figure 1 This is a schematic diagram of the semiconductor MOS device of the present invention.

[0018] In the above figures: 1. Silicon wafer; 2. N-type drain region; 3. Lightly doped N-type drift region; 41. P-type left well region; 51. First source region; 52. Second source region; 6. Gate electrode; 7. Gate oxide layer; 8. Medium-doped N-type vertical stripe; 91. First upper metal layer; 92. Second upper metal layer; 10. Lower metal layer; 11. Insulating dielectric layer; 12. Device unit cell; 13. Trench; 14. Insulating dielectric pillar. Detailed Implementation

[0019] The present patent can be further understood through the specific embodiments given below, but they are not intended to limit the present patent.

[0020] Example 1: A semiconductor MOS device, as shown in the figure, includes: an N-type drain region 2 and a lightly doped N-type drift region 3 stacked within a silicon wafer 1, at least two device cells 12 are spaced apart within the N-type drain region 2 and the lightly doped N-type drift region 3, and the device cell 13 further includes a P-type left well region 41 and a P-type right well region 42 located on the upper part of the lightly doped N-type drift region 3, respectively. The upper part of each of the P-type left well region 41 and the P-type right well region 42 has a first source region 51 and a second source region 52, respectively.

[0021] A gate electrode 6 is disposed directly above the region between the lightly doped N-type drift region 3 and the P-type left well region 41 and the P-type right well region 42. The left end of the gate electrode 6 extends above the region between the first source region 51 and the lightly doped N-type drift region 3, and the right end of the gate electrode 6 extends above the region between the second source region 52 and the lightly doped N-type drift region 3.

[0022] A gate oxide layer 7 is provided between the gate electrode 6 and the lightly doped N-type drift region 3. A medium-doped N-type vertical stripe 8 is vertically disposed at the center between the P-type left well region 41 and the P-type right well region 42 in the lightly doped N-type drift region 3. The medium-doped N-type vertical stripe 8 is equidistant from the P-type left well region 41 and the P-type right well region 42 in the horizontal direction.

[0023] A first upper metal layer 91 is located on the upper surface of the first source region 51 and the second source region 52, a second upper metal layer 92 is located on the upper surface of the gate electrode 6, and a lower metal layer 10 is located on the lower surface of the N-type drain region 2; a trench 13 is provided between the P-type right well region 42 of one device cell 12 and the P-type left well region 41 of the other device cell 12 in the two adjacent device cells 12, and an insulating dielectric pillar 14 is filled in the trench 13.

[0024] In the embodiment, a deep trench 14 is provided between the P-type base region 3 and the lightly doped N-type drift region 4 of adjacent device unit cells 13. The deep trench 14 extends from the upper surface of the P-type base region 3 to the lower part of the lightly doped N-type drift region 4. An insulating dielectric portion 15 is filled in the deep trench 14, which effectively avoids leakage current between device unit cells, thereby improving the overall reliability of the device.

[0025] The depth of the aforementioned trench 13 is greater than the depth of each of the P-type left well region 41 and the P-type right well region 42.

[0026] The width between the aforementioned P-type left well region 41 and P-type right well region 42 is 5 times the width of the medium-doped N-type vertical stripe 8.

[0027] The height of the doped N-type vertical stripe 8 is lower than the height of the P-type left well region 41 and the P-type right well region 42.

[0028] An insulating dielectric layer 11 is located around the first upper metal layer 91 and covers the edge of the P-type left well region 41.

[0029] The aforementioned gate oxide layer 7 is a silicon dioxide layer.

[0030] Example 2: A semiconductor MOS device, comprising: an N-type drain region 2 and a lightly doped N-type drift region 3 stacked within a silicon wafer 1, at least two device cells 12 disposed at intervals within the N-type drain region 2 and the lightly doped N-type drift region 3, wherein each device cell 13 further comprises a left portion and a right portion located above the lightly doped N-type drift region 3 having a P-type left well region 41 and a P-type right well region 42 respectively, and the upper portion of each of the P-type left well region 41 and the P-type right well region 42 having a first source region 51 and a second source region 52 respectively;

[0031] A gate electrode 6 is disposed directly above the region between the lightly doped N-type drift region 3 and the P-type left well region 41 and the P-type right well region 42. The left end of the gate electrode 6 extends above the region between the first source region 51 and the lightly doped N-type drift region 3, and the right end of the gate electrode 6 extends above the region between the second source region 52 and the lightly doped N-type drift region 3.

[0032] A gate oxide layer 7 is provided between the gate electrode 6 and the lightly doped N-type drift region 3. A medium-doped N-type vertical stripe 8 is vertically disposed at the center between the P-type left well region 41 and the P-type right well region 42 in the lightly doped N-type drift region 3. The medium-doped N-type vertical stripe 8 is equidistant from the P-type left well region 41 and the P-type right well region 42 in the horizontal direction.

[0033] A first upper metal layer 91 is located on the upper surface of the first source region 51 and the second source region 52, a second upper metal layer 92 is located on the upper surface of the gate electrode 6, and a lower metal layer 10 is located on the lower surface of the N-type drain region 2; a trench 13 is provided between the P-type right well region 42 of one device cell 12 and the P-type left well region 41 of the other device cell 12 in the two adjacent device cells 12, and an insulating dielectric pillar 14 is filled in the trench 13.

[0034] In the embodiment, a deep trench 14 is provided between the P-type base region 3 and the lightly doped N-type drift region 4 of adjacent device unit cells 13. The deep trench 14 extends from the upper surface of the P-type base region 3 to the lower part of the lightly doped N-type drift region 4. An insulating dielectric portion 15 is filled in the deep trench 14, which effectively avoids leakage current between device unit cells, thereby improving the overall reliability of the device.

[0035] The depth of the aforementioned trench 13 is greater than the depth of each of the P-type left well region 41 and the P-type right well region 42.

[0036] The aforementioned insulating dielectric column 14 is a low dielectric constant insulating dielectric column.

[0037] The width between the aforementioned P-type left well region 41 and P-type right well region 42 is 7 times the width of the medium-doped N-type vertical stripe 8.

[0038] The height of the doped N-type vertical stripe 8 is lower than the height of the P-type left well region 41 and the P-type right well region 42.

[0039] The aforementioned first upper metal layer 91 covers the central regions of the first source region 51 and the second source region 52, respectively.

[0040] The aforementioned insulating dielectric layer 11 is a low dielectric constant insulating dielectric layer.

[0041] When using the above-mentioned semiconductor MOS device, the left and right portions of the upper part of the lightly doped N-type drift region 3 have a P-type left well region 41 and a P-type right well region 42, respectively. The lightly doped N-type drift region 3 has a medium-doped N-type vertical stripe 8 in the region between the P-type left well region 41 and the P-type right well region 42. The width of the medium-doped N-type vertical stripe 8 is equal to that of the lightly doped N-type drift region 3 between the P-type left well region 41 and the P-type right well region 42. Adding a medium-doped N-type vertical stripe at the center of the current path avoids reducing the breakdown voltage and reduces the reverse recovery current, thereby reducing the overall loss of the device.

[0042] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A semiconductor MOS device, characterized by: The application relates to a vertical power MOSFET device, comprising: an N-type drain region (2) and a lightly-doped N-type drift region (3) arranged in a silicon wafer (1) and stacked, at least two device cells (12) arranged in the N-type drain region (2) and the lightly-doped N-type drift region (3) at intervals, the device cell (13) further comprising a left part and a right part arranged on the upper part of the lightly-doped N-type drift region (3) and respectively provided with a P-type left well region (41) and a P-type right well region (42), the upper part of each of the P-type left well region (41) and the P-type right well region (42) is respectively provided with a first source region (51) and a second source region (52); a gate electrode (6) arranged above the region between the P-type left well region (41) and the P-type right well region (42) of the lightly-doped N-type drift region (3), the left end of the gate electrode (6) extends above the first source region (51) and the lightly-doped N-type drift region (3), and the right end of the gate electrode (6) extends above the second source region (52) and the lightly-doped N-type drift region (3); a gate oxide layer (7) arranged between the gate electrode (6) and the lightly-doped N-type drift region (3), and a middle-doped N-type vertical strip part (8) vertically arranged at the center between the P-type left well region (41) and the P-type right well region (42) of the lightly-doped N-type drift region (3), the distance between the middle-doped N-type vertical strip part (8) and the P-type left well region (41) and the P-type right well region (42) in the horizontal direction is equal; a first upper metal layer (91) arranged on the upper surface of the first source region (51) and the second source region (52), a second upper metal layer (92) arranged on the upper surface of the gate electrode (6), and a lower metal layer (10) arranged on the lower surface of the N-type drain region (2); a trench (13) is arranged in the lightly-doped N-type drift region (3) between the P-type right well region (42) of one device cell (12) and the P-type left well region (41) of another device cell (12) of the two adjacent device cells (12), and an insulating medium column (14) is filled in the trench (13).

2. The semiconductor MOS device of claim 1, wherein: The depth of the trench (13) is greater than the depth of each of the P-type left well region (41) and the P-type right well region (42).

3. The semiconductor MOS device of claim 1, wherein: The insulating medium column (14) is a low-dielectric-constant insulating medium column.

4. The semiconductor MOS device of claim 1, wherein: The width between the P-type left well region (41) and the P-type right well region (42) is 4-8 times the width of the middle-doped N-type vertical strip part (8).

5. The semiconductor MOS device of claim 1, wherein: The height of the middle-doped N-type vertical strip part (8) is lower than the height of the P-type left well region (41) and the P-type right well region (42).

6. The semiconductor MOS device of claim 1, wherein: The first upper metal layer (91) covers the central region of each of the first source region (51) and the second source region (52).

7. The semiconductor MOS device of claim 1, wherein: An insulating medium layer (11) is arranged around the first upper metal layer (91) and covers the upper part of the edge of the P-type left well region (41).

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