Manufacturing method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, which is applied to the technical field of semiconductors. In the invention, a function relationship between different electrical parameters of the semiconductor device under the width of the gate structure in the horizontal direction and the process parameters of the semiconductor manufacturing process is established, and the process parameter compensation value of the to-be-executed semiconductor manufacturing process of the semiconductor device is determined, that is, aiming at the actual width of the gate structure, the process parameter compensation value of the to-be-executed semiconductor manufacturing process is determined. By compensating process parameters of a target semiconductor manufacturing process to be executed by a semiconductor device comprising the actual width of the gate structure, automatic compensation of fluctuation generated by the actual width of the gate structure and the initial set width due to the influence of the manufacturing process is realized; and mass production of channel length automatic compensation of the semiconductor device is also realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits, the channel length of transistors fluctuates with the fluctuations of actual semiconductor process technology, and the impact on the performance of transistor devices is becoming increasingly greater, which in turn leads to large differences in the device performance of transistors formed on multiple substrates corresponding to the same batch of wafers or different batches of wafers. Therefore, the existing technology for the impact of the channel length on the transistor devices still needs to be improved. Summary of the invention

[0003] The object of the present invention is to provide a method for manufacturing a semiconductor device, so as to determine the process parameter compensation value of at least one semiconductor process to be executed by the semiconductor device by establishing or determining the functional relationship or correlation between the electrical parameters of the semiconductor device and the process parameters of the semiconductor process technology under the width of the gate structure, so as to realize automatic compensation for the width of the gate structure by utilizing the compensation method for the semiconductor process technology.

[0004] In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, comprising: The correlation between the plurality of electrical parameters of the semiconductor device and the process parameters of the target semiconductor manufacturing process at the widths of different gate structures in the horizontal direction is pre-established.

[0005] A substrate having at least one gate structure formed thereon is provided.

[0006] The actual width of the gate structure in the horizontal direction is measured, and based on the correlation, a compensation value of the process parameter of the target semiconductor process technology corresponding to the electrical parameter of the semiconductor device at the target value under the actual width of the gate structure is determined, and the compensation value is the difference between the initial setting value of the process parameter and the target value.

[0007] The target semiconductor process is performed on the substrate and / or the gate structure.

[0008] In some optional examples, the semiconductor device may include a MOS transistor or a CMOS transistor.

[0009] In some optional examples, the electrical parameter may include an on-current parameter, a turn-on voltage parameter, or a drain-source cut-off current parameter.

[0010] In some optional examples, the target semiconductor process may be at least one of an ion doping process and a spacer process.

[0011] In some optional examples, the process parameters of the sidewall process may include the thickness of the sidewall in the horizontal direction; the correlation between the multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor process at different widths of the gate structure in the horizontal direction includes: at different widths of the gate structure in the horizontal direction, the on-current parameter is inversely proportional to the turn-on voltage parameter as the thickness of the sidewall process gradually increases, and is directly proportional to the drain-source cut-off current parameter.

[0012] In some optional examples, the ion doping process may include pocket doping and / or light drain doping, and the process parameters of the ion doping process may include the implantation dose and / or implantation depth of the doped ions; the correlation between the multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor process at different horizontal widths of the gate structure includes: at different horizontal widths of the gate structure, the on-current parameter is directly proportional to the drain-source cut-off current parameter as the implantation dose of the ion doping process gradually decreases or the implantation depth gradually increases, and is inversely proportional to the turn-on voltage parameter.

[0013] In some optional examples, the step of determining the process parameter compensation value of the target semiconductor process technology corresponding to the electrical parameter of the semiconductor device at the target value under the actual width of the gate structure may include: determining the target value of the electrical parameter of the semiconductor device under the actual width of the gate structure.

[0014] By utilizing the correlation between the multiple electrical parameters and the process parameters of the target semiconductor process technology at the horizontal widths of different gate structures, the target values ​​of the process parameters of the target semiconductor process technology to be executed by the semiconductor device are determined when the values ​​of the electrical parameters are the target values.

[0015] A difference operation is performed between the determined target value of the process parameter and the initial setting value thereof, and the result of the difference operation is used as the compensation value of the corresponding process parameter.

[0016] In some optional examples, the initial setting value range of the thickness of the sidewall in the horizontal direction may be: 50nm~100nm, and the process parameter compensation value range of the thickness of the sidewall in the horizontal direction may be: 0nm~200nm.

[0017] In some optional examples, the process parameter compensation value range of the implantation dose of the dopant ions may be 1E-16 to 1E-11, and the process parameter compensation value range of the implantation depth of the dopant ions may be 2KeV to 100KeV.

[0018] In some optional examples, the doping ions may include N-type ions and / or P-type ions.

[0019] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects: The present invention provides a method for manufacturing a semiconductor device, comprising: pre-establishing the correlation between multiple electrical parameters of the semiconductor device and the process parameters of a target semiconductor process technology at the widths of different gate structures in the horizontal direction, providing a substrate on which at least one gate structure is formed, measuring the actual width of the gate structure in the horizontal direction, and based on the correlation, determining the compensation value of the process parameter of the target semiconductor process technology corresponding to the electrical parameter of the semiconductor device at the target value at the actual width of the gate structure, and performing the target semiconductor process technology on the substrate and / or the gate structure.

[0020] In the present invention, by establishing a functional relationship between different electrical parameters of the semiconductor device under the condition of the width of the gate structure in the horizontal direction (hereinafter referred to as the width of the gate structure) and the process parameters of the semiconductor process technology, the process parameter compensation value of the semiconductor process technology to be executed of the semiconductor device is determined, and an unexpected effect is obtained: for the actual width of the gate structure, by using the process parameters of the target semiconductor process technology to be executed by the semiconductor device including the actual width of the gate structure to compensate, the fluctuation caused by the actual width of the gate structure and the initial set width due to the influence of the process technology is automatically compensated, the device performance of the semiconductor device is improved, and it is ensured that the channel lengths of different semiconductor devices corresponding to different annotated wafers or the same batch of wafers can meet the design requirements, that is, the mass production of automatic compensation of the channel length of the semiconductor device is realized, that is, the compensation efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings: Figure 1 It is a schematic flow chart of a method for manufacturing a semiconductor device in one embodiment of the present invention.

[0022] Figure 2An exemplary curve relationship diagram corresponding to the correlation between multiple electrical parameters of a semiconductor device in an embodiment of the present invention and process parameters of a target semiconductor manufacturing process at different widths of gate structures in the horizontal direction.

[0023] Figure 3 Another exemplary curve relationship diagram corresponding to the correlation between multiple electrical parameters of a semiconductor device in an embodiment of the present invention and process parameters of a target semiconductor manufacturing process at different widths of gate structures in the horizontal direction.

[0024] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0025] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0026] With the development trend of ultra-large-scale integrated circuits, the fluctuation of the channel length of transistors with the fluctuation of the actual semiconductor process technology has an increasingly greater impact on the performance of transistor devices, which in turn leads to large differences in the device performance of transistors formed on multiple substrates corresponding to the same batch of wafers or different batches of wafers. For example, the channel length of transistors shortens with the fluctuation of the actual semiconductor process technology, and the shortening degree of transistors formed on multiple substrates corresponding to the same batch of wafers or different batches of wafers is different. In addition, as the width of the gate structure of the transistor (also known as the gate length) decreases, its electrical parameters will change, for example, the turn-on voltage continues to decrease, the drain-source cut-off current increases exponentially, and so on.

[0027] At present, the prior art often adjusts the process parameters of the semiconductor process used to form the gate structure to avoid the problem of poor performance of transistor devices or even failure of transistor devices caused by fluctuations in the width of the gate structure due to fluctuations in the actual process technology.

[0028] In order to solve the above problems, the present invention proposes a method for manufacturing a semiconductor device and a computer-readable storage medium, so as to determine the process parameter compensation value (i.e., the difference between an initial set value and a target value) of at least one semiconductor process to be executed by the semiconductor device by establishing a correlation or functional relationship between the electrical parameters of the semiconductor device and the process parameters of the semiconductor process under the width of the gate structure, so as to realize automatic compensation for the width of the gate structure by compensating the semiconductor process.

[0029] Please refer to Figure 1 As shown, Figure 1 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device in one embodiment of the present invention. Figure 1 As shown, the method for manufacturing the semiconductor device may include at least the following steps: Step S101 , pre-establishing correlations between a plurality of electrical parameters of the semiconductor device and process parameters of a target semiconductor manufacturing process at different gate structure widths in a horizontal direction.

[0030] Step S102 , providing a substrate having at least one gate structure formed thereon.

[0031] Step S103, measuring the actual width of the gate structure in the horizontal direction, and based on the correlation, determining the compensation value of the process parameter of the target semiconductor process technology corresponding to the electrical parameter of the semiconductor device at the target value under the actual width of the gate structure, wherein the compensation value is the difference between the initial setting value of the process parameter and the target value.

[0032] Step S104 , performing the target semiconductor process on the substrate and / or the gate structure.

[0033] In the above step S101, actual data sets located in different batches of wafers or the same batch of wafers may be collected first, and the actual data sets may be used as sample sets; in one embodiment, the actual data sets may include electrical parameters of the corresponding semiconductor devices (such as CMOS transistors or MOS transistors) and process parameters of the corresponding semiconductor process technology that has been executed under the gate structures with different widths formed on multiple substrates included in the different batches of wafers or the same batch of wafers. Wherein, the semiconductor devices may include: MOS transistors or CMOS transistors, the electrical parameters may include: on-current parameters (Ion), turn-on voltage parameters (Vt) or drain-source cut-off current parameters (Ioff) of MOS transistors or CMOS transistors, and the semiconductor process technology may include: ion doping process and / or sidewall process, but is not limited thereto.

[0034] Since the width of the gate structures formed on different substrates will be affected by factors such as the process parameters and process equipment of the actual process technology, after using the same machine to prepare gate structures on different batches of wafers or multiple substrates contained in the same batch of wafers, the widths of multiple gate structures formed on different substrates or on the same substrate will be different from their expected initial widths (hereinafter referred to as the initial set widths). Therefore, the existing technology can compensate for the value of the corresponding initial set width before forming the gate structure through empirical values, so that the width of the actually formed gate structure (hereinafter referred to as the actual width) meets the design requirements.

[0035] Another method for compensating for transistor performance fluctuations caused by fluctuations in the width of a gate structure is proposed in an embodiment of the present invention. Specifically, the actual data sets (sample sets) collected in step S101 and located in different batches of wafers or the same batch of wafers can be trained to determine the correlation / functional relationship between the electrical parameters of the semiconductor device corresponding to the width of the gate structure and the process parameters of the target semiconductor process technology for different gate structure widths, that is, for a certain width of the gate structure, the electrical parameters of the transistor with the gate structure of the width are determined from the sample set, such as the parameter values ​​of voltage, current, etc., the thickness value of the sidewall formed by the transistor in the horizontal direction and the process parameter value of the sidewall process when forming the sidewall, the ion doping concentration of the ion implantation region formed in the substrate on both sides of the sidewall and the process parameter value of the ion implantation process performed when forming the ion implantation region, and then based on the above-determined values, the correlation between the multiple electrical parameters of the gate structure and the process parameters of the semiconductor process technology performed by it at a certain width is obtained. Then, in the process of preparing the gate structure, the actual width of the gate structure formed on the substrate can be compensated by compensating the process parameters of the subsequent semiconductor manufacturing process of the semiconductor device, so that even if the width of the gate structure of the semiconductor device has errors due to fluctuations in the process, its overall electrical characteristics and device performance are stable.

[0036] In a first optional example, if the semiconductor process subsequently performed on the substrate with the gate structure formed thereon is the sidewall spacer process, then the process parameters of the sidewall spacer process may include the thickness of the sidewall in the horizontal direction. Based on the above sample set, through multiple trainings, the correlation or functional relationship between the multiple electrical parameters of the CMOS transistor or MOS transistor and the sidewall thickness of the sidewall spacer process at different gate structure widths in the horizontal direction can be determined; in other words, by training the actual data in the sample set, the changing trend (for example, increase or decrease) between the multiple electrical parameters of the CMOS transistor or MOS transistor as the sidewall thickness of the sidewall spacer process changes at different gate structure widths in the horizontal direction can be obtained.

[0037] Specifically, the correlation between the multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor process technology at different widths of the gate structure in the horizontal direction can be: at different widths of the gate structure in the horizontal direction, the on-current parameter changes with the change of the process parameters of the sidewall process and the turn-on voltage parameter, or with the drain-source cut-off current parameter. For example, the on-current parameter is inversely proportional to the turn-on voltage parameter as the thickness of the sidewall process gradually increases, and is directly proportional to the drain-source cut-off current parameter, such as Figure 2 As shown, Figure 2 An exemplary curve relationship diagram corresponding to the correlation between multiple electrical parameters of a semiconductor device in an embodiment of the present invention and process parameters of a target semiconductor process technology at different widths of gate structures in the horizontal direction; wherein, Figure 2 The black lines in the figure represent the target values ​​of the on-current parameter (Ion) and the turn-on voltage parameter (Vt) of the semiconductor device under different process parameters of the ion doping process and the spacer process.

[0038] In one embodiment, the sidewall process may specifically include: first using a deposition process, such as at least one of a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process, to form a sidewall material layer that buries the gate structure on the substrate, such as at least one of silicon nitride and silicon oxide, and then using an etching process, such as at least one of a dry etching process or a wet etching process, to selectively remove the sidewall material layer to form sidewalls of a target set thickness only on the side walls of the gate structure.

[0039] In a second optional example, if the semiconductor process subsequently performed on the substrate with the gate structure is the ion doping process, wherein the ion doping process may include pocket doping (also referred to as pocket implantation process) and / or drain light doping (also referred to as LDD implantation process), the process parameters of the ion doping process may specifically include the implantation dose and / or implantation depth of the doped ions, but are not limited thereto; then based on the above sample set, through multiple trainings, the correlation or functional relationship between the multiple electrical parameters of the CMOS transistor or MOS transistor and the process parameters of the ion doping process at different gate structure widths in the horizontal direction can be determined; in other words, by training the actual data in the sample set, the changing trends (for example, increase or decrease) between the multiple electrical parameters of the CMOS transistor or MOS transistor as the doping concentration / implantation dose of the ion doping process changes at different gate structure widths in the horizontal direction can be obtained.

[0040] Specifically, the correlation between the multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor process technology at different widths of the gate structure in the horizontal direction may be: at different widths of the gate structure in the horizontal direction, the on-current parameter changes with the change of the process parameters of the sidewall process and the turn-on voltage parameter, or the drain-source cut-off current parameter. For example, the on-current parameter is proportional to the drain-source cut-off current parameter as the implantation dose of the ion doping process gradually decreases or the implantation depth gradually increases, and is inversely proportional to the turn-on voltage parameter, such as Figure 3 As shown, Figure 3 is another example curve relationship diagram corresponding to the electrical model in one embodiment of the present invention. In one embodiment, the ion doping process may specifically include: after forming the gate structure, performing N-type or P-type ion implantation on the substrate on both sides of the gate structure to sequentially form corresponding pocket doping regions and / or lightly doped drain regions; wherein, Figure 3 The black lines in the figure represent the target values ​​of the on-current parameter (Ion) and the drain-source off-current parameter (Ioff) of the semiconductor device under different process parameters of the ion doping process and the spacer process.

[0041] In a third optional example, if the semiconductor process subsequently performed on the substrate with the gate structure formed thereon includes both the ion doping process and the sidewall process, then based on the above sample set, through multiple trainings, it is possible to establish an integration of the correlations or functional relationships corresponding to the first example and the second example above, for example, the result of convolution, as the final correlation or functional relationship between the multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor process at the horizontal width of different gate structures, which will not be repeated here.

[0042] In the above step S102, following the above step S101, a substrate can be provided, and the substrate can be any suitable substrate material known in the art, such as a silicon substrate, a silicon-containing substrate (such as SiC, SiGe) or a silicon-on-insulator substrate or a substrate composed of other suitable materials, etc., but not limited thereto. In one embodiment, one substrate can be provided in step S102, and multiple substrates can also be provided, such as providing multiple substrates contained in a batch of wafers, and then, a gate material layer is formed on the one or more substrates by using a deposition process such as a chemical vapor deposition process, such as single crystal silicon (crystalline silicon), polycrystalline silicon (poly silicon), amorphous silicon (amorphous silicon), doped silicon (doped silicon), silicon germanium (SiGe), or other suitable semiconductor materials, but not limited thereto, and then an etching process, such as a dry etching process, is used to form one or more discrete gate structures on the substrate.

[0043] In the above step S103, due to the process parameters of the etching process and the deposition process and the errors on the process equipment, the width of the gate structure formed in step S102 is bound to be different from the corresponding initially set width. Therefore, in the embodiment of the present invention, the actual width of each of the gate structures formed in step S102 in the horizontal direction (hereinafter referred to as the actual width of the gate structure) can be measured first, and then the actual width of the gate structure (for example, represented by A) and the corresponding initially set width (for example, represented by B) are differenced to obtain the width compensation value of each gate structure (for example, represented by C), where C=AB; then, based on the actual width of the gate structure, the compensation value of the semiconductor process to be subsequently executed on the substrate including the gate structure (referred to as the target semiconductor process in the embodiment of the present invention) is determined by the correlation between the multiple electrical parameters of the semiconductor device provided in the embodiment of the present invention and the process parameters of the target semiconductor process at the width of different gate structures in the horizontal direction.

[0044] Specifically, the correlation determined by training in step S101 is first used to determine the target value corresponding to each electrical parameter of the semiconductor device containing the gate structure under the actual width of the gate structure, and then the target value of the process parameter of the target semiconductor process technology to be executed for the semiconductor device containing the gate structure is determined. At this time, the target value of the process parameter of the target semiconductor process technology to be executed is the optimal value to ensure the electrical performance of the semiconductor device; then the target value of the process parameter determined is subtracted from the initial setting value, and the result of the subtraction is used as the compensation value of the corresponding process parameter, thereby adjusting the initial setting value of the process parameter of the target semiconductor process technology to be executed on the substrate containing the gate structure.

[0045] In one embodiment, if the target semiconductor process technology is the sidewall process, the initial setting value range of the thickness of the sidewall in the horizontal direction may be: 50nm~100nm, and the process parameter compensation value range of the thickness of the sidewall in the horizontal direction may be: 0nm~200nm, that is, 1nm, 2nm, 10nm, 20nm, 30nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, etc., but not limited to this. Similarly, if the target semiconductor process is the ion implantation process, the process parameter compensation value range of the implantation dose of the doped ions may be 1E-16~1E-11, that is, 1E-15, 1E-14, 1E-13, 1E-12, etc., and the process parameter compensation value range of the implantation depth of the doped ions may be 2KeV~100KeV, that is, 2KeV, 5KeV, 10KeV, 20KeV, 30KeV, 40KeV, 50KeV, 70KeV, 80KeV, 90KeV, 100KeV, etc.

[0046] In the above step S104, following the above step S103, after the process parameters of the target semiconductor process technology to be executed by the semiconductor device are adjusted to the initial set values, the target semiconductor process technology can be performed on the substrate formed with the gate structure based on the adjusted process parameters, thereby achieving the purpose of automatically compensating for the fluctuation caused by the actual width of the gate structure and the initial set width due to the influence of the process technology, that is, reducing the performance impact of the semiconductor device caused by the process deviation, improving the process stability of the semiconductor process technology, and improving the overall performance of the semiconductor device.

[0047] At the same time, since the embodiment of the present invention adjusts the process parameters of the corresponding target semiconductor process for each gate structure when the widths of the gate structures formed on different substrates are different, the present invention can also realize mass production of automatic compensation of the channel length of semiconductor devices.

[0048] It should be understood that the horizontal direction mentioned in the embodiment of the present invention is a direction parallel to the surface of the substrate.

[0049] In summary, the present invention provides a method for manufacturing a semiconductor device, including: pre-establishing the correlation between multiple electrical parameters of the semiconductor device and the process parameters of a target semiconductor process technology at the widths of different gate structures in the horizontal direction, providing a substrate on which at least one gate structure is formed, measuring the actual width of the gate structure in the horizontal direction, and based on the correlation, determining the compensation value of the process parameter of the target semiconductor process technology corresponding to the electrical parameter of the semiconductor device at the target value at the actual width of the gate structure, and performing the target semiconductor process technology on the substrate and / or the gate structure.

[0050] In the present invention, by establishing a functional relationship between different electrical parameters of the semiconductor device under the condition of the width of the gate structure in the horizontal direction (hereinafter referred to as the width of the gate structure) and the process parameters of the semiconductor process technology, the process parameter compensation value of the semiconductor process technology to be executed of the semiconductor device is determined, and an unexpected effect is obtained: for the actual width of the gate structure, by using the process parameters of the target semiconductor process technology to be executed by the semiconductor device including the actual width of the gate structure to compensate, the fluctuation caused by the actual width of the gate structure and the initial set width due to the influence of the process technology is automatically compensated, the device performance of the semiconductor device is improved, and it is ensured that the channel lengths of different semiconductor devices corresponding to different annotated wafers or the same batch of wafers can meet the design requirements, that is, the mass production of automatic compensation of the channel length of the semiconductor device is realized, that is, the compensation efficiency is improved.

[0051] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0052] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, electronic device, and computer-readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0053] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Preliminarily establishing correlations between a plurality of electrical parameters of the semiconductor device and process parameters of a target semiconductor manufacturing process at different widths of gate structures in a horizontal direction; Providing a substrate having at least one gate structure formed thereon; Measuring the actual width of the gate structure in the horizontal direction, and based on the correlation, determining a compensation value of a process parameter of the target semiconductor manufacturing process corresponding to the electrical parameter of the semiconductor device at a target value under the actual width of the gate structure, wherein the compensation value is a difference between an initial setting value of the process parameter and a target value; The target semiconductor process is performed on the substrate and / or the gate structure.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The semiconductor device includes a MOS transistor or a CMOS transistor.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The electrical parameters include on-current parameters, turn-on voltage parameters or drain-source cut-off current parameters.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The target semiconductor process technology is at least one of an ion doping process and a sidewall spacer process.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The process parameters of the sidewall process include the thickness of the sidewall in the horizontal direction; The correlation between multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor process technology at different horizontal widths of the gate structure includes: at different horizontal widths of the gate structure, the on-current parameter is inversely proportional to the turn-on voltage parameter as the thickness of the sidewall process gradually increases, and is directly proportional to the drain-source cut-off current parameter.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The ion doping process includes pocket doping and / or drain light doping, and the process parameters of the ion doping process include implantation dose and / or implantation depth of the doping ions; The correlation between multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor process technology at different horizontal widths of the gate structure includes: at different horizontal widths of the gate structure, the on-current parameter is directly proportional to the drain-source cut-off current parameter as the implantation dose of the ion doping process gradually decreases or the implantation depth gradually increases, and is inversely proportional to the turn-on voltage parameter.

7. The method for manufacturing a semiconductor device according to claim 5 or 6, characterized in that: The step of determining a process parameter compensation value of the target semiconductor process technology corresponding to the electrical parameter of the semiconductor device at a target value under the actual width of the gate structure comprises: determining a target value of the electrical parameter of the semiconductor device at the actual width of the gate structure; Determine, by using the correlation between the plurality of electrical parameters and the process parameters of the target semiconductor process technology at the widths of different gate structures in the horizontal direction, the target value of the process parameter of the target semiconductor process technology to be executed by the semiconductor device when the value of the electrical parameter is the target value; A difference operation is performed between the determined target value of the process parameter and the initial setting value thereof, and the result of the difference operation is used as the compensation value of the corresponding process parameter.

8. The method for manufacturing a semiconductor device according to claim 5, wherein: The initial setting value range of the thickness of the side wall in the horizontal direction is: 50nm~100nm, and the process parameter compensation value range of the thickness of the side wall in the horizontal direction is: 0nm~200nm.

9. The method for manufacturing a semiconductor device according to claim 6, wherein: The process parameter compensation value range of the implantation dose of the doping ions is 1E-16 to 1E-11, and the process parameter compensation value range of the implantation depth of the doping ions is 2KeV to 100KeV.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The doping ions include N-type ions and / or P-type ions.

Images