A manufacturing method of a semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device, which is applied to the field of semiconductor technology. In the present invention, a functional relationship between different electrical parameters of the semiconductor device and process parameters of the semiconductor manufacturing process is established in the horizontal direction of the gate structure at a width, and a process parameter compensation value for the semiconductor manufacturing process to be performed on the semiconductor device is determined. That is, for the actual width of the gate structure, by compensating the process parameters of the target semiconductor manufacturing process to be performed on the semiconductor device including the actual width of the gate structure, automatic compensation for the fluctuation caused by the manufacturing process between the actual width and the initially set width of the gate structure is achieved, and mass production of automatic compensation for the channel length of the semiconductor device is also realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for manufacturing a semiconductor device. Background Art

[0002] In semiconductor manufacturing, with the development trend of very large scale integrated circuits, the channel length of transistors fluctuates with the fluctuations of the actual semiconductor manufacturing process, and the impact on the performance of transistor devices is also increasing. As a result, there are significant differences in the device performance of transistors formed on multiple substrates corresponding to the same batch of wafers or different batches of wafers. Therefore, the prior art still needs to improve the impact of the channel length on the transistor devices. Summary of the Invention

[0003] The purpose of the present invention is to provide a method for manufacturing a semiconductor device, by establishing or determining the functional relationship or correlation between the electrical parameters of the semiconductor device under the width of the gate structure and the process parameters of the target semiconductor manufacturing process, determining the compensation value of the process parameters of at least one semiconductor manufacturing process to be executed for the semiconductor device, and realizing the automatic compensation of the width of the gate structure by compensating the semiconductor manufacturing process.

[0004] To solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device, including:

[0005] Pre-establish the correlation between multiple electrical parameters of the semiconductor device under the width in the horizontal direction of different gate structures and the process parameters of the target semiconductor manufacturing process.

[0006] Provide a substrate on which at least one gate structure is formed.

[0007] Measure the actual width of the gate structure in the horizontal direction, and based on the correlation, determine the compensation value of the process parameters of the target semiconductor manufacturing process corresponding to the electrical parameters of the semiconductor device when taking the target value under the actual width of the gate structure, where the compensation value is the difference between the initial set value and the target value of the process parameter.

[0008] Execute the target semiconductor manufacturing process on the substrate and / or the gate structure.

[0009] In some alternative examples, the semiconductor device may include a MOS transistor or a CMOS transistor.

[0010] In some alternative examples, the electrical parameters may include a conduction current parameter, a turn-on voltage parameter, or a drain-source cut-off current parameter.

[0011] In some alternative examples, the target semiconductor manufacturing process may be at least one of an ion doping process and a spacer process.

[0012] In some alternative examples, the process parameters of the spacer process may include the thickness of the spacer in the horizontal direction; the correlation between the process parameters of the target semiconductor manufacturing process and the electrical parameters of the semiconductor device at different widths in the horizontal direction of different gate structures includes: at different widths in the horizontal direction of different gate structures, the on-current parameter is inversely proportional to the threshold voltage parameter and directly proportional to the drain-source cut-off current parameter as the thickness of the spacer process gradually increases.

[0013] In some alternative examples, the ion doping process may include pocket doping and / or drain light doping, and the process parameters of the ion doping process may include the implantation dose and / or implantation depth of the doped ions; the correlation between the process parameters of the target semiconductor manufacturing process and the electrical parameters of the semiconductor device at different widths in the horizontal direction of different gate structures includes: at different widths in the horizontal direction of different gate structures, the on-current parameter is directly proportional to the drain-source cut-off current parameter and inversely proportional to the threshold voltage parameter as the implantation dose of the ion doping process gradually decreases or the implantation depth gradually increases.

[0014] In some alternative examples, the step of determining the compensation value of the process parameters of the target semiconductor manufacturing process corresponding to the electrical parameters of the semiconductor device when the electrical parameters take target values at the actual width of the gate structure may include: determining the target values of the electrical parameters of the semiconductor device at the actual width of the gate structure.

[0015] Using the correlation between the process parameters of the target semiconductor manufacturing process and the electrical parameters of the semiconductor device at different widths in the horizontal direction of different gate structures, determine the target values of the process parameters of the target semiconductor manufacturing process to be performed by the semiconductor device when the values of the electrical parameters are the target values.

[0016] Perform a subtraction operation on the determined target value of the process parameter and its initial set value, and use the result of the subtraction operation as the compensation value of the corresponding process parameter.

[0017] In some alternative examples, the initial set value range of the thickness of the spacer in the horizontal direction may be: 50 nm to 100 nm, and the process parameter compensation value range of the thickness of the spacer in the horizontal direction may be: 0 nm to 200 nm.

[0018] In some alternative examples, the process parameter compensation value range of the implantation dose of the doped ions may be: 1E-16~1E-11, and the process parameter compensation value range of the implantation depth of the doped ions may be: 2KeV~100KeV.

[0019] In some alternative examples, the doped ions may include N-type ions and / or P-type ions.

[0020] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects:

[0021] The present invention provides a method for manufacturing a semiconductor device, including: pre-establishing the correlation between multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor manufacturing process at different widths in the horizontal direction of the gate structure, providing a substrate on which at least one gate structure is formed, measuring the actual width of the gate structure in the horizontal direction, and based on the correlation, determining the compensation value of the process parameters of the target semiconductor manufacturing process corresponding to the target values of the electrical parameters of the semiconductor device at the actual width of the gate structure, and performing the target semiconductor manufacturing process on the substrate and / or the gate structure.

[0022] In the present invention, by establishing the functional relationship between different electrical parameters of the semiconductor device and the process parameters of the semiconductor manufacturing process at the width of the gate structure in the horizontal direction (hereinafter simply referred to as the width of the gate structure), the compensation value of the process parameters of the semiconductor manufacturing process to be performed on the semiconductor device is determined, and the unexpected effect is: for the actual width of the gate structure, by compensating the process parameters of the target semiconductor manufacturing process to be performed on the semiconductor device including the actual width of the gate structure, automatic compensation for the fluctuation caused by the manufacturing process between the actual width of the gate structure and the initially set width is achieved, improving the device performance of the semiconductor device, ensuring that the channel lengths of different semiconductor devices corresponding to different annotated wafers or wafers of the same batch can meet the design requirements, that is, realizing the mass production of automatic channel length compensation of semiconductor devices, and also improving the compensation efficiency. Description of the Drawings

[0023] The drawings are used to provide a further understanding of the present application, and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application, but do not constitute a limitation to the present application. In the drawings:

[0024] Figure 1 It is a schematic flow chart of the method for manufacturing a semiconductor device in an embodiment of the present invention.

[0025] Figure 2This is an example curve relationship diagram corresponding to the correlation between multiple electrical parameters of a semiconductor device in an embodiment of the present invention and the process parameters of a target semiconductor manufacturing process at different widths in the horizontal direction of different gate structures.

[0026] Figure 3 This is another example curve relationship diagram corresponding to the correlation between multiple electrical parameters of a semiconductor device in an embodiment of the present invention and the process parameters of a target semiconductor manufacturing process at different widths in the horizontal direction of different gate structures.

[0027] In the drawings, the same components are denoted by the same reference numerals, and the drawings are not drawn to actual scale. Detailed implementation manners

[0028] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further elaborated in detail below with reference to the drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0029] With the development trend of very large scale integrated circuits, the channel length of transistors fluctuates with the fluctuations of the actual semiconductor manufacturing process, and the impact on the performance of transistor devices is also increasing, which further leads to significant differences in the performance of transistors formed on multiple substrates corresponding to the same batch of wafers or different batches of wafers. For example, the channel length of transistors shortens with the fluctuations of the actual semiconductor manufacturing process, and the shortening degrees of transistors formed on multiple substrates corresponding to the same batch of wafers or different batches of wafers are different. Moreover, as the width (also the gate length) of the gate structure of transistors decreases, its electrical parameters will change. For example, the turn-on voltage continuously decreases, and the drain-source cut-off current increases exponentially, etc.

[0030] Currently, the prior art often adjusts the process parameters of the semiconductor manufacturing process used to form the gate structure to avoid the problem that the performance of transistor devices deteriorates or even the transistor devices fail due to the fluctuations of the width of the gate structure caused by the fluctuations of the actual manufacturing process.

[0031] To solve the above problems, the present invention provides a method for manufacturing a semiconductor device and a computer-readable storage medium, which can determine the compensation value (i.e., the difference between the initial setting value and the target value) of the process parameters of at least one semiconductor manufacturing process to be performed on the semiconductor device by establishing the correlation or functional relationship between the electrical parameters of the semiconductor device and the process parameters of the semiconductor manufacturing process under the width of the gate structure, so as to automatically compensate for the width of the gate structure by compensating the semiconductor manufacturing process.

[0032] Please refer to Figure 1 as shown in Figure 1 FIG. Figure 1 which is a schematic flow chart of the method for manufacturing a semiconductor device according to an embodiment of the present invention. As

[0033] shown, the method for manufacturing a semiconductor device may at least include the following steps:

[0034] Step S101: Pre-establish the correlation between multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor manufacturing process under the width in the horizontal direction of different gate structures.

[0035] Step S102: Provide a substrate on which at least one gate structure is formed.

[0035] Step S103: Measure the actual width of the gate structure in the horizontal direction, and based on the correlation, determine the compensation value of the process parameters of the target semiconductor manufacturing process corresponding to the electrical parameters of the semiconductor device when taking the target values under the actual width of the gate structure, where the compensation value is the difference between the initial setting value and the target value of the process parameters.

[0036] Step S104: Perform the target semiconductor manufacturing process on the substrate and / or the gate structure.

[0037] In the above step S101, the actual data sets located on different batches of wafers or the same batch of wafers may be collected first, and the actual data sets may be used as a sample set; in one embodiment, the actual data sets may include the electrical parameters of the semiconductor device (such as CMOS transistors or MOS transistors) and the process parameters of the corresponding semiconductor manufacturing processes already performed under the gate structures with different widths formed on multiple substrates included in different batches of wafers or the same batch of wafers. Among them, the semiconductor device may include: MOS transistors or CMOS transistors, the electrical parameters may include: the on-current parameter (Ion), the threshold voltage parameter (Vt), or the off-current parameter (Ioff) of the MOS transistor or CMOS transistor, and the semiconductor manufacturing process may include: ion doping process and / or spacer process, but not limited thereto.

[0038] Since the widths of the gate structures formed on different substrates are affected by factors such as the process parameters of the actual manufacturing process and the process equipment, etc., after preparing the gate structures on different batches of wafers or multiple substrates included in the same batch of wafers using the same machine tool, the widths of the multiple gate structures formed on different substrates or on the same substrate will be different from their initially designed widths (hereinafter simply referred to as the initial set widths). Furthermore, in the prior art, through empirical values, the values of the corresponding initial set widths can be compensated before forming the gate structures, so that the widths of the actually formed gate structures (hereinafter simply referred to as the actual widths) meet the design requirements.

[0039] In an embodiment of the present invention, another method for compensating for the performance fluctuations of transistors caused by the width fluctuations of the gate structures is proposed. Specifically, the actual data sets (sample sets) collected in different batches of wafers or the same batch of wafers in step S101 can be trained to determine the correlation / functional relationship between the electrical parameters of the semiconductor devices corresponding to the widths of different gate structures and the process parameters of the target semiconductor manufacturing process, that is, for a certain width of the gate structure, the electrical parameters of the transistors of the gate structure with this width are determined from the sample set, such as parameter values of voltage, current, etc., as well as the thickness value of the sidewall formed by the transistor in the horizontal direction and the process parameter values of the sidewall process when forming the sidewall, the ion doping concentration of the ion implantation regions formed in the substrates on both sides of the sidewall, and the process parameter values of the ion implantation process performed when forming the ion implantation regions. Then, based on the values determined above, the correlation between the multiple electrical parameters and the process parameters of the semiconductor manufacturing process executed by it at a certain width of the gate structure is obtained. Then, during the process of preparing the gate structure, for the actual width of the width of the gate structure formed on the substrate, by compensating the process parameters of the semiconductor manufacturing process to be performed on the semiconductor device subsequently, it can be achieved that even if the width of the gate structure of the semiconductor device has an error due to the fluctuations of the manufacturing process, its overall electrical characteristics and device performance are stable.

[0040] In the first optional example, if the semiconductor manufacturing process performed on the substrate having the gate structure formed thereon subsequently is the sidewall process, the process parameters of the sidewall process may include the thickness of the sidewall in the horizontal direction. Then, based on the above sample set, through multiple trainings, the correlation or functional relationship between the multiple electrical parameters of the CMOS transistor or MOS transistor and the sidewall thickness of the sidewall process at different widths in the horizontal direction of the gate structure can be determined. In other words, by training the actual data in the sample set, the changing trend (such as increasing or decreasing) of the multiple electrical parameters of the CMOS transistor or MOS transistor with the change of the sidewall thickness of the sidewall process at different widths in the horizontal direction of the gate structure can be obtained.

[0041] Specifically, the correlation between the multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor manufacturing process at different widths in the horizontal direction of the gate structure may be: at different widths in the horizontal direction of the gate structure, the changing trend of the on-current parameter with the process parameters of the sidewall process and the turn-on voltage parameter, or the drain-source cut-off current parameter. For example, as the thickness of the sidewall process gradually increases, the on-current parameter is inversely proportional to the turn-on voltage parameter and directly proportional to the drain-source cut-off current parameter, as Figure 2 shown, the Figure 2 is an example curve relationship diagram corresponding to the correlation between the multiple electrical parameters of the semiconductor device in an embodiment of the present invention and the process parameters of the target semiconductor manufacturing process at different widths in the horizontal direction of the gate structure; wherein, Figure 2 the black lines in represent the target values of the on-current parameter (Ion) and the turn-on voltage parameter (Vt) of the semiconductor device under the process parameters of different ion doping processes and sidewall processes.

[0042] In one embodiment, the sidewall process may specifically include: first, using a deposition process, such as at least one of physical vapor deposition process, chemical vapor deposition process, or atomic layer deposition process, to form a sidewall material layer covering the gate structure on the substrate, such as at least one of silicon nitride and silicon oxide, and then using an etching process, such as at least one of dry etching process or wet etching process, to selectively remove the sidewall material layer to form sidewalls with a target set thickness only on the two sidewalls of the gate structure.

[0043] In a second alternative example, if the semiconductor manufacturing process performed on the substrate with the gate structure formed thereon subsequently is the ion doping process, wherein the ion doping process may include pocket doping (also referred to as Pocket Implant Process) and / or lightly doped drain (also referred to as LDD Implant Process), and the process parameters of the ion doping process may specifically include the implantation dose and / or implantation depth of the doping ions, but are not limited thereto; then based on the above sample set, through multiple trainings, the correlation or functional relationship between multiple electrical parameters of the CMOS transistor or MOS transistor and the process parameters of the ion doping process at different widths in the horizontal direction of the gate structure can be determined; in other words, by training the actual data in the sample set, the change trend (such as increase or decrease) of the multiple electrical parameters of the CMOS transistor or MOS transistor with different doping concentrations / implantation doses of the ion doping process at different widths in the horizontal direction of the gate structure can be obtained.

[0044] Specifically, the correlation between multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor manufacturing process at different widths in the horizontal direction of the gate structure may be: at different widths in the horizontal direction of the gate structure, the change trend of the on-current parameter with the process parameters of the spacer process and the turn-on voltage parameter, or the leakage current parameter between the drain and source, for example, the on-current parameter is proportional to the leakage current parameter between the drain and source and inversely proportional to the turn-on voltage parameter as the implantation dose of the ion doping process gradually decreases or the implantation depth gradually increases, as Figure 3 shown, the Figure 3 is another example curve relationship diagram corresponding to the electrical model in an embodiment of the present invention. In one embodiment, the ion doping process may specifically include: after forming the gate structure, performing N-type or P-type ion implantation on the substrate on both sides of the gate structure to sequentially form corresponding pocket doping regions and / or lightly doped drain regions; wherein, Figure 3 the black lines in represent the target values of the on-current parameter (Ion) and the leakage current parameter between the drain and source (Ioff) of the semiconductor device under the process parameters of different ion doping processes and spacer processes.

[0045] In a third alternative example, if the semiconductor manufacturing process performed on the substrate on which the gate structure is formed subsequently includes both the ion doping process and the spacer process, then based on the above sample set, through multiple trainings, the association or functional relationship corresponding to the first example and the second example above can be integrated, for example, the result after convolution, as the final association or functional relationship between the multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor manufacturing process at the width in the horizontal direction of different gate structures. This will not be elaborated here.

[0046] In the above step S102, following the above step S101, a substrate can be provided. The substrate is any suitable substrate material well-known in the art. For example, it can be a silicon substrate, a silicon-containing substrate (such as SiC, SiGe), or a silicon-on-insulator substrate, or a substrate composed of other suitable materials, etc., but not limited thereto. In one embodiment, in step S102, one substrate can be provided, or multiple substrates can be provided. For example, multiple substrates included in a batch of wafers are provided. Then, using a deposition process, such as chemical vapor deposition, a gate material layer is formed on the one or more substrates. For example, crystalline silicon, poly silicon, amorphous silicon, doped silicon, SiGe, or other suitable semiconductor materials, but not limited thereto. Subsequently, using an etching process, such as dry etching, one or more discrete gate structures are correspondingly formed on the substrate.

[0047] In the above step S103, due to the errors in the process parameters and process equipment of the etching process and the deposition process, it is inevitable that the width of the gate structure formed in step S102 is different from its corresponding initial set width. Therefore, in the embodiment of the present invention, the actual width of each gate structure formed in step S102 in the horizontal direction (hereinafter simply referred to as the actual width of the gate structure) can be measured first. Then, the difference operation is performed on the actual width of the gate structure (for example, represented by A) and its corresponding initial set width (for example, represented by B) to obtain the width compensation value of each gate structure (for example, represented by C), then C = A - B. After that, based on the actual width of the gate structure, through the association between the multiple electrical parameters of the semiconductor device provided in the embodiment of the present invention and the process parameters of the target semiconductor manufacturing process at the width in the horizontal direction of different gate structures, the compensation value of the target semiconductor manufacturing process (referred to as the target semiconductor manufacturing process in the embodiment of the present invention) to be subsequently performed on the substrate including this gate structure is determined.

[0048] Specifically, first, use the correlation determined by training in step S101 to determine the target value corresponding to each electrical parameter of the semiconductor device including the gate structure at the actual width of the gate structure. Then, determine the target value of the process parameters of the target semiconductor manufacturing process to be performed on the semiconductor device including the gate structure. At this time, the target value of the process parameters of the target semiconductor manufacturing process to be performed is the optimal value to ensure the electrical performance of the semiconductor device. Then, perform a subtraction operation on the determined target value of the process parameters and its initial setting value, and use the result of the subtraction operation as the compensation value for the corresponding process parameter, that is, the initial setting value of the process parameters of the target semiconductor manufacturing process to be performed on the substrate including the gate structure is adjusted.

[0049] In an embodiment, if the target semiconductor manufacturing process is the sidewall process, the initial setting value range of the thickness of the sidewall in the horizontal direction can be: 50 nm to 100 nm, and the process parameter compensation value range of the thickness of the sidewall in the horizontal direction can be: 0 nm to 200 nm, that is, it can be 1 nm, 2 nm, 10 nm, 20 nm, 30 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc., but not limited thereto. Similarly, if the target semiconductor manufacturing process is the ion implantation process, the process parameter compensation value range of the implantation dose of the doped ions can be: 1E-16 to 1E-11, that is, it can be 1E-15, 1E-14, 1E-13, 1E-12, etc., and the process parameter compensation value range of the implantation depth of the doped ions can be: 2 KeV to 100 KeV, that is, it can be 2 KeV, 5 KeV, 10 KeV, 20 KeV, 30 KeV, 40 KeV, 50 KeV, 70 KeV, 80 KeV, 90 KeV, 100 KeV, etc.

[0050] In the above step S104, following the above step S103, after adjusting the initial setting value of the process parameters of the target semiconductor manufacturing process to be performed on the semiconductor device, based on the adjusted process parameters, perform the target semiconductor manufacturing process on the substrate formed with the gate structure, so as to realize compensating for the process parameters of the target semiconductor manufacturing process to be performed on the semiconductor device including the actual width of the gate structure, and achieve the purpose of automatically compensating for the fluctuation caused by the manufacturing process between the actual width and the initial setting width of the gate structure, that is, reducing the performance impact of the semiconductor device caused by process deviation, improving the process stability of the semiconductor manufacturing process, and improving the overall performance of the semiconductor device.

[0051] Meanwhile, when the widths of the gate structures formed on different substrates are different in the embodiments of the present invention, the process parameters of the corresponding target semiconductor manufacturing process are adjusted for each gate structure respectively. Furthermore, the present invention can also achieve mass production of automatic channel length compensation for semiconductor devices.

[0052] It should be understood that the horizontal direction mentioned in the embodiments of the present invention is the direction parallel to the surface of the substrate.

[0053] In summary, the present invention provides a method for manufacturing a semiconductor device, including: pre-establishing the correlation between multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor manufacturing process at different widths in the horizontal direction of different gate structures, providing a substrate with at least one gate structure formed thereon, measuring the actual width of the gate structure in the horizontal direction, and based on the correlation, determining the compensation value of the process parameters of the target semiconductor manufacturing process corresponding to the electrical parameters of the semiconductor device when the electrical parameters take target values at the actual width of the gate structure, and performing the target semiconductor manufacturing process on the substrate and / or the gate structure.

[0054] In the present invention, by establishing the functional relationship between different electrical parameters of the semiconductor device and the process parameters of the semiconductor manufacturing process at the width of the gate structure in the horizontal direction (hereinafter simply referred to as the width of the gate structure), the compensation value of the process parameters of the semiconductor manufacturing process to be performed on the semiconductor device is determined. The unexpected effect obtained is that for the actual width of the gate structure, by compensating the process parameters of the target semiconductor manufacturing process to be performed on the semiconductor device including the actual width of the gate structure, automatic compensation for the fluctuation caused by the manufacturing process and resulting in the difference between the actual width and the initial set width of the gate structure is achieved, the device performance of the semiconductor device is improved, and it is ensured that the channel lengths of different semiconductor devices corresponding to different annotated wafers or wafers of the same batch can meet the design requirements, that is, mass production of automatic channel length compensation for semiconductor devices is achieved, and the compensation efficiency is improved.

[0055] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising said element.

[0056] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other, and the key points of each embodiment are the differences from other embodiments. In particular, for the embodiments of the device, electronic device and computer-readable storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and for the relevant parts, reference can be made to the partial description of the method embodiments.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Including: Pre - establish the correlation between multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor manufacturing process at widths in the horizontal direction of different gate structures; Provide a substrate with at least one gate structure formed thereon; Measure the actual width of the gate structure in the horizontal direction, and based on the correlation, determine the compensation value of the process parameters of the target semiconductor manufacturing process corresponding to the target value of the electrical parameters of the semiconductor device at the actual width of the gate structure, where the compensation value is the difference between the initial setting value and the target value of the process parameter; Perform the target semiconductor manufacturing process on the substrate and / or the gate structure; Wherein, the target semiconductor manufacturing process includes a spacer process and an ion doping process, the process parameters of the spacer process include the thickness of the spacer in the horizontal direction, the ion doping process includes pocket doping and / or drain light doping, and the process parameters of the ion doping process include the implantation dose and / or implantation depth of the doping ions; The correlation between multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor manufacturing process at widths in the horizontal direction of different gate structures includes: at widths in the horizontal direction of different gate structures, the on - current parameter is inversely proportional to the threshold voltage parameter and directly proportional to the drain - source off - current parameter as the thickness of the spacer process gradually increases; and, The correlation between multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor manufacturing process at widths in the horizontal direction of different gate structures includes: at widths in the horizontal direction of different gate structures, the on - current parameter is directly proportional to the drain - source off - current parameter and inversely proportional to the threshold voltage parameter as the implantation dose of the ion doping process gradually decreases or the implantation depth gradually increases.

2. The manufacturing method of the semiconductor device as described in claim 1, characterized in that, The semiconductor device includes a MOS transistor or a CMOS transistor.

3. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The electrical parameters include an on - current parameter, a threshold voltage parameter, or a drain - source off - current parameter.

4. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The step of determining the compensation value of the process parameters of the target semiconductor manufacturing process corresponding to the target value of the electrical parameters of the semiconductor device at the actual width of the gate structure includes: Determine the target value of the electrical parameters of the semiconductor device at the actual width of the gate structure; Utilize the correlation between multiple electrical parameters of the semiconductor device and the process parameters of the target semiconductor manufacturing process at widths in the horizontal direction of different gate structures to determine the target value of the process parameters of the target semiconductor manufacturing process to be executed by the semiconductor device when the value of the electrical parameter is the target value; Perform a subtraction operation between the determined target value of the process parameter and its initial setting value, and use the result of the subtraction operation as the compensation value of the corresponding process parameter.

5. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The initial setting value range of the thickness of the spacer in the horizontal direction is: 50nm - 100nm, and the compensation value range of the process parameter of the thickness of the spacer in the horizontal direction is: 0nm - 200nm.

6. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The process parameter compensation value range of the implantation dose of the doped ions is: 1E-16~1E-11, and the process parameter compensation value range of the implantation depth of the doped ions is: 2KeV~100KeV.

7. The method for manufacturing a semiconductor device according to claim 6, wherein, The doped ions include N-type ions and / or P-type ions.

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