Semiconductor device including contact structures having different sizes

Abstract

There is provided a semiconductor device including: a first channel structure; a first source / drain region and a second source / drain region connected by a first channel structure in a first direction; a first gate structure on the first channel structure; a first contact structure on the first source / drain region and connecting the first source / drain region to a voltage source; and a second contact structure on the second source / drain region and connecting the second source / drain region to another circuit element different from the voltage source, in which a first contact area between the first contact structure and the first source / drain region is greater than a second contact area between the second contact structure and the second source / drain region.

Description

Technical Field

[0001] Apparatuses and methods consistent with the present disclosure relate to three-dimensional stacked (3D stacked) semiconductor devices, also referred to as multi-stacked semiconductor devices, in which a double contact structure is formed on a lower source / drain region. Background Art

[0002] In response to the increasing demand for integrated circuits with high device density and performance, 3D stacked semiconductor devices have been introduced. The 3D stacked semiconductor device may include a first transistor at a first level and a second transistor at a second level above the first level, wherein each of the transistors may be a fin field effect transistor (FinFET), a nanosheet transistor, a forkplate transistor, or any other type of transistor.

[0003] FinFET has one or more horizontally arranged vertical fin structures as channel structures, wherein at least three surfaces of each fin structure are surrounded by a gate structure, and nanosheet transistors are characterized by one or more nanosheet layers vertically stacked on a substrate as channel structures and a gate structure surrounding all four surfaces of each of the nanosheet layers. Nanosheet transistors are called gate all around (GAA) transistors or multi-bridge channel field effect transistors (MBCFETs). Forkplate transistors are a combination of two nanosheet transistors with an insulating backbone structure in between. The nanosheet layers of each nanosheet transistor are formed on each side of the insulating backbone structure and pass through the gate structure in parallel with the backbone structure.

[0004] A backside power distribution network (BSPDN) for semiconductor devices has been introduced to address the blocking of signal lines and power rails at the front side of the semiconductor device. The BSPDN may also help reduce the contact resistance between circuit elements formed at the front side of the semiconductor device. Here, the front side refers to the side where the transistor is formed relative to the top surface of the substrate, and the back side refers to the side opposite to the front side. The BSPDN is formed on the back side of the semiconductor device and may include a backside metal line (such as a buried power rail) and a backside contact structure formed on the bottom surface of the source / drain region of the field effect transistor, and the backside metal line may connect the backside contact structure to a voltage source or another circuit element for signal routing. The BSPDN may also be formed on the back side of a 3D stacked semiconductor device to connect the source / drain region of a second transistor at the second level and a first transistor at the first level to a voltage source.

[0005] In order to achieve improved device performance of semiconductor devices such as 3D stacked semiconductor devices, for example, it should be considered how to configure contact structures to be formed on source / drain regions of transistor structures included in the 3D stacked semiconductor devices. These contact structures are formed in a middle-of-line (MOL) process of manufacturing semiconductor devices, and therefore, in view of front-end process (FEOL) structures such as channel structures, source / drain regions, and gate structures, back-end process (BEOL) structures such as metal lines and via structures, and back-side power distribution network (BSPDN) structures including back-side metal lines, back-side contact structures, back-side power rails, etc., these contact structures may be referred to as MOL structures.

[0006] The information disclosed in this background technology section has been known or derived by the inventor before or during the process of implementing the embodiments of the present application, or is technical information acquired in the process of implementing the embodiments. Therefore, it may contain information that does not form prior art known to the public. Summary of the invention

[0007] According to an aspect of an example embodiment, a semiconductor device is provided, which may include: a first channel structure; a first source / drain region and a second source / drain region connected in a first direction by the first channel structure; a first gate structure on the first channel structure; a first contact structure on the first source / drain region and connecting the first source / drain region to a voltage source; and a second contact structure on the second source / drain region and connecting the second source / drain region to another circuit element different from the voltage source, wherein a first contact area between the first contact structure and the first source / drain region is greater than a second contact area between the second contact structure and the second source / drain region.

[0008] According to one aspect of an example embodiment, a semiconductor device is provided, which may include: a first channel structure; a first source / drain region and a second source / drain region connected in a first direction by the first channel structure; a first gate structure on the first channel structure; a first contact structure on the first source / drain region and connecting the first source / drain region to a voltage source; and a second contact structure on the second source / drain region and connecting the second source / drain region to another circuit element different from the voltage source, wherein a first contact length between the first contact structure and the first source / drain region in the first direction is greater than a second contact length between the second contact structure and the second source / drain region in the first direction.

[0009] According to one aspect of an example embodiment, a semiconductor device is provided, which may include: a first channel structure; a first source / drain region and a second source / drain region connected in a first direction by the first channel structure; a first gate structure on the first channel structure; a first contact structure on the first source / drain region and connecting the first source / drain region to a voltage source; and a second contact structure on the second source / drain region and connecting the second source / drain region to another circuit element different from the voltage source, wherein a first contact height between the first contact structure and the first source / drain region in a third direction is greater than a second contact height between the second contact structure and the second source / drain region in the third direction.

[0010] According to one aspect of an example embodiment, a method for manufacturing a semiconductor device is provided. The method may include: providing a transistor structure, the transistor structure including a channel structure, a gate structure on the channel structure, a first source / drain region, and a second source / drain region connected to the first source / drain region through the channel structure in a first direction; and forming a first contact structure and a second contact structure on the first source / drain region and the second source / drain region, respectively, so that the first contact structure on the first source / drain region has a larger contact area than the second contact structure on the second source / drain region, wherein the first source / drain region is connected to a voltage source through the first contact structure, and the second source / drain region is connected to a circuit element different from the voltage source. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figures 1A-1F A 3D stacked semiconductor device including contact structures having different contact areas on respective source / drain regions according to one or more embodiments is shown.

[0013] Figure 2 A 3D stacked semiconductor device including contact structures having different contact areas on respective source / drain regions according to one or more embodiments is shown.

[0014] Figure 3 A flow chart of a method of manufacturing a semiconductor device including contact structures having different contact areas on respective source / drain regions according to one or more embodiments is shown.

[0015] Figure 4is a schematic block diagram illustrating an electronic apparatus including a semiconductor device in which contact structures having different contact areas are formed on respective source / drain regions according to one or more embodiments. DETAILED DESCRIPTION

[0016] The embodiments of the present disclosure described herein are example embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms. Each of the embodiments provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure. For example, even if the matter described in a specific example or embodiment is not described in an example or embodiment different therefrom, the matter may also be understood to be related to or combined with the different example or embodiment, unless otherwise mentioned in its description. In addition, it should be understood that all descriptions of the principles, aspects, examples and embodiments of the present disclosure are intended to cover their structural and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents to be developed in the future, that is, all devices invented to perform the same function, regardless of their structure. For example, the channel layer, sacrificial layer and isolation layer described herein may be of different types or forms, as long as the present disclosure can be applied thereto.

[0017] It should be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as being "on," "over," "up," "under," "below," "connected to," or "coupled to" another element of the semiconductor device, it may be directly on, over, over, under, under, under, connected to, or coupled to the other element, or there may be intervening elements. In contrast, when an element of a semiconductor device is referred to as being "directly on," "directly over," "directly on," "directly under," "directly under," "directly under," "directly connected to," or "directly coupled to" another element of the semiconductor device, there are no intervening elements. Throughout this disclosure, the same reference numerals refer to the same elements.

[0018] Spatially relative terms, such as "above", "above", "upper", "below", "below", "below", "lower", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle", etc., may be used herein for ease of description to describe the relationship of one element to another element as shown in the figure. It will be understood that spatially relative terms are intended to cover different orientations of the semiconductor device in use or operation in addition to the orientation depicted in the figure. For example, if the semiconductor device in the figure is flipped, the element described as being "below" or "below" another element will be oriented as being "above" the other element. Therefore, the term "below" can cover both the above and below orientations. The semiconductor device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly. As another example, when a device or structure including elements referred to as "left" elements and "right" elements are oriented differently, these elements can be "right" elements and "left" elements. Therefore, in the following description, the "left" element and the "right" element may also be referred to as the "first" element or the "second" element, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms "lower" element and "upper" element may be referred to as the "first" element and the "second" element, respectively, with the necessary description to distinguish the two elements.

[0019] It should be understood that although the terms "first", "second", "third", "fourth", "fifth", "sixth", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, a first element discussed in the description of the embodiments may be referred to as a second element in the claims.

[0020] As used herein, expressions such as "at least one of," when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. In this document, when the term "same" is used to compare the size of two or more elements, the term can encompass "substantially the same" sizes.

[0021] It will also be understood that even if a step or operation of manufacturing a device or structure is described before another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation.

[0022] Many embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of the embodiments (and intermediate structures). Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments should not be interpreted as limited to the specific shapes of the regions shown herein, but rather include shape deviations caused by, for example, manufacturing. The various regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the present disclosure. In addition, in the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0023] For the sake of brevity, conventional elements, structures or layers of semiconductor devices including nanosheet transistors and the materials forming them may or may not be described in detail herein. For example, when a certain isolation layer or structure of a semiconductor device is not related to the novel features of an embodiment, a certain isolation layer or structure of a semiconductor device and the materials forming the isolation layer or structure may be omitted herein. In addition, when the materials forming the known structural elements of the semiconductor device are not related to the novel features of an embodiment, the description of these materials may be omitted herein. In this article, the term "isolation" refers to electrical insulation or separation between structures, layers, components or regions in the corresponding device or structure.

[0024] Hereinafter, various embodiments provide a contact structure of a semiconductor device to improve the performance of the semiconductor device.

[0025] With respect to the contact structure formed on the source / drain region of the semiconductor device, it may be necessary to reduce the contact resistance and capacitance for efficient power delivery to the source / drain region (source) and signal routing from and to the source / drain region (drain). However, reducing the contact resistance can usually be achieved at the expense of an increase in the contact capacitance in the semiconductor device. In other words, the two characteristics of the semiconductor device are in a trade-off relationship.

[0026] In order to improve or optimize device performance, the contact structure connected to the source / drain region of the semiconductor device can be formed to have different sizes, taking into account the location or purpose of forming the contact structure in the semiconductor device. For the contact structure that connects the source / drain region (source) to the voltage source VDD or VSS, the contact resistance has a greater sensitivity to device performance than the contact capacitance because the power delivery from the voltage source may be less related to the contact capacitance. Therefore, even if the capacitance may increase to a certain extent, reducing the contact resistance has a greater performance effect, for example, for reducing power consumption. In contrast, a contact structure that connects the source / drain region (drain) to another circuit element for signal routing purposes may cause a large crosstalk effect due to the continuous shaking of the AC signal. Therefore, even if the contact resistance may increase to a certain extent, reducing the capacitance has a greater impact on performance improvement. Therefore, a contact structure for delivering power to the source / drain region (source) may have a large contact area on the source / drain region (source) to reduce contact resistance, while a contact structure for connecting the source / drain region (drain) to another circuit element for signal routing purposes may have a small contact area on the source / drain region (drain) to reduce contact capacitance.

[0027] For a 3D stacked semiconductor device having a structure with greater complexity than a single stacked semiconductor device, more consideration may need to be given to contact resistance and capacitance.

[0028] Figures 1A-1F A 3D stacked semiconductor device including contact structures having different contact areas on respective source / drain regions according to one or more embodiments is shown.

[0029] Figure 1A is a plan view of a 3D stacked semiconductor device, and Figures 1B-1F It is taken along lines I-I', II-II', III-III', IV-IV' and V-V' respectively. Figure 1A 3D stacked semiconductor device 10 is shown in FIG. It should be understood that the Figure 1A To illustrate the positional relationship between selected structural elements of the 3D stacked semiconductor device 10, Figures 1B to 1F Some structural elements such as the substrate and isolation structures shown in FIG. Figure 1A Shown in.

[0030] like Figure 1A As shown in the figure, the D1 direction is the channel length direction in which the current flows between the two source / drain regions connected to each other by the channel structure, the D2 direction is the channel width direction intersecting the D1 direction, and the D3 direction is the vertical direction intersecting the D1 and D2 directions which are both horizontal directions.

[0031] refer to Figures 1A-1F , the 3D stacked semiconductor device 10 may include a plurality of nanosheet layers forming a first channel structure 110 at a first level above a backside isolation structure 141 and a plurality of nanosheet layers forming a second channel structure 120 at a second level above the first level. An intermediate isolation structure 115 may be formed between the first channel structure 110 and the second channel structure 120. When manufacturing the 3D stacked semiconductor device 10, the nanosheet layers of the channel structures 110 and 120 may have been epitaxially grown from a silicon substrate that is replaced by the backside isolation structure 141.

[0032] The first channel structure 110 may connect the first source / drain regions 135S and 135D to each other so that current flows between the first source / drain regions 135S and 135D under the control of the gate structure 125B surrounding the first channel structure 110. Similarly, the second channel structure 120 may connect the second source / drain regions 145S and 145D to each other so that current flows between the second source / drain regions 145S and 145D under the control of the gate structure 125B surrounding the second channel structure 120. The gate structures 125A and 125C formed on both sides of the gate structure 125B are passive gate structures in the 3D stacked semiconductor device 10 of this article.

[0033] The first source / drain regions 135S and 135D may be epitaxially grown from the first channel structure 110, and the second source / drain regions 145S and 145D may be epitaxially grown from the second channel structure 120. Therefore, in the 3D stacked semiconductor device 10, the first channel structure 110 together with the first source / drain regions 135S, 135D and the gate structure 125B may form a first transistor at a first level, which is a nanosheet transistor. In addition, the second channel structure 120 together with the second source / drain regions 145S, 145D and the gate structure 125B may form a second transistor at a second level, which is also a nanosheet transistor.

[0034] Herein, the first source / drain regions 135S and 135D can be used as the source and drain of the first transistor, respectively, and the second source / drain regions 145S and 145D can be used as the source and drain of the second transistor, respectively. A front side isolation structure 142 can be formed to surround each of the source / drain regions 135S, 135D, 145S, and 145D to isolate these semiconductor structures from each other and from other circuit elements.

[0035] The gate structure 125B may be a common gate structure shared by two transistors to form a complementary metal oxide semiconductor (CMOS) device structure such as an inverter circuit. However, the present disclosure is not limited thereto, and additional isolation may be formed to divide the gate structure 125B into two gate structures for the first transistor and the second transistor, respectively. The gate spacer 151 formed on the side surface of the gate structure 125A-125B may have been used to protect the dummy gate structure of polysilicon from the various processes in manufacturing the 3D stacked semiconductor device 10, and is retained after the dummy gate structure is replaced by the gate structure 125A-125C to prevent current from leaking therefrom to other circuit elements. The inner spacer 116 may be formed between the gate structures 125A-125B, surrounding the channel structures 110 and 120 and the source / drain regions 135S, 125D, 145S, and 125D to prevent current leakage therebetween.

[0036] The isolation structures 141 and 142 may each be made of, for example, SiO 2 , but not limited to this. Each semiconductor nanosheet layer forming the channel structures 110 and 120 may be formed of silicon (Si) or silicon germanium (SiGe). The first source / drain regions 135S, 135D and the second source / drain regions 145S, 145D may also be formed of Si or SiGe. However, when the first source / drain regions 135S and 135D are formed of Si and doped with n-type impurities such as phosphorus (P), arsenic (As), antimony (Sb), etc., the first transistor may be an n-type transistor. On the contrary, when the second source / drain regions 145S and 145D are formed of SiGe and doped with impurities such as boron (B), gallium (Ga), indium (In), etc., the second transistor may be a p-type transistor.

[0037] The gate structures 125A-125C may each include a gate dielectric layer and a conductor layer. The gate dielectric layer may include a high-k material such as, but not limited to, Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and / or a combination thereof, and the conductor layer may include a metal or a metal compound such as, but not limited to, Cu, Al, Ti, Ta, W, Co, TiN, WN, TiAl, TiAlN, TaN, TiC, TaC, TiAlC, TaCN, TaSiN, or a combination thereof. The inner spacer 116 may be formed of, but not limited to, silicon nitride (e.g., SiN, SiBCN, SiCN, SiOCN, etc.). The gate spacer 151 may be formed of silicon oxide or silicon nitride (e.g., SiO 2 , SiN, SiBCN, SiCN, SiOC, SiOCN, etc.), but is not limited thereto, and may be different from the material forming the inner spacer 116.

[0038] Meanwhile, the second channel structure 120 may be formed to have a smaller width in the D2 direction than the first channel structure 110. For example, although the left edge (or left side surface) of the second channel structure 120 is vertically aligned or coplanar with the left edge (or left side surface) of the first channel structure 110, the right edge (or right side surface) of the second channel structure 120 is not vertically aligned or coplanar with the right edge (or right side surface) of the first channel structure 110. Therefore, a non-overlapping region may be provided on the right side of the second channel structure 120 and above the first channel structure 110, where the second channel structure 120 does not vertically overlap with the first channel structure 110.

[0039] When the second channel structure 120 has a smaller width in the D2 direction than the first channel structure 110, each of the second source / drain regions 145S and 145D epitaxially grown from the second channel structure 120 may also have a smaller width in the D2 direction than each of the first source / drain regions 135S and 135D epitaxially grown from the first channel structure 110, respectively. For example, while the left edge of the second source / drain region 145D is vertically aligned or coplanar with the left edge of the first source / drain region 135D therebelow, the right edge of the second source / drain region 145D is not vertically aligned or coplanar with the right edge of the first source / drain region 135D. Therefore, a non-overlapping region may be provided on the right side of the second source / drain region 145D above the first source / drain region 135D, where the second source / drain region 145D does not vertically overlap with the first source / drain region 135D. The aforementioned width difference between the source / drain regions is provided to form a contact structure of the first source / drain region 135D on at least a portion of the top surface of the first source / drain region 135D through a non-overlapping region in a limited area, such as Figure 1F as shown in .

[0040] Each of the first source / drain regions 135S and 135D and the second source / drain regions 145S and 145D may have a contact structure formed thereon for connecting to a voltage source or another circuit element therethrough. The first source / drain region 135S may have a backside contact structure BCA formed on its bottom surface in the backside isolation structure 141. The backside contact structure BCA may connect the first source / drain region 135S to a negative voltage source VSS through a backside metal line BM1 formed in the backside isolation structure 141. The first source / drain region 135D may have a first contact structure CR formed on the right side portion of the top surface. The first contact structure CR may connect the first source / drain region 135D to the second source / drain region 145D above it through a second contact structure CA2 formed on the upper right portion of the second source / drain region 145D. The second source / drain region 145S may have a second contact structure CA1 formed on an upper left portion of the second source / drain region 145S. The second contact structure CA1 may connect the second source / drain region 145S to a positive voltage source VDD through a first front via RB, a second front via TB, and a backside metal line BM2.

[0041] A gate contact structure (not shown) may be formed on the gate structure 125 to receive a gate input signal through a metal line included in a back end of line (BEOL) layer.

[0042] In this document, a source / drain region connected to a voltage source means that the source / drain region is connected to the voltage source without passing through another source / drain region or a gate structure, and a source / drain region connected to another circuit element means that the source / drain region is connected to another circuit element such as another source / drain region without passing through a voltage source.

[0043] Each of the contact structures BCA, CR, CA1, CA2, vias RB and TB, and backside metal lines BM1 and BM2 may be formed of a metal or a metal compound such as Cu, W, Al, Ru, Mo, Co, and / or combinations thereof, but is not limited thereto.

[0044] At the same time, in order to further improve the performance of the 3D stacked semiconductor device 10, the second contact structure CA1 can be formed to have a large contact area on the second source / drain region 145S to reduce the contact resistance therebetween, and the second contact structure CA2 can be formed to have a small contact area on the second source / drain region 145D to reduce the contact capacitance therebetween.

[0045] For example, in the corresponding D1-D3 direction, the second contact structure CA1 may have a large contact length L1, a large contact width W1, and a large contact height H1 on the second source / drain region 145S, while the second contact structure CA1 may have a small contact length L2, a small contact width W2, and a small contact height H2 on the second source / drain region 145D. However, the present disclosure is not limited thereto. According to one or more other embodiments, the contact area difference may be achieved by only distinguishing one or two of the contact length, contact width, and contact height. In addition, a large contact area may be achieved by only increasing one or two of the contact length, contact width, and contact height, even if the other one or two is reduced. Similarly, a small contact area may be achieved by reducing one or two of the contact length, contact width, and contact height, even if the other one or two is increased.

[0046] The aforementioned contact area difference between the two second contact structures CA1 and CA2 is provided because the second contact structure CA1 is configured to receive power and deliver power from the voltage source VDD to the second source / drain region 145S, while the second contact structure CA2 is configured to send a routing signal to or receive a routing signal from another circuit element (such as the first source / drain region 135D of the first transistor at the first level).

[0047] As described above, when the second contact structure CA1 has a small contact resistance on the second source / drain region 145S, power delivery from the voltage source VDD to the second source / drain region 145S can be more effective and efficient. Therefore, due to the small contact resistance caused by the large contact area, power consumption at the second source / drain region 145S can be reduced. At this time, the increase in capacitance between the second contact structure CA1 and the second source / drain region 145S due to the large contact area may not affect the performance of the 3D stacked semiconductor device 10 as much as the small contact resistance contributes to the performance improvement in the 3D stacked semiconductor device 10.

[0048] On the contrary, the small contact capacitance caused by the small contact area between the second contact structure CA2 and the second source / drain region 145D can prevent the increase of the switching time of the AC signal transmitted to or received from the second source / drain region 145D, thereby reducing power consumption. At this time, the increase of the contact resistance between the second contact structure CA2 and the second source / drain region 145D due to the small contact area may not affect the performance of the 3D stacked semiconductor device 10 as much as the small contact capacitance contributes to the improvement of the performance of the 3D stacked semiconductor device 10.

[0049] In order to achieve a large contact area on the second source / drain region 145S and a small contact area on the second source / drain region 145D, the bottom surface of the second contact structure CA1 on the second source / drain region 145S may have a length L1 in the D1 direction, and the bottom surface of the second contact structure CA2 on the second source / drain region 145D may have a length L2 in the D1 direction that is smaller than the length L1, as shown in FIG. Figure 1B as shown in .

[0050] In addition, when the contact length L2 of the second contact structure CA2 on the second source / drain region 145D is formed to be smaller than the contact length L1 of the second contact structure CA1 on the second source / drain region 145S, the distance D2 between the second contact structure CA2 and the gate structure 125B may be greater than the distance D1 between the second contact structure CA1 and the gate structure 125B. Therefore, the fringe capacitance between the second contact structure CA2 and the gate structure 125B may be smaller than the fringe capacitance between the second contact structure CA1 and the gate structure 125B. Therefore, the device performance may be additionally improved by reducing the AC signal switching time, reducing power consumption, and reducing the influence on the gate threshold voltage of the gate structure 125B.

[0051] The second contact structures CA1 and CA2 may be formed by patterning the front side isolation structure 142 on the second source / drain regions 145S and 145D between the gate structures 125A-125C. The patterning may be performed by, for example, photolithography, masking, and etching (such as dry and / or wet etching) to expose the top surfaces of the second source / drain regions 145S and 145D by lengths L1 and L2, such as Figure 1B As shown in . Subsequently, a metal or metal compound (such as Cu, W, Al, Ru, Mo, Co and / or a combination thereof) may be deposited in the patterned front side isolation structure 142 by, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or a combination thereof, followed by planarization such as chemical mechanical polishing (CMP), but not limited thereto.

[0052] However, according to one or more embodiments, the second contact structure CA1 and the second contact structure CA2 may be formed in a self-aligned manner.

[0053] Figure 2 A 3D stacked semiconductor device including contact structures having different contact areas on respective source / drain regions according to one or more embodiments is shown.

[0054] refer to Figure 2 , the 3D stacked semiconductor device 20 may include Figures 1A-1FThe 3D stacked semiconductor device 10 includes the same structural elements as those included in the 3D stacked semiconductor device 10, except that second contact structures CA3 and CA4 may be formed in the front side isolation structure 242 based on additional gate spacers 152 on the side surfaces of the gate spacers 151. Hereinafter, although repeated description of the same structural elements is omitted herein, different aspects of the 3D stacked semiconductor device 20 are described in view of the 3D stacked semiconductor device 10.

[0055] exist Figures 1A-1F In the 3D stacked semiconductor device 10, the gate spacer 151 may be formed on the side surfaces of the gate structures 125A-125C and on the second source / drain regions 145S and 145D, and the front side isolation structure 142 may be formed between the gate spacers 151 on the second source / drain regions 145S and 145D. In addition, in the 3D stacked semiconductor device 10, the second contact structures CA1 and CA2 may be formed through the front side isolation structure 142 to contact the top surfaces of the second source / drain regions 145S and 145D, respectively. Therefore, the side surfaces of the second contact structures CA1 and CA2 may be surrounded by the front side isolation structure 142, and the contact lengths L1 and L2 of the second contact structures CA1 and CA2 on the second source / drain regions 145S and 145D may be respectively defined in the front side isolation structure 142.

[0056] In contrast, in Figure 2 In the 3D stacked semiconductor device 20, the additional gate spacer 152 may be formed along the side surfaces of the gate spacers 151 on the gate structures 125B and 125C and on the second source / drain regions 145S and 145D. The additional gate spacer 152 may contact the side surfaces of these gate spacers 151, and the bottom surface of the additional gate spacer 152 may contact the top surface of the second source / drain regions 145S and 145D. Here, the additional gate spacer 152 may be formed on the second source / drain regions 145S and 145D so that the contact length L3 of the second contact structure CA3 on the second source / drain region 145S is defined by the distance between the gate spacer 151 on the second source / drain region 145S and the additional gate spacer 152, and the contact length L4 of the second contact structure CA4 on the second source / drain region 145D is defined by the distance between the additional gate spacers 152 on the second source / drain region 145D.

[0057] Due to the additional gate spacer 152, the front side isolation structure 242 can be formed between the gate spacer 151 and the additional gate spacer 152 on the second source / drain region 145S and between the additional gate spacer 152 on the second source / drain region 145D. In addition, second contact structures CA3 and CA4 can be formed through the front side isolation structure 242 to contact the top surfaces of the second source / drain regions 145S and 145D, respectively, as shown in Figures 1A-1F However, in the 3D stacked semiconductor device 20, although the second contact structures CA3 and CA4 may be formed through the front side isolation structure 242, the lower edge portion of the second contact structure CA3 may contact the gate spacer 151 and the additional gate spacer 152 on the second source / drain region 145S without the front side isolation structure 242 therebetween, and the lower edge portion of the second contact structure CA4 may contact the additional gate spacer 152 on the second source / drain region 145D without the front side isolation structure 242 therebetween. Therefore, the contact lengths L3 and L4 of the second contact structures CA3 and CA4 on the second source / drain regions 145S and 145D may be defined by the gate spacer 151 and the additional gate spacer 152, respectively.

[0058] Here, due to the additional gate spacer 152 and the gate spacer 151, the front side isolation structure 242 may have been patterned in a self-aligned manner to provide corresponding contact holes to expose the corresponding contact areas including the contact lengths L3 and L4 on the second source / drain regions 145S and 145D. For example, chlorine trifluoride (ClF 3 ) and hydrogen (H 2 ) can be used as an etchant for reactive ion etching (RIE) to selectively etch silicon nitrides such as SiBCN from substrates such as SiO 2 Therefore, the front side isolation structure 242 can be removed around the lower edges of the gate spacers 151 and the additional gate spacers 152 on the second source / drain regions 145S and 145D, so that the lower edge portions of the second contact structures CA3 and CA4 can contact the gate spacers 151 and the additional gate spacers 152 on the second source / drain regions 145S and 145D as described above, without the front side isolation structure 242 therebetween.

[0059] Structurally, the 3D stacked semiconductor device 20 may still be characterized by the difference in contact areas of the second contact structures CA3 and CA4 on the second source / drain regions 145D and 145S, respectively. Figure 2As shown in , considering that the second contact structure CA3 connects the second source / drain region 145S to the voltage source VDD and the second contact structure CA4 connects the second source / drain region 145D to another circuit element (such as the first source / drain region 135D of the first transistor at the first level), the second contact structure CA3 on the second source / drain region 145S can have a larger area than the second contact structure CA4 on the second source / drain region 145D.

[0060] For example, a contact length L3 of a bottom surface of a second contact structure CA3 defined by the gate spacer 151 and the additional gate spacer 152 on the second source / drain region 145S may be greater than a contact length L4 of a bottom surface of a second contact structure CA4 defined by the additional gate spacer 152 on the second source / drain region 145D by a length of the additional gate spacer 152 in the D1 direction.

[0061] As in the 3D stacked semiconductor device 10, the contact area difference in the 3D stacked semiconductor device 20 can be achieved by considering that the contact resistance is the priority factor for the power delivery performance of the second contact structure CA3 to the second source / drain region 145S, and the contact capacitance is the priority factor for the signal routing performance of the second contact structure CA4 relative to the second source / drain region 145D. As previously described, the second contact structure CA3 configured to deliver power from the voltage source VDD to the second source / drain region 145S is less sensitive to the contact capacitance, while the second contact structure CA4 configured to receive a signal from the second source / drain region 145D or send a signal to the second source / drain region 145D for signal routing purposes rather than delivering power to the second source / drain region 145D is less sensitive to the contact resistance.

[0062] In addition, when the contact length L4 of the second contact structure CA4 on the second source / drain region 145D is formed to be smaller than the contact length L3 of the second contact structure CA3 on the second source / drain region 145S, the distance D4 between the second contact structure CA4 and the gate structure 125B may be greater than the distance D3 between the second contact structure CA3 and the gate structure 125B. Therefore, the fringe capacitance between the second contact structure CA4 and the gate structure 125B may be smaller than the fringe capacitance between the second contact structure CA3 and the gate structure 125B. Therefore, the device performance may be additionally improved by reducing the AC signal switching time, reducing power consumption, and reducing the influence on the gate threshold voltage of the gate structure 125B.

[0063] In the above-mentioned embodiments, the 3D stacked semiconductor devices 10 and 20 are described as being formed of nanosheet transistors. However, the present disclosure is not limited thereto, and according to one or more embodiments, at least one of the first transistor and the second transistor at the first level and the second level, respectively, in each of the 3D stacked semiconductor devices 10 and 20 may be formed of different types of transistors (such as FinFETs and forkplate transistors).

[0064] In addition, the first transistor and the second transistor are described as a p-type transistor and an n-type transistor. However, the present disclosure is not limited thereto, and according to one or more embodiments, each of the first transistor and the second transistor may be a p-type or an n-type.

[0065] It should also be understood that the above-mentioned embodiments of distinguishing contact structures by their purpose or function can be applied to a 3D stacked semiconductor device in which the width of the channel structure and the width of the source / drain region of a first transistor at a first level are the same or substantially the same as the width of the channel structure and the width of the source / drain region of a second transistor at a second level.

[0066] It should also be understood that the above-described embodiments of differentiating contact structures by their purpose or function may be applied to single-stack semiconductor devices.

[0067] Hereinafter, a method of manufacturing a semiconductor device corresponding to the 3D stacked semiconductor device 20 is provided.

[0068] Figure 3 A flow chart of a method of manufacturing a semiconductor device including contact structures having different contact areas on respective source / drain regions according to one or more embodiments is shown.

[0069] according to Figure 3 The flow chart of manufacturing a semiconductor device may correspond to Figures 1A-1F and Figure 2 The 3D stacked semiconductor device 10 or 20 shown in the figure, therefore, the materials and functions of the structural elements of the semiconductor device may be the same as the materials and functions of the above-mentioned 3D stacked semiconductor device 10 or 20, and therefore, repeated description thereof is omitted here.

[0070] In step S10 , a transistor structure may be provided, the transistor structure including a channel structure, three gate structures having gate spacers thereon, and first and second source / drain regions connected to a voltage source and another circuit element, respectively.

[0071] In the transistor structure provided in this step, the first and second source / drain regions can be formed by epitaxial growth from the channel structure, and the gate structure can be formed by replacing the dummy gate structure on the channel structure. Gate spacers can be formed on the corresponding side surfaces of the dummy gate structure to protect the dummy gate structure from various operations including forming the first source / drain region and the second source / drain region, and are retained after the dummy gate structure is replaced by the gate structure to at least prevent current leakage from the gate structure when the semiconductor device is completed and activated.

[0072] The channel structure may be formed of a plurality of nanosheet semiconductor layers to form the transistor structure as a nanosheet transistor or a forkplate transistor, or may be formed of one or more fin structures to form the transistor structure as a FinFET.

[0073] The first source / drain region may be configured to receive power from a voltage source, and the second source / drain region may be configured to receive an AC signal from or send an AC signal to another circuit element in or outside the semiconductor device.

[0074] In step S20 , an isolation structure may be formed to surround the transistor structure provided in the previous step, such that the isolation structure is formed on the first source / drain region and the second source / drain region.

[0075] An isolation structure may be formed to isolate the first source / drain region and the second source / drain region from each other and from other circuit elements. Formation of the isolation structure may be performed by, for example, PVD, CVD, PECVD, or a combination thereof, followed by planarization such as chemical mechanical polishing (CMP), but is not limited thereto.

[0076] In step S30 , the isolation structure may be patterned to provide first and second contact holes exposing portions of the first and second source / drain regions, such that the first contact hole exposes a larger contact area on the first source / drain region than the second contact hole on the second source / drain region.

[0077] Here, the isolation structure can be patterned based on a hard mask structure formed thereon so that the first contact hole exposes the first source / drain region with a first contact area, and the second contact hole exposes the second source / drain region with a second contact area. The first and second contact holes can be through holes, and the first contact area is larger than the second contact area. By controlling at least one of the contact length, contact width, and contact height formed by each of the first contact hole and the second contact hole, the first contact area can be larger than the second contact area. The patterning operation in this step can be performed by, for example, dry etching and / or wet etching.

[0078] In step S40, a first contact structure and a second contact structure may be formed through the first contact hole and the second contact hole in the isolation structure respectively, so that the first contact structure on the first source / drain region may have a larger contact area than the second contact structure on the second source / drain region.

[0079] When a first contact area on a first source / drain region is larger than a second contact area on a second source / drain region, a first contact structure connecting the first source / drain region to a voltage source may have a smaller contact resistance and a larger contact capacitance relative to the first source / drain region, while a second contact structure connecting the second source / drain region to another circuit element (such as another source / drain region or a gate structure) may have a smaller contact capacitance and a larger contact resistance relative to the second source / drain region.

[0080] Therefore, the semiconductor device manufactured through the above steps may have improved device performance in terms of power delivery and signal routing.

[0081] At the same time, before forming the isolation structure on the transistor structure in step S20, as an optional step S15, additional gate spacers may be formed on the side surfaces of two gate structures selected from the three gate structures. For example, by forming additional gate spacers on the side surfaces of two gate spacers on the second source / drain region or adjacent to the second source / drain region in this step, the isolation structure may be patterned in a self-aligned manner to form a second contact hole based on the additional gate spacers thereon, and to form a first contact hole based on the additional gate spacers and the gate spacers on the unselected gate structures.

[0082] Due to the additional gate spacer, the second contact hole can expose a second contact area on the second source / drain region that is smaller than the first contact area exposed by the first contact hole on the first source / drain region. Therefore, the additional gate spacer can help form the first and second contact structures with different contact areas on the first and second source / drain regions, respectively.

[0083] Figure 4 is a schematic block diagram showing an electronic device including a semiconductor device according to one or more embodiments, in which contact structures having different contact areas are formed on corresponding source / drain regions. The semiconductor device may be Figures 1A-1F and Figure 2 One of the 3D stacked semiconductor devices 10 and 20 shown in FIG. 1 or according to reference Figure 3 A method for fabricating a semiconductor device is described.

[0084] refer to Figure 4, the electronic device 1000 may include at least one processor 1100, a communication module 1200, an input / output module 1300, a storage device 1400, and a buffer random access memory (RAM) module 1500. According to an embodiment, the electronic device 1000 may be a mobile device such as a smart phone or a tablet computer, but is not limited thereto.

[0085] The processor 1100 may include a central processing unit (CPU), a graphics processing unit (GPU), and / or any other processor that controls the operation of the electronic device 1000. The communication module 1200 may be implemented to perform wireless or wired communication with an external device. The input / output module 1300 may include at least one of a touch sensor, a touch panel, a keyboard, a mouse, a proximity sensor, a microphone, etc. for receiving input and at least one of a display, a speaker, etc. for generating an output signal processed by the processor 1100. The storage device 1400 may be implemented to store user data, output signals, etc. input through the input / output module 1300. The storage device 1400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), a universal flash memory (UFS) device, etc.

[0086] The buffer RAM module 1500 may temporarily store data used for processing operations of the electronic device 1000. For example, the buffer RAM 1500 may include a volatile memory such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a low power double data rate (LPDDR) SDRAM, a graphics double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0087] Although not in Figure 4 Although not shown in FIG. 1 , the electronic device 1000 may further include at least one sensor, such as an image sensor.

[0088] At least one component in the electronic device 1000 may be formed based on a semiconductor device according to one or more embodiments, the semiconductor device including contact structures having different contact areas on corresponding source / drain regions.

[0089] The foregoing is a description of example embodiments and should not be construed as limiting the present disclosure. Although several example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the above-described embodiments without materially departing from the present disclosure.

Claims

1. A semiconductor device, comprising: a first channel structure; a first source / drain region and a second source / drain region connected in a first direction by the first channel structure; a first gate structure on the first channel structure; a first contact structure on the first source / drain region and connecting the first source / drain region to a voltage source; as well as a second contact structure on the second source / drain region and connecting the second source / drain region to another circuit element different from the voltage source, A first contact area between the first contact structure and the first source / drain region is greater than a second contact area between the second contact structure and the second source / drain region.

2. The semiconductor device according to claim 1 , wherein one or more of a first contact length in the first direction, a first contact width in the second direction, and a first contact height in the third direction between the first contact structure and the first source / drain region are respectively greater than one or more of a second contact length in the first direction, a second contact width in the second direction, and a second contact height in the third direction between the second contact structure and the second source / drain region. 3 . The semiconductor device according to claim 1 , wherein a first contact length between the first contact structure and the first source / drain region in the first direction is greater than a second contact length between the second contact structure and the second source / drain region in the first direction. 4 . The semiconductor device according to claim 3 , wherein an isolation structure is provided at a side surface of each of the first contact structure and the second contact structure. 5 . The semiconductor device of claim 3 , wherein at least one gate spacer is disposed to contact at least a portion of a side surface of each of the first contact structure and the second contact structure.

6. The semiconductor device according to claim 5, wherein the at least a portion of the side surface of each of the first contact structure and the second contact structure is a lower side surface of each of the first contact structure and the second contact structure close to each of the first source / drain region and the second source / drain region. 7 . The semiconductor device of claim 5 , wherein a length of the at least one gate spacer contacting the side surface of the first contact structure is smaller than a length of the at least one gate spacer contacting the side surface of the second contact structure.

8. The semiconductor device according to claim 3, further comprising: a second gate structure, on one side of the first gate structure in the first direction; a third gate structure on an opposite side of the first gate structure in the first direction; wherein the first contact length is defined by a distance between a gate spacer on a side surface of the second gate structure and an additional gate spacer on a gate spacer on a side surface of the first gate structure, and The second contact length is defined by a distance between an additional gate spacer on the gate spacer on the other side surface of the first gate structure and an additional gate spacer on the gate spacer on the side surface of the third gate structure. 9 . The semiconductor device of claim 1 , wherein a first distance between the first contact structure and the first gate structure is smaller than a second distance between the second contact structure and the first gate structure.

10. The semiconductor device according to claim 1, further comprising: a second channel structure; as well as a third source / drain region and a fourth source / drain region, respectively overlapping the first source / drain region and the second source / drain region in a third direction intersecting the first direction, and the third source / drain region and the fourth source / drain region are connected in the first direction through the second channel structure; A fourth contact structure is on the fourth source / drain region and connects the fourth source / drain region to the second source / drain region through the second contact structure.

11. The semiconductor device according to claim 10, further comprising: A third contact structure is on the third source / drain region and connects the third source / drain region to another voltage source.

12. A semiconductor device comprising: a first channel structure; a first source / drain region and a second source / drain region connected in a first direction by the first channel structure; a first gate structure on the first channel structure; a first contact structure on the first source / drain region and connecting the first source / drain region to a voltage source; as well as a second contact structure on the second source / drain region and connecting the second source / drain region to another circuit element different from the voltage source, A first contact length between the first contact structure and the first source / drain region in the first direction is greater than a second contact length between the second contact structure and the second source / drain region in the first direction. 13 . The semiconductor device of claim 12 , wherein a first distance between the first contact structure and the first gate structure is smaller than a second distance between the second contact structure and the first gate structure. 14 . The semiconductor device according to claim 12 , wherein an isolation structure is provided at a side surface of each of the first contact structure and the second contact structure. 15 . The semiconductor device of claim 12 , wherein at least one gate spacer is disposed to contact at least a portion of a side surface of each of the first contact structure and the second contact structure.

16. The semiconductor device according to claim 12, further comprising: a second channel structure; as well as a third source / drain region and a fourth source / drain region, respectively overlapping the first source / drain region and the second source / drain region in a third direction intersecting the first direction, and the third source / drain region and the fourth source / drain region are connected in the first direction through the second channel structure; A fourth contact structure is on the fourth source / drain region and connects the fourth source / drain region to the second source / drain region through the second contact structure.

17. A semiconductor device comprising: a first channel structure; a first source / drain region and a second source / drain region connected in a first direction by the first channel structure; a first gate structure on the first channel structure; a first contact structure on the first source / drain region and connecting the first source / drain region to a voltage source; as well as a second contact structure on the second source / drain region and connecting the second source / drain region to another circuit element different from the voltage source, A first contact height between the first contact structure and the first source / drain region in the third direction is greater than a second contact height between the second contact structure and the second source / drain region in the third direction. 18 . The semiconductor device of claim 17 , wherein a first distance between the first contact structure and the first gate structure is smaller than a second distance between the second contact structure and the first gate structure. 19 . The semiconductor device according to claim 17 , wherein an isolation structure is provided at a side surface of each of the first contact structure and the second contact structure.

20. A method for manufacturing a semiconductor device, the method comprising: Providing a transistor structure, the transistor structure comprising a channel structure, a gate structure on the channel structure, a first source / drain region, and a second source / drain region connected to the first source / drain region through the channel structure in a first direction; as well as forming a first contact structure and a second contact structure on the first source / drain region and the second source / drain region, respectively, so that the first contact structure on the first source / drain region has a larger contact area than the second contact structure on the second source / drain region, The first source / drain region is connected to a voltage source through the first contact structure, and the second source / drain region is connected to a circuit element different from the voltage source.

21. The method of claim 20, wherein the gate structure comprises a gate spacer on a side surface thereof, wherein providing the transistor structure includes forming an additional gate spacer on the gate spacer, and The forming of the first contact structure and the second contact structure is performed based on the gate spacer and the additional gate spacer.

22. The method according to claim 20, wherein the gate structure comprises a first gate structure, a second gate structure, and a third gate structure respectively having gate spacers on side surfaces thereof, wherein providing the transistor structure includes forming additional gate spacers on the side surfaces of the second gate structure and the third gate structure, wherein forming the first contact structure is performed based on the gate spacer on the side surface of the first gate structure and the additional gate spacer on the gate spacer on one side surface of the second gate structure, The forming of the second contact structure is performed based on the additional gate spacer on the gate spacer on the other side surface of the second gate structure and the additional gate spacer on the gate spacer on the side surface of the third gate structure.

23. The method according to claim 20, wherein the first contact structure and the second contact structure are formed on the first source / drain region and the second source / drain region, respectively, so that the first contact structure on the first source / drain region has a larger contact length in the first direction than the second contact structure on the second source / drain region.

24. The method according to claim 20, wherein the first contact structure and the second contact structure are formed on the first source / drain region and the second source / drain region, respectively, so that a first distance between the first contact structure and the gate structure is smaller than a second distance between the second contact structure and the gate structure.

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