Integrated structure based on multi-material composite substrate structure and manufacturing method thereof

Abstract

The invention provides an integrated structure constructed based on a multi-material composite substrate and a manufacturing method of the integrated structure. In the device, a multi-layer structure is arranged on the multi-material composite substrate in an epitaxial manner; the multi-layer structure comprises a buffer layer, a high-resistance layer and a channel layer which are stacked; the plurality of p-type regions are arranged in the region of the channel layer at intervals; the barrier layer is arranged on the channel layer in an epitaxial manner, and two-dimensional electron gas is formed at an interface; the trench isolation region penetrates downwards into the multi-material composite substrate from the top of the barrier layer; the first channel downwards penetrates into the buffer layer from the top of the barrier layer; the second channel downwards penetrates into the channel layer from the top of the barrier layer and is in contact with the p-type region; and the passivation dielectric layer is deposited on the surface of the barrier layer, is filled in the trench isolation region and covers the inner wall sides of the first channel and the second channel. The integrated structure can effectively solve a series of problems of floating body effect, self-heating effect, hot carrier effect, short channel effect, latch-up effect of bulk silicon devices, power consumption, parasitic resistance and capacitance increase in the prior art.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an integrated structure based on a multi-material composite substrate and a manufacturing method thereof. Background Art

[0002] The semiconductor integrated circuit industry has entered the nanometer (nm) era. As the feature size of integrated circuits is gradually reduced to the sub-nanometer (100 nm) range, a series of new problems have emerged in the materials, device structure, process and reliability of bulk silicon integrated circuits. These problems mainly include: (1) The parasitic thyristor latch-up effect of bulk silicon CMOS circuits and the soft failure effect of bulk silicon devices in cosmic ray irradiation environments reduce the reliability of the circuits; (2) As the device size decreases, various multidimensional and nonlinear effects of bulk silicon CMOS devices, such as surface energy level quantization effect, tunneling effect, short channel effect, narrow channel effect, drain induced barrier lowering effect, hot carrier effect, subthreshold conductivity effect, velocity saturation effect, velocity overshoot effect, etc., become very significant, affecting the further improvement of device performance; (3) The chip area occupied by the isolation region between devices increases relatively with the decrease of device size, which increases the parasitic capacitance and lengthens the interconnection lines, affecting the improvement of integration and speed.

[0003] At the same time, with the development trend of increasing chip integration and miniaturization, chip functions and performance have been further upgraded and enhanced, but the chip power consumption and heat generation have also increased, bringing increasingly serious power consumption and heat dissipation problems.

[0004] The adverse effects of excessive heat include performance degradation, reduced reliability, safety hazards, energy waste, etc. Therefore, as the integration of chips increases, the heat dissipation problem becomes more important.

[0005] In addition, Si materials are limited by their own material properties, and silicon-based semiconductors are not suitable for use in high-frequency and high-power fields. In the future, the development of integrated circuits towards high voltage, high frequency, high temperature and high power density is an inevitable trend. Based on this, the present invention provides a new integrated structure based on a multi-material composite substrate structure and a manufacturing method thereof. Summary of the invention

[0006] Based on the above description, the present invention provides an integrated structure based on a multi-material composite substrate and a manufacturing method thereof to solve a series of problems existing in the prior art in integrated circuits, such as floating body effect, self-heating effect, hot carrier effect, short channel effect, latch-up effect of bulk silicon devices, power consumption, increased parasitic resistance and capacitance.

[0007] The technical solution of the present invention to solve the above technical problems is as follows: In a first aspect, the present invention provides an integrated structure based on a multi-material composite substrate, comprising: a multi-material composite substrate, a multi-layer structure, a barrier layer, a trench isolation region, a first channel, a second channel, a passivation dielectric layer, a source electrode, a drain electrode, and a gate electrode; The multi-layer structure is epitaxially arranged on the multi-material composite substrate; The multilayer structure comprises a buffer layer, a high resistance layer and a channel layer which are sequentially stacked from bottom to top; a plurality of p-type regions are spaced in the region of the channel layer; The barrier layer is epitaxially arranged on the channel layer, and a two-dimensional electron gas is formed at the interface; the trench isolation region penetrates from the top of the barrier layer downward to the middle area of ​​the multi-material composite substrate, and is used to isolate different devices; the first channel penetrates from the top of the barrier layer downward to the buffer layer, and is used for electrode grounding lead-out; the second channel penetrates from the top of the barrier layer downward to the channel layer, and contacts the p-type region, and is used for electrode lead-out of the donor PN diode; The passivation dielectric layer is deposited on the surface of the barrier layer, filled in the trench isolation region, and covers the inner wall sides of the first channel and the second channel; The source electrode, the drain electrode and the gate electrode are respectively arranged in the passivation dielectric layer, wherein the drain electrode is located at the top of the second channel and contacts with the electrode of the body PN diode.

[0008] Based on the above technical solution, the present invention can also be improved as follows.

[0009] Furthermore, the multi-material composite substrate includes a Si substrate, a 3C-SiC epitaxial layer and a SiC isolation layer; The 3C-SiC epitaxial layer is epitaxially arranged on the Si substrate; The SiC isolation layer is bonded on the 3C-SiC epitaxial layer, and a bonding interface layer is formed between the SiC isolation layer and the 3C-SiC epitaxial layer.

[0010] Furthermore, the SiC isolation layer is a high-purity semi-insulating SiC film, or a composite layer of a p-type SiC layer and a high-purity semi-insulating SiC film.

[0011] Furthermore, in the multilayer structure, the buffer layer, the high resistance layer and the channel layer are all made of III-V compound semiconductor materials.

[0012] Furthermore, the III-V compound semiconductor material is a heterojunction composed of one or at least two of GaN, GaAs, InP, Ga2O3, and AlGaN.

[0013] Further, a nucleation layer is provided at the bottom of the buffer layer.

[0014] Further, the buffer layer is a Ga2O3 buffer layer; the high-resistance layer is a high-resistance Ga2O3 layer; the channel layer is an unintentionally doped Ga2O3 channel layer; the barrier layer is an (Al x Ga 1-x )2O3 barrier layer, where 0 < x < 1, and the p-type region is a high-resistance quasi-p-Ga2O3 region; Or, the nucleation layer is an AlN nucleation layer; the buffer layer is a GaN buffer layer; the high-resistance layer is a high-resistance GaN layer; the channel layer is a GaN channel layer; the barrier layer is an AlGaN barrier layer, and the p-type region is a p-GaN region.

[0015] Further, the integrated structure further includes a p-type layer; The p-type layer is disposed at the bottom of the gate and is located in the passivation dielectric layer.

[0016] Further, the integrated structure further includes a metal connection layer; A plurality of the metal connection layers are respectively disposed at intervals on the top of the passivation dielectric layer and are respectively used for external connection to form a chip interconnection structure.

[0017] In a second aspect, the present invention further provides a manufacturing method for manufacturing an integrated structure based on a multi-material composite substrate structure as described in the first aspect, including: Growing and depositing a layer of 3C-SiC epitaxial layer on a Si substrate to obtain a 3C-SiC / Si substrate; Bonding an SiC thin film to the 3C-SiC / Si substrate to obtain an SiC / 3C-SiC / Si substrate; Growing a multi-layer structure on the SiC / 3C-SiC / Si substrate by metal-organic chemical vapor deposition or hydride vapor epitaxy; the multi-layer structure includes a buffer layer, a high-resistance layer, and a channel layer sequentially stacked from bottom to top; Epitaxially growing a barrier layer on the channel layer; Performing etching on the substrate at different depths to form through holes with different depths; etching the channels inside the 3C-SiC epitaxial layer as the trench isolation region between devices; etching the channels inside the buffer layer for electrode grounding lead-out; etching the channels to the high-resistance layer for electrode lead-out of the body PN diode; Depositing a layer of p-type doped III-V material on the surface, or a layer of undoped III-V material and then performing p-type ion implantation and annealing activation on it to form a p-type material, and selectively etching the p-type material to form p-type layers distributed at intervals; Depositing, partially etching and partially filling a passivation dielectric layer, the inside of the grounding channel is covered with a passivation dielectric layer, and the dielectric layer at the bottom of the grounding channel is etched to expose the buffer layer; covering the surface of the barrier layer with a dielectric layer, and the dielectric opening of the electrode channel; filling the channel in the trench isolation area with dielectric material; Depositing metal and patterning it, performing an ohmic annealing process to form a source electrode, a drain electrode, and an electrode lead-out and electrode preparation of a body PN diode at the formed dielectric opening, and forming a gate at the p-type layer; Deposit the passivation dielectric layer again, etch and flatten it locally, and complete the PAD electrode opening and ground channel opening; Deposit and pattern PAD metal, fill the ground via metal, and complete the multi-layer metal layer interconnection of the chip.

[0018] Compared with the prior art, the technical solution of this application has the following beneficial technical effects: The integrated structure based on the multi-material composite substrate structure and the manufacturing method thereof provided by the present invention have the following beneficial effects compared with the prior art: When the substrate of the prior art is Si, the integrated structure can effectively solve a series of problems existing therein, such as hot carrier effect, short channel effect, latch effect of bulk silicon device, power consumption, parasitic resistance and capacitance increase; when the substrate of the prior art is SOI, it can effectively solve a series of problems existing in the prior art, such as floating body effect, self-heating effect, parasitic resistance and capacitance increase; realize heterogeneous integration with compound semiconductors, and then realize high-performance and high-integration high-frequency and high-voltage integrated chips, specifically: (1) The multi-material composite substrate contains high thermal conductivity 3C-SiC, which can be used as a high heat dissipation layer for integrated circuits; the 3C-SiC layer is obtained by epitaxy based on a Si substrate, and belongs to the cubic crystal system with Si, so the process is feasible. It combines the advantages of Si's large size and low cost with the advantages of the wide bandgap semiconductor 3C-SiC.

[0019] (2) A layer of semi-insulating SiC film - SiC isolation layer - is bonded to a multi-material composite substrate, which can effectively achieve isolation between high-frequency and high-voltage chip structures. Semi-insulating SiC and 3C-SiC belong to the same silicon carbide system, and homogeneous bonding makes it easier to achieve a high-quality bonding interface without affecting the performance of the bonding material.

[0020] (3) Compared with directly bonding or epitaxially growing III-V materials on Si, heterojunction or heteroepitaxial growth of III-V compound semiconductor materials on semi-insulating SiC films makes it easier to obtain III-V semiconductor epitaxial layers with good crystal quality, which is beneficial for the preparation of high-performance materials.

[0021] (4) Using a III-V material buffer layer of average crystal quality as a ground potential layer can improve the floating body phenomenon of integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic structural diagram of an integrated structure based on a multi-material composite substrate structure provided in Example 1 of the present invention; Figure 2 A schematic structural diagram of a multi-material composite substrate in an integrated structure based on a multi-material composite substrate structure provided in Example 1 of the present invention; Figure 3 A schematic structural diagram of an integrated structure based on a multi-material composite substrate structure provided in Example 2 of the present invention; Figure 4 A schematic structural diagram of an integrated structure based on a multi-material composite substrate structure provided in Example 3 of the present invention; Figure 5 A schematic structural diagram of an integrated structure based on a multi-material composite substrate structure provided in Example 4 of the present invention; Figures 6 to 13 A schematic diagram of each step of the manufacturing process of an integrated structure based on a multi-material composite substrate structure provided in Example 5 of the present invention; Fig.14 A specific method diagram of bonding a SiC film to a 3C-SiC / Si substrate in step S2 of the manufacturing process of an integrated structure based on a multi-material composite substrate structure provided in Example 5 of the present invention; In the accompanying drawings, the components represented by the reference numerals are listed as follows: 1. Multi-material composite substrate; 101. Si substrate; 102. 3C-SiC epitaxial layer; 103. SiC isolation layer; 2. Multilayer structure; 201. Buffer layer; 202. High resistance layer; 203. Channel layer; 204. Nucleation layer; 3. Barrier layer; 4. Trench isolation area; 5. p-type region; 6. Passivation dielectric layer; 7. p-type layer; 8. Source; 9. Drain; 10. Gate. DETAILED DESCRIPTION

[0023] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0024] Regarding a series of problems in bulk silicon integrated circuits, such as hot carrier effect, short channel effect, latch-up effect of bulk silicon devices, power consumption, parasitic resistance, increased capacitance, etc., although process technologies such as deep trench isolation, electron beam etching, silicide, and intermediate bandgap gate electrode can reduce such effects, as long as the PN junction exists, there will be a depletion region, and as long as there is a Well, there will be substrate leakage, so it cannot be solved at all.

[0025] However, the silicon on insulator (SOI) technology has effectively overcome the shortage of bulk silicon materials with its unique material structure. By forming a semiconductor film on an insulator, the dielectric isolation of components in the integrated circuit can be achieved, giving full play to the advantages of bulk silicon integrated circuit technology, especially in improving switching speed and reducing parasitic effects. The earliest predecessor of SOI should be SOS (Silicon on Sapphire), which was gradually replaced by SOI. SOI technology is gradually becoming the mainstream technology for manufacturing high-integration, high-speed, low-power, and high-reliability ultra-large-scale integrated circuits.

[0026] However, SOI also has its inherent parasitic characteristics. The most typical one is the kink-effect, also known as the floating-body effect. Because the wells of SOI are all floating in the substrate, their wells are not connected to voltage. When the reverse-biased pn junction of the drain flows through current, the potential of the silicon epitaxial layer will increase, thereby increasing the channel conductance. Therefore, as the drain voltage increases, the drain current also increases, forming a non-saturated characteristic, thereby reducing the drain breakdown voltage performance; and the floating body effect will lead to a series of problems such as floating threshold voltage, memory effect, hysteresis effect, etc. Of course, substrate access will solve this problem, but it will increase the area and increase the body resistance.

[0027] Secondly, there is the self-heating effect. Since the bottom and the periphery are isolated by oxide, and the thermal conductivity of oxide is poor, the heat generated by the collision of carriers is accumulated in the well, which will reduce the carrier lifetime.

[0028] In addition, since SOI has silicon material on top, when some third- and fourth-generation compound semiconductor materials need to be integrated to improve chip performance, reliability, and / or reduce circuit size, other problems are often introduced due to the large mismatch between Si and other materials, limiting the further development of integrated circuits.

[0029] In summary, there are many problems in the prior art. First, in order to achieve device isolation on integrated circuits and solve a series of problems such as hot carrier effect, short channel effect, latch effect, power consumption, parasitic resistance, and capacitance increase of bulk silicon integrated circuits, it is best to use a substrate containing an insulating layer, which is conducive to the realization of various isolation schemes. At the same time, the substrate has the advantages of low resistance and low cost. The current mainstream technology SOI substrate is constructed in this way, but SOI technology still has some shortcomings.

[0030] Second: Using a substrate containing an insulating layer as the integrated substrate, the surrounding area is isolated, resulting in a floating body effect. The substrate needs to be grounded, but the area will be sacrificed.

[0031] 3. Currently, integrated circuits are developing towards high voltage, high temperature and high power density. As the integration of chips increases, it is necessary to improve their heat dissipation performance. The dielectric isolation layer of SOI is silicon dioxide (SiO2), which has poor thermal conductivity and has a self-heating effect.

[0032] 4. Si has large lattice mismatch and thermal mismatch with most compound semiconductors. When integrated circuits need to integrate compound semiconductor devices such as InP-based devices, SiC electronic devices, and GaN-based devices, there is still no optimal solution. Whether it is using heteroepitaxial growth or bonding to heterogeneously integrate compound semiconductor materials on Si, there are some problems.

[0033] Based on this, the present invention provides a new integrated structure based on a multi-material composite substrate.

[0034] The following embodiments of the present invention are further described in detail in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention but cannot be used to limit the scope of the present invention.

[0035] It should be noted that the terms "first" and "second" and the like in the specification, claims and drawings of this application are used to distinguish different objects rather than to limit a specific order.

[0036] Example 1 like Figure 1 As shown, this embodiment provides an integrated structure based on a multi-material composite substrate 1, such as Figure 1 As shown, it includes: a multi-material composite substrate 1, a multi-layer structure 2, a barrier layer 3, a trench isolation region 4, a first channel, a second channel, a passivation dielectric layer 6, a source 8, a drain 9 and a gate 10.

[0037] The multi-layer structure 2 is epitaxially disposed on the multi-material composite substrate 1 .

[0038] The multilayer structure 2 includes a buffer layer 201 , a high resistance layer 202 and a channel layer 203 which are sequentially stacked from bottom to top; a plurality of p-type regions 5 are spaced apart in the region of the channel layer 203 .

[0039] The barrier layer 3 is epitaxially arranged on the channel layer 203, and a two-dimensional electron gas is formed at the interface; the trench isolation region 4 penetrates downward from the top of the barrier layer 3 to the middle area of ​​the multi-material composite substrate 1, and is used to isolate different devices; the first channel penetrates downward from the top of the barrier layer 3 to the buffer layer 201, and is used for electrode grounding lead-out; the second channel penetrates downward from the top of the barrier layer 3 to the channel layer 203 and contacts with the p-type region 5, and is used for electrode lead-out of the donor PN diode.

[0040] The passivation dielectric layer 6 is deposited on the surface of the barrier layer 3 , filled in the trench isolation region 4 , and covers the inner wall sides of the first channel and the second channel.

[0041] The source 8, the drain 9 and the gate 10 are respectively arranged in the passivation dielectric layer 6, wherein the drain 9 is located at the top of the second channel and contacts the electrode of the body PN diode.

[0042] Among them, Figure 2 As shown, the multi-material composite substrate 1 includes a Si substrate 101 , a 3C—SiC epitaxial layer 102 and a SiC isolation layer 103 .

[0043] The 3C—SiC epitaxial layer 102 is epitaxially disposed on the Si substrate 101 .

[0044] 3C-SiC has high thermal conductivity and is used as a high heat dissipation layer for integrated circuits. 3C-SiC can be grown at a temperature below 1300° C. and belongs to the same cubic crystal system as Si. Therefore, the 3C-SiC epitaxial layer 102 can be grown on Si while ensuring good crystal quality.

[0045] The SiC isolation layer 103 is bonded on the 3C—SiC epitaxial layer 102 , and a bonding interface layer is formed between the SiC isolation layer 103 and the 3C—SiC epitaxial layer 102 .

[0046] The SiC isolation layer 103 is a high-purity (HPSI, High-purity semi-insulating) semi-insulating SiC film. This layer, as an isolation layer, can achieve isolation between high-frequency and high-voltage chip structures; HPSI-SiC usually uses 4H-SiC, which is the same silicon carbide material as the lower layer 3C-SiC, with a small mismatch. Homogeneous bonding can simplify the bonding difficulty and improve the bonding strength.

[0047] In the multilayer structure 2 , the buffer layer 201 , the high resistance layer 202 and the channel layer 203 are all made of III-V compound semiconductor materials.

[0048] Preferably, the III-V compound semiconductor material is a heterojunction composed of one or at least two of GaN, GaAs, InP, Ga2O3, and AlGaN. As a device region, high-frequency, high-voltage, optoelectronic, and other devices can be fabricated.

[0049] In this specific example, as Figure 1 shown, the buffer layer 201 is a Ga2O3 buffer layer 201; the high-resistance layer 202 is a high-resistance Ga2O3 layer; the channel layer 203 is an unintentionally doped Ga2O3 channel layer 203; the barrier layer 3 is an (Al x Ga 1-x )2O3 barrier layer 3, where 0 < x < 1; the p-type region 5 is a high-resistance quasi-p-Ga2O3 region.

[0050] Specifically, SiC has good compatibility with III-V materials. Whether it is epitaxy or bonding, better-quality materials can be obtained; the buffer layer 201 at the bottom of the III-V material can be connected to a potential and used as a device ground layer.

[0051] As Figure 1 shown, the integrated structure further includes a p-type layer 7; the p-type layer 7 is disposed at the bottom of the gate 10 and is located in the passivation dielectric layer 6.

[0052] Furthermore, the integrated structure further includes metal connection layers; a plurality of metal connection layers are respectively disposed at intervals on the top of the passivation dielectric layer 6 and are respectively used for external connection to form a chip interconnection structure.

[0053] Specifically, as Figure 1 shown, based on the multi-material composite substrate 1, a high-performance integrated circuit with good heat dissipation performance, an effective isolation solution, improved floating body effect, and hetero-integrated compound semiconductor materials can be constructed.

[0054] In this example, the III-V material is gallium oxide Ga2O3 and an (Al x Ga 1-x )2O3 / Ga2O3 heterojunction. The buffer layer 201 can be intentionally or unintentionally doped to have a certain electrical property. The buffer layer 201 is grounded, and the device can be connected to the buffer layer 201 to avoid device floating. HPSI-SiC also belongs to compound semiconductors. Whether it is epitaxy or bonding, the III-V materials on it can ensure good crystal quality.

[0055] Example 2 Based on Example 1, the difference from Example 1 is that: In this embodiment, as Figure 3 shown, in the integrated structure constructed based on the multi-material composite substrate, a nucleation layer 204 is provided at the bottom of the buffer layer 201.

[0056] The nucleation layer 204 is an AlN nucleation layer; the buffer layer 201 is a GaN buffer layer; the high resistance layer 202 is a high resistance GaN layer; the channel layer 203 is a GaN channel layer; the barrier layer 3 is an AlGaN barrier layer; and the p-type region 5 is a p-GaN region.

[0057] Specifically, the integrated structure can be prepared based on GaN materials. The multilayer structure of III-V materials includes an AlN nucleation layer, which is conducive to the nucleation and growth of GaN during subsequent heteroepitaxial GaN; an unintentionally doped GaN buffer layer, which is usually n-type and serves as a ground potential layer; a high-resistance GaN layer, which limits the flow of carriers in the channel layer and improves the device's gate control capability; an n-type doped GaN channel layer, which provides a channel for carrier transport; and an AlGaN barrier layer, which can form a polarization effect with GaN to produce a two-dimensional electron gas (2DEG).

[0058] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0059] Example 3 Based on Example 1, the difference from Example 1 is that: In this embodiment, if Figure 4 As shown, the bottom layer of the multi-material composite substrate can be a 3C-SiC polycrystalline substrate, that is, a 3C-SiC polycrystalline substrate is used to replace the above-mentioned 3C-SiC / Si substrate to form a multi-material composite substrate. The polycrystalline 3C-SiC substrate is cheap and has high mechanical strength.

[0060] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0061] Example 4 Based on Example 1, the difference from Example 1 is that: like Figure 5 As shown, the HPSI type high-purity semi-insulating SiC film of the SiC isolation layer in the multi-material composite substrate may include a p-type SiC layer, that is, a stacked composite layer of the p-type SiC layer and the high-purity semi-insulating SiC film.

[0062] For the rest of the same structures, please refer to the introduction of Example 1 and will not be repeated here.

[0063] Example 5 This embodiment provides a method for manufacturing an integrated structure based on a multi-material composite substrate structure provided in Embodiment 1, such as Figures 6 to 13 As shown, the operation is as follows: Step S1 ( Figure 6 ): A 3C-SiC epitaxial layer is grown and deposited on a Si substrate to obtain a 3C-SiC / Si substrate.

[0064] Specifically, a layer of 3C-SiC is deposited on a Si substrate by a chemical or physical growth method as a high heat dissipation layer.

[0065] 3C-SiC can be grown at temperatures below 1300°C and belongs to the same cubic crystal system as Si. The 3C-SiC-on-Si substrate can have the advantages of large size and low cost while ensuring good crystal quality.

[0066] Step S2 ( Figure 7 ): The SiC film is bonded to the 3C-SiC / Si substrate to obtain a SiC / 3C-SiC / Si substrate.

[0067] Specifically, the HPSI type high-purity semi-insulating SiC film is bonded to the 3C-SiC / Si substrate through the Smart-cut process, and the HPSI-SiC film serves as an isolation layer between high-frequency and high-voltage chip structures.

[0068] Specific production methods such as Fig.14 As shown, hydrogen ions are first implanted into a HPSI type SiC wafer, and then the SiC wafer is bonded to 3C-SiC / Si. After appropriate annealing or condensation method, the hydrogen implanted wafer is completely cracked, and the semi-insulating SiC film is peeled off to form a HPSI-SiC / 3C-SiC / Si substrate. The surface is chemically mechanically polished (CMP) to remove residual damage and form a smooth surface.

[0069] Step S3 ( Figure 8 ): A multilayer structure is grown on a SiC / 3C-SiC / Si substrate by metal organic chemical vapor deposition or hydride vapor phase epitaxy; the multilayer structure includes a buffer layer, a high resistance layer and a channel layer which are stacked in sequence from bottom to top.

[0070] Specifically, a Ga2O3 multilayer structure is grown on a HPSI-SiC / 3C-SiC / Si substrate by metal organic chemical vapor deposition (MOCVD) or hydride vapor phase epitaxy (HVPE), including a bottom unintentionally-doped (UID) Ga2O3 buffer layer, a high-resistance Ga2O3 layer formed by doping control, and a top unintentionally-doped UID-Ga2O3 channel layer.

[0071] The Ga2O3 buffer layer is formed in the early stage of epitaxy and usually has poor crystal quality and is not used to prepare devices, but it can provide a ground potential for subsequently prepared devices; the high-resistance Ga2O3 layer limits the flow of carriers in the channel layer and can improve the gate control capability of the device; the UID-Ga2O3 buffer layer is formed in the later stage of epitaxy and has better crystal quality and is used as the channel layer to form the device functional area.

[0072] The UID-Ga2O3 buffer layer is locally implanted with N ions and annealed to form a high-resistance quasi-p-Ga2O3 region in a part of the inner region of the UID-Ga2O3 buffer layer. The UID-Ga2O3 is n-type and forms a body PN diode with the high-resistance quasi-p-Ga2O3 region.

[0073] As the fourth generation ultra-wide bandgap semiconductor material, Ga2O3 has the advantages of good voltage resistance and radiation resistance. Although epitaxial growth of Ga2O3 on SiC is still heteroepitaxial growth, the crystal quality of the epitaxial layer is improved to a certain extent because the mismatch between the two is small compared to the mismatch between Si and Ga2O3.

[0074] Step S4 ( Fig. 9 ): A barrier layer is epitaxially grown on the channel layer.

[0075] Specifically, epitaxial growth (Al x Ga 1-x )2O3 barrier layer, Ga2O3 / (Al x Ga 1-x )2O3 heterojunction forms a two-dimensional electron gas (2DEG) at the interface due to the polarization effect, which can be used to prepare high-frequency devices.

[0076] Step S5 ( Fig. 9 ): The substrate is locally etched to different depths to form through holes of different depths; the channel etched into the inside of the 3C-SiC epitaxial layer is used as the trench isolation area between devices; the channel etched into the inside of the buffer layer is used for electrode grounding lead-out; the channel etched into the high resistance layer is used for the electrode lead-out of the body PN diode.

[0077] Specifically, Fig. 9 As shown, the substrate is locally etched to form through holes of different depths. The through holes etched into the 3C-SiC epitaxial layer will be used as trench isolation (Trench Isolation) regions between devices later; the through holes etched into the Ga2O3 buffer layer will be used for electrode grounding (GND Via) later; the through holes etched into the high-resistance quasi-p-Ga2O3 region will be used as electrode leads (Diode Via) of the body PN diode later, so that the body diode can be used as an avalanche diode to connect with the subsequently prepared high-frequency and high-voltage devices, thereby improving the avalanche capability of the high-frequency and high-voltage devices.

[0078] Step S6 ( Fig.10 ): A layer of p-type doped III-V material is deposited on the surface, or a layer of undoped III-V material is subjected to p-type ion implantation and annealing activation to form a p-type material, and the p-type material is selectively etched to form an interval-distributed p-type layer.

[0079] Specifically, in this embodiment, a layer of Ga2O3 is deposited on the surface and N ion implantation, annealing activation, and selective etching processes are performed to form a p-Ga2O3 layer.

[0080] Step S7 ( Fig.10 ): Deposition, partial etching and partial filling of a passivation dielectric layer. The inside of the grounding channel is covered with a passivation dielectric layer. The dielectric layer at the bottom of the grounding channel is etched open to expose the buffer layer. A dielectric layer is covered on the surface of the barrier layer. The dielectric opening of the electrode channel; the channel in the trench isolation area is filled with dielectric material.

[0081] Step S8 ( Fig.11 ): Deposit metal and pattern it, perform ohmic annealing process to form source, drain, electrode lead-out and electrode preparation of body PN diode at the formed dielectric opening, and form a gate at the p-Ga2O3 layer.

[0082] Step S9 ( Fig.12 ): The passivation dielectric layer is deposited again and locally etched and planarized to complete the PAD electrode opening and the ground channel opening.

[0083] Step S10 ( Fig.13 ): Deposit PAD metal and pattern it, fill the metal of the ground via, and complete the multi-layer metal layer interconnection of the chip.

[0084] Specifically, PAD metal is deposited and patterned, metal filling of grounding vias is completed, and multi-layer metal layer interconnection of the chip is completed. The integrated structure achieves high heat dissipation performance through high thermal conductivity 3C-SiC; isolation between the device and the chip is achieved through HPSI semi-insulating SiC and trench isolation; the device is electrically connected to the buffer layer through the ground potential of the Ga2O3 buffer layer to prevent the source of the device from floating; high-voltage and high-frequency devices are prepared using epitaxial Ga2O3 materials and corresponding heterojunction materials.

[0085] This integrated structure can realize a high-frequency and high-voltage integrated chip with good heat dissipation, effective isolation, improved floating body effect, high performance and high integration.

[0086] In summary, the integrated structure based on the multi-material composite substrate structure and the corresponding manufacturing method provided in the above embodiments 1 to 5 have the following technical effects: (1) The multi-material composite substrate contains high thermal conductivity 3C-SiC, which can be used as a high heat dissipation layer for integrated circuits; the 3C-SiC layer is obtained by epitaxy based on a Si substrate, and belongs to the cubic crystal system with Si, so the process is feasible. It combines the advantages of Si's large size and low cost with the advantages of the wide bandgap semiconductor 3C-SiC.

[0087] (2) A layer of semi-insulating SiC film - SiC isolation layer - is bonded to a multi-material composite substrate, which can effectively achieve isolation between high-frequency and high-voltage chip structures. Semi-insulating SiC and 3C-SiC belong to the same silicon carbide system, and homogeneous bonding makes it easier to achieve a high-quality bonding interface without affecting the performance of the bonding material.

[0088] (3) Compared with directly bonding or epitaxially growing III-V materials on Si, heterojunction or heteroepitaxial growth of III-V compound semiconductor materials on semi-insulating SiC films makes it easier to obtain III-V semiconductor epitaxial layers with good crystal quality, which is beneficial for the preparation of high-performance materials.

[0089] (4) Using a III-V material buffer layer of average crystal quality as a ground potential layer can improve the floating body phenomenon of integrated circuits.

[0090] That is, when the prior art substrate is Si, the integrated structure can effectively solve a series of problems existing therein, such as hot carrier effect, short channel effect, latch effect of bulk silicon device, power consumption, parasitic resistance and capacitance increase; when the prior art substrate is SOI, it can effectively solve a series of problems existing in the prior art, such as floating body effect, self-heating effect, parasitic resistance and capacitance increase; and realize heterogeneous integration with compound semiconductors, thereby realizing high-performance and high-integration high-frequency and high-voltage integrated chips. In the description of this specification, the description with reference to the terms "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated structure based on a multi-material composite substrate, characterized in that: include: Multi-material composite substrate, multi-layer structure, barrier layer, trench isolation region, first channel, second channel, passivation dielectric layer, source, drain and gate; The multi-layer structure is epitaxially arranged on the multi-material composite substrate; The multilayer structure comprises a buffer layer, a high resistance layer and a channel layer which are sequentially stacked from bottom to top; a plurality of p-type regions are spaced in the region of the channel layer; The barrier layer is epitaxially arranged on the channel layer, and a two-dimensional electron gas is formed at the interface; the trench isolation region penetrates from the top of the barrier layer downward to the middle area of ​​the multi-material composite substrate, and is used to isolate different devices; the first channel penetrates from the top of the barrier layer downward to the buffer layer, and is used for electrode grounding lead-out; the second channel penetrates from the top of the barrier layer downward to the channel layer, and contacts the p-type region, and is used for electrode lead-out of the donor PN diode; The passivation dielectric layer is deposited on the surface of the barrier layer, filled in the trench isolation region, and covers the inner wall sides of the first channel and the second channel; The source electrode, the drain electrode and the gate electrode are respectively arranged in the passivation dielectric layer, wherein the drain electrode is located at the top of the second channel and contacts with the electrode of the body PN diode.

2. The integrated structure based on a multi-material composite substrate structure according to claim 1, characterized in that: The multi-material composite substrate comprises a Si substrate, a 3C-SiC epitaxial layer and a SiC isolation layer; The 3C-SiC epitaxial layer is epitaxially arranged on the Si substrate; The SiC isolation layer is bonded on the 3C-SiC epitaxial layer, and a bonding interface layer is formed between the SiC isolation layer and the 3C-SiC epitaxial layer.

3. The integrated structure based on a multi-material composite substrate structure according to claim 2, characterized in that: The SiC isolation layer is a high-purity semi-insulating SiC film, or a composite layer of a p-type SiC layer and a high-purity semi-insulating SiC film.

4. The integrated structure based on a multi-material composite substrate according to claim 1, characterized in that: In the multi-layer structure, the buffer layer, the high resistance layer and the channel layer are all made of III-V compound semiconductor materials.

5. The integrated structure based on a multi-material composite substrate structure according to claim 4, characterized in that: The III-V compound semiconductor material is a heterojunction composed of one or at least two of GaN, GaAs, InP, Ga2O3, and AlGaN.

6. The integrated structure based on a multi-material composite substrate according to claim 4, characterized in that: A nucleation layer is provided at the bottom of the buffer layer.

7. The integrated structure based on a multi-material composite substrate according to claim 6, characterized in that: The buffer layer is a Ga2O3 buffer layer; the high-resistance layer is a high-resistance Ga2O3 layer; the channel layer is an unintentionally doped Ga2O3 channel layer; the barrier layer is an (Al x Ga 1-x )2O3 barrier layer, where 0 < x < 1, and the p-type region is a high-resistance quasi-p-Ga2O3 region; Or, the nucleation layer is an AlN nucleation layer; the buffer layer is a GaN buffer layer; the high resistance layer is a high resistance GaN layer; the channel layer is a GaN channel layer; the barrier layer is an AlGaN barrier layer, and the p-type region is a p-GaN region.

8. The integrated structure based on a multi-material composite substrate according to claim 1, characterized in that: The integrated structure further includes a p-type layer; The p-type layer is arranged at the bottom of the gate and is located in the passivation dielectric layer.

9. The integrated structure based on a multi-material composite substrate according to claim 1, characterized in that: The integrated structure also includes a metal connection layer; The plurality of metal connection layers are spaced apart on the top of the passivation dielectric layer and are used for external connection to form a chip interconnection structure.

10. A method for manufacturing an integrated structure based on a multi-material composite substrate structure as claimed in any one of claims 1 to 9, characterized in that: include: A 3C-SiC epitaxial layer is grown and deposited on a Si substrate to obtain a 3C-SiC / Si substrate; Bonding the SiC film to the 3C-SiC / Si substrate to obtain a SiC / 3C-SiC / Si substrate; A multilayer structure is grown on the SiC / 3C-SiC / Si substrate by metal organic chemical vapor deposition or hydride vapor phase epitaxy; the multilayer structure comprises a buffer layer, a high resistance layer and a channel layer which are sequentially stacked and arranged from bottom to top; epitaxially growing a barrier layer on the channel layer; Etching the substrate locally at different depths to form through holes of different depths; etching the channel inside the 3C-SiC epitaxial layer as a trench isolation region between devices; etching the channel inside the buffer layer for electrode grounding lead-out; etching the channel inside the high resistance layer for electrode lead-out of the body PN diode; Depositing a layer of p-type doped III-V material on the surface, or implanting a layer of undoped III-V material with p-type ions, annealing and activating it to form a p-type material, and selectively etching the p-type material to form a spaced p-type layer; Depositing, partially etching and partially filling a passivation dielectric layer, the inside of the grounding channel is covered with a passivation dielectric layer, and the dielectric layer at the bottom of the grounding channel is opened to expose the buffer layer; a dielectric layer is covered on the surface of the barrier layer, and the dielectric opening of the electrode channel; The channel filling dielectric material of the trench isolation region; Depositing metal and patterning it, performing an ohmic annealing process to form a source electrode, a drain electrode, and an electrode lead-out and electrode preparation of a body PN diode at the formed dielectric opening, and forming a gate at the p-type layer; Deposit the passivation dielectric layer again, etch and planarize it locally, and complete the PAD electrode opening and ground channel opening; Deposit and pattern PAD metal, fill the ground via metal, and complete the chip's multi-layer metal layer interconnection.

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