Display device, electronic device, and method of manufacturing display device

Abstract

The invention relates to a display device, an electronic device and a method of manufacturing the display device. The display device includes: a display panel that displays an image; the circuit board is connected with the display panel; and a metal pattern electrically connecting the display panel and the circuit board. The display panel includes: a base layer; and a circuit layer disposed on the base layer and including a pad electrode exposed to the outside via an opening defined to pass through the base layer. The metal pattern includes: a first portion overlapping the opening and contacting the pad electrode; and a second portion that does not overlap the opening and is in contact with the circuit board.

Description

Technical Field

[0001] The present invention relates to a display device, an electronic device, and a method of manufacturing the display device, and more particularly, to a display device including a circuit board that can be bonded to a rear surface thereof, an electronic device, and a method of manufacturing the display device. Background Art

[0002] Electronic devices such as smart phones, tablet computers, notebook computers, car navigation units, and smart TVs are being developed. The electronic devices include display devices for providing information.

[0003] Various types of display devices are being developed to satisfy user experience (UX) and user interface (UI). Summary of the invention

[0004] The present invention provides a display device that is manufactured by a simplified manufacturing method and has a reduced non-display area.

[0005] The invention provides an electronic device comprising the display device.

[0006] The invention provides a method for manufacturing the display device.

[0007] According to an embodiment, the present invention provides a display device, comprising: a display panel, displaying an image; a circuit board, coupled to the display panel; and a metal pattern, electrically connecting the display panel and the circuit board. The display panel comprises: a base layer; and a circuit layer, disposed on the base layer, and comprising a pad electrode exposed to the outside via a first opening defined to pass through the base layer. The metal pattern comprises: a first portion, overlapping the first opening and contacting the pad electrode; and a second portion, not overlapping the first opening and contacting the circuit board.

[0008] In an embodiment, the pad electrode includes: a first pad portion disposed on the base layer and not overlapping the first opening; and a second pad portion overlapping the first opening.

[0009] In an embodiment, the base layer includes: a sub-base layer in contact with the circuit board; and a base inorganic layer disposed on the sub-base layer.

[0010] In an embodiment, the first opening includes: a first sub-opening defined through the base inorganic layer; and a second sub-opening defined through the sub-base layer.

[0011] In an implementation, the second pad portion is disposed in the first sub-opening, and the second pad portion is exposed to the outside through the second sub-opening.

[0012] In an embodiment, the circuit layer includes: a transistor; and a shielding electrode disposed under the transistor and overlapping a semiconductor pattern of the transistor.

[0013] In an embodiment, the first pad portion and the shielding electrode are disposed on the same layer.

[0014] In an embodiment, the circuit layer includes an inorganic layer disposed on the base layer, the pad electrode is disposed on the inorganic layer, and the inorganic layer includes a second opening corresponding to the first opening, and the pad electrode is exposed through the second opening.

[0015] In an implementation, the circuit layer further includes a connection pattern connected to the semiconductor pattern, and the first pad portion and the connection pattern are disposed on the same layer.

[0016] In an implementation, the transistor further includes a gate electrode overlapping the semiconductor pattern, and the first pad portion and the gate electrode are disposed on the same layer.

[0017] In an embodiment, the circuit layer further includes at least one signal line connected to the transistor, and the pad electrode is electrically connected to the signal line.

[0018] In an embodiment, the first portion is disposed in the first opening.

[0019] In an embodiment, the first portion covers one side surface of the base layer defining the first opening.

[0020] In an embodiment, the display device further includes an adhesive resin, at least a portion of the adhesive resin is disposed in the first opening, and the adhesive resin covers the metal pattern.

[0021] In an embodiment, the adhesive resin covers the other side surface of the base layer facing the one side surface of the base layer.

[0022] In an embodiment, the metal pattern and the adhesive resin are provided to fill the first opening.

[0023] In an embodiment, a circuit board includes: a base film; and a bump electrode disposed between the base film and a base layer, and the bump electrode is electrically connected to the pad electrode via a metal pattern.

[0024] In an embodiment, each of the bump electrode and the pad electrode is provided in plural, and the metal pattern is provided in plural to correspond to the bump electrode and the pad electrode.

[0025] In an embodiment, the display device further includes an adhesive layer disposed between the bump electrode and the base layer.

[0026] In an embodiment, the circuit board is disposed to be spaced apart from the first opening.

[0027] An embodiment of the present invention provides an electronic device, comprising: a housing; an electronic module disposed in the housing; and a display device, disposed to overlap with the electronic module. The display device comprises: a display panel, displaying an image; a circuit board, coupled to the display panel; and a metal pattern, electrically connecting the display panel and the circuit board. The display panel comprises: a base layer; and a circuit layer, disposed on the base layer, and comprising a pad electrode exposed to the outside via a first opening defined to pass through the base layer. The metal pattern comprises: a first portion, overlapping with the first opening and in contact with the pad electrode; and a second portion, not overlapping with the first opening and in contact with the circuit board.

[0028] An embodiment of the present invention provides a method for manufacturing a display device. The method for manufacturing a display device includes: forming a preliminary base layer; placing a pad electrode on the preliminary base layer to form a circuit layer; etching the preliminary base layer to form a base layer, defining a first opening through the base layer to expose the pad electrode to the outside; placing a circuit board on the lower surface of the base layer; and forming a metal pattern to electrically connect the pad electrode and the circuit board. The metal pattern includes: a first portion overlapping the first opening and contacting the pad electrode; and a second portion not overlapping the first opening and contacting the circuit board.

[0029] In an embodiment, forming the preliminary base layer includes: forming a first preliminary sub-base layer; forming a first preliminary base inorganic layer on the first preliminary sub-base layer; forming a second preliminary sub-base layer on the first preliminary base inorganic layer; and forming a second preliminary base inorganic layer on the second preliminary sub-base layer.

[0030] In an embodiment, forming the preliminary base layer further includes: before forming the second preliminary sub-base layer, performing a first preliminary etching on the first preliminary base inorganic layer to form a first basic inorganic layer; and before placing a pad electrode on the preliminary base layer, performing a second preliminary etching on the second preliminary base inorganic layer to form a second basic inorganic layer.

[0031] In an embodiment, placing the pad electrode on the preliminary base layer includes placing the pad electrode in a sub-opening formed through the second base inorganic layer by the secondary preliminary etching.

[0032] In an embodiment, forming the circuit layer includes placing an inorganic layer on the preliminary base layer, and providing a pad electrode on the inorganic layer.

[0033] In an embodiment, forming the base layer includes: etching the preliminary base layer to form a first opening; and etching the inorganic layer to form a second opening corresponding to the first opening, exposing the pad electrode to the outside through the second opening.

[0034] In an embodiment, the second opening is formed substantially simultaneously with the first opening.

[0035] In an embodiment, forming the circuit layer further includes: forming a metal layer on the inorganic layer; and etching the metal layer to form a pad electrode.

[0036] In an embodiment, forming the circuit layer further includes: forming a shielding electrode; and forming a transistor including a semiconductor pattern on the shielding electrode, and the semiconductor pattern overlaps the shielding electrode.

[0037] In an embodiment, forming the circuit layer includes forming a shielding electrode on the preliminary base layer, and forming the pad electrode and the shielding electrode substantially simultaneously.

[0038] In an implementation, the transistor further includes a gate electrode overlapping the semiconductor pattern, and the pad electrode is formed substantially simultaneously with the gate electrode.

[0039] In an embodiment, forming the circuit layer further includes forming a connection pattern connected to the semiconductor pattern, and the pad electrode and the connection pattern are formed substantially simultaneously.

[0040] In an embodiment, the method further includes forming an adhesive resin after forming the metal pattern, at least a portion of the adhesive resin is disposed in the first opening, and the adhesive resin covers the metal pattern.

[0041] According to an embodiment, a flexible circuit board is coupled to a display panel on a rear surface of the display panel (rear surface bonding). The non-display area of ​​the display panel is not bent, and thus defects that occur when the non-display area of ​​the display panel is bent are prevented. In addition, a frame area of ​​a window covering the non-display area of ​​the display panel is reduced.

[0042] According to an embodiment, a method for manufacturing a display device includes forming a base opening formed to completely penetrate a base layer and expose a pad electrode embedded in a circuit layer to the outside. A metal pattern disposed in the base opening defined to completely penetrate the base layer electrically connects the pad electrode and the bump electrode. Since the metal pattern is directly connected to the pad electrode exposed through the base opening, no connection electrode is required between the pad electrode and the metal pattern. Therefore, the manufacturing process of the display device is simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above and other advantages of the present invention will become apparent by referring to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0044] Figure 1 is a perspective view of an electronic device according to an embodiment;

[0045] Figure 2 is an exploded perspective view of an electronic device according to an embodiment;

[0046] Figure 3 According to the implementation method Figure 2 A cross-sectional view of the display device taken along line II';

[0047] Figure 4 is a cross-sectional view of a display module according to an embodiment;

[0048] Figure 5 is a plan view of a display panel according to an embodiment;

[0049] Figure 6 is a cross-sectional view of a display module according to an embodiment;

[0050] Figure 7 is a plan view of a display panel according to an embodiment;

[0051] Figure 8 is an enlarged plan view of a portion of a display device according to an embodiment;

[0052] Fig. 9A According to the implementation method Figure 8 A cross-sectional view of a portion of the display device taken along line II-II';

[0053] Fig. 9B is a cross-sectional view of a portion of a display device according to an embodiment;

[0054] Fig. 10A is a cross-sectional view of a portion of a display device according to an embodiment;

[0055] Fig. 10B is a cross-sectional view of a portion of a display device according to an embodiment;

[0056] Fig.11 is a flowchart showing a method of manufacturing a display device according to an embodiment;

[0057] Fig. 12A are views showing processes of a method of manufacturing a display device according to an embodiment;

[0058] Fig. 12B are views showing processes of a method of manufacturing a display device according to an embodiment;

[0059] Fig. 12C are views showing processes of a method of manufacturing a display device according to an embodiment;

[0060] Fig.12D are views showing processes of a method of manufacturing a display device according to an embodiment;

[0061] Fig.12E are views showing processes of a method of manufacturing a display device according to an embodiment;

[0062] Fig.12F are views showing processes of a method of manufacturing a display device according to an embodiment;

[0063] Figure 12G are views showing processes of a method of manufacturing a display device according to an embodiment;

[0064] Fig.12H are views showing processes of a method of manufacturing a display device according to an embodiment;

[0065] Fig.12I are views showing processes of a method of manufacturing a display device according to an embodiment;

[0066] Fig.13A is a flowchart showing a method of manufacturing a display device according to an embodiment;

[0067] Fig. 13B is a flowchart illustrating a method of manufacturing a display device according to an embodiment; and

[0068] Fig. 13C is a flowchart illustrating a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0069] The present invention can be modified and implemented in many different forms, and therefore specific embodiments will be illustrated in the accompanying drawings and will be described in detail below. However, the present invention should not be limited to the disclosed specific embodiments, and should be interpreted as including all modifications, equivalents or substitutions included in the spirit and scope of the present invention.

[0070] In the present disclosure, it will be understood that when an element (or region, layer or portion) is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, directly connected to or directly coupled to another element or layer, or intervening elements or layers may be present.

[0071] The same reference numerals denote the same elements throughout. In the drawings, the thickness, proportion and size of components are exaggerated in order to effectively describe the technical contents.

[0072] As used herein, the term "and / or" may include any and all combinations of one or more of the associated listed items.

[0073] It will be understood that, although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teaching of the present disclosure, the first element discussed below can be referred to as the second element. As used herein, the singular forms "one", "a kind of" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise.

[0074] For ease of description, spatially relative terms such as “below,” “beneath,” “lower,” “above,” “upper,” etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures.

[0075] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted as an idealized or overly formal meaning unless explicitly so defined herein.

[0076] It will also be understood that when used in this specification, the terms "include" and / or "including" specify the presence of stated features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof.

[0077] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0078] Figure 1 is a perspective view of an electronic device ED according to an embodiment. Figure 2 is an exploded perspective view of an electronic device ED according to an embodiment. Figure 3 According to the implementation method Figure 2 4 is a cross-sectional view of the display device DD taken along line II'.

[0079] In the implementation mode and with reference to Figure 1 , the electronic device ED may include a display surface DS defined by a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The electronic device ED may provide an image IM to a user through the display surface DS.

[0080] In an embodiment, the display surface DS may include a display area DA and a non-display area NDA disposed around the display area DA. The display area DA may display an image IM, and the non-display area NDA may not display the image IM. The non-display area NDA may surround the display area DA, however, it should not be limited thereto or thereby, and the shape of the display area DA and the shape of the non-display area NDA may be changed.

[0081] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 may be referred to as a third direction DR3. The front surface and the rear surface of each component of the electronic device ED may be distinguished from each other with respect to the third direction DR3. In the present disclosure, the expression "when viewed in a plane" may mean a state viewed in the third direction DR3.

[0082] In an embodiment, the electronic device ED may be a foldable electronic device that can be folded relative to a folding axis. The folding axis may be substantially parallel to the first direction DR1 or the second direction DR2, and may define a folding area in a portion of the display area DA. The electronic device ED may be folded inward (folded inward) to allow a portion of the display area DA to face another portion of the display area DA, or may be folded outward (folded outward) to allow a portion of the display area DA not to face another portion of the display area DA.

[0083] In the implementation mode and with reference to Figure 2 , the electronic device ED may include a display device DD, an electronic module EM, a power module PSM and a housing HM. Figure 2 The electronic device ED is schematically shown in FIG. 1 , and the electronic device ED may further include a mechanical structure (eg, a hinge) to control the operation of the display device DD, such as a folding or rolling operation of the display device DD.

[0084] In an embodiment, the display device DD may generate an image IM and may sense an external input. The display device DD may include a window WM, an upper member UM, a display module DM, a lower member LM, a circuit board (or a flexible circuit board) FCB, and a driving chip DIC. The upper member UM may include a component disposed above the display module DM, and the lower member LM may include a component disposed below the display module DM.

[0085] In an embodiment, the window WM may provide a front surface of the electronic device ED. The window WM may include a transmissive area TA and a bezel area BZA. Figure 1The display area DA and non-display area NDA of the display surface DS shown may be defined by a transmissive area TA and a bezel area BZA. The transmissive area TA may be an area through which an image passes, and the bezel area BZA may be an area covering a structure / member disposed under the window WM.

[0086] In an embodiment, the display module DM may include a display area DM-DA and a non-display area DM-NDA, which correspond to Figure 1 The display area DA and the non-display area NDA are shown. In the present disclosure, the expression "an area / portion corresponds to another area / portion" means "an area / portion overlaps another area / portion", however, they should not be limited to having the same size as each other.

[0087] In an embodiment, a pad area PA may be defined at one side of the non-display area DM-NDA. The pad area PA may be electrically coupled or connected to a circuit board FCB described later. In an embodiment, the pad area PA may be defined in a rear surface of the display module DM.

[0088] In an embodiment, the display module DM may have a substantially quadrilateral shape. The expression "substantially quadrilateral shape" used herein means not only the mathematical concept of a rectangular shape, but also a shape that is similar to a rectangle and is perceived as a rectangle by a user. For example, the substantially quadrilateral shape may include a quadrilateral shape with rounded corners. In addition, the edge of the display module DM having a substantially rectangular shape should not be limited to a straight line, and the edge may have a curved area.

[0089] In an embodiment, the upper member UM may include a protective film or an optical film. The optical film may include a polarizer or a retarder to reduce the reflection of external light. The lower member LM may include a protective film to protect the display module DM, a supporting member to support the display module DM, and a digitizer. The upper member UM and the lower member LM will be described in detail later.

[0090] In an embodiment, the circuit board FCB may be disposed under the display module DM. The circuit board FCB may be coupled to the rear surface of the display module DM and may electrically connect the display module DM to the main circuit board MCB (refer to FIG. Figure 3 ). The circuit board FCB may include at least one insulating layer and at least one conductive layer. The conductive layer may include a plurality of signal lines.

[0091] In an implementation, the driving chip DIC may be mounted on the circuit board FCB. The driving chip DIC may include a driving circuit, such as a data driving circuit, to drive the pixels of the display module DM. Figure 2The structure in which the driver chip DIC is mounted on the circuit board FCB is shown, however, the present invention should not be limited thereto or thereby. As an example, in another embodiment, the driver chip DIC may be mounted on the display module DM or the main circuit board MCB (see Figure 3 )superior.

[0092] In an embodiment, the electronic module EM may include a control module, a wireless communication module, an image input module, an audio input module, an audio output module, a memory, and an external interface module. The electronic module EM may include a main circuit board, and the module may be mounted on the main circuit board or may be electrically connected to the main circuit board via a flexible circuit board. The electronic module EM may be electrically connected to the power supply module PSM.

[0093] In an embodiment, although not shown in the figure, the electronic device ED may further include an electro-optical module. The electro-optical module may be an electronic component that outputs or receives an optical signal. The electro-optical module may include a camera module and / or a proximity sensor. The camera module may take a picture of an external object via an area of ​​the display module DM.

[0094] In an embodiment, Figure 2 The housing HM shown can be connected to the display device DD, specifically to the window WM, to accommodate the modules mentioned above. The housing HM is shown as having an integral shape, however, it should not be limited to this or should not be limited thereby. In an embodiment, the housing HM may include a plurality of parts connected to each other, such as a side surface edge portion and a bottom portion.

[0095] In the implementation mode and with reference to Figure 3 , the window WM may include a base substrate BS and a frame pattern BM disposed on the lower surface of the base substrate BS. In an embodiment, the base substrate BS may include a synthetic resin film or a glass substrate. The base substrate BS may have a multi-layer structure. The base substrate BS may include a thin glass substrate, a protective film disposed on the thin glass substrate, and an adhesive layer attaching the thin glass substrate and the protective film.

[0096] In an embodiment, the frame pattern BM may be a colored light blocking layer and may be formed by a coating process. The frame pattern BM may include a base material and a pigment or dye mixed with the base material. Figure 1 The non-display area NDA and Figure 2The frame area BZA shown overlaps. The frame pattern BM may be disposed on the lower surface of the base substrate BS. When the base substrate BS has a multi-layer structure, the frame pattern BM may be disposed at an interface defined between the multiple layers. For example, in an embodiment, the frame pattern BM may be disposed between the thin glass substrate and the protective film. Although not shown in the figure, in an embodiment, the window WM may include at least one of a hard coating layer, an anti-fingerprint layer, and an anti-reflection layer disposed on the upper surface of the base substrate BS.

[0097] In an embodiment, the upper member UM may include an upper film. The upper film may include a synthetic resin film. The synthetic resin film may include polyimide, polycarbonate, polyamide, triacetyl cellulose, polymethyl methacrylate, or polyethylene terephthalate.

[0098] In an embodiment, the upper film may absorb external impact applied to the front surface of the display device DD. According to an embodiment, the display module DM may include a color filter as an anti-reflection member instead of a polarizing film, and in this case, the impact resistance of the display device DD to the external impact applied to the front surface thereof may be reduced. The upper film may compensate for the reduction in the impact resistance to the external impact caused by applying the color filter to the display module DM.

[0099] In an embodiment, the upper member UM may be connected to the frame area BZA (refer to Figure 2 ) and the transmissive area TA (reference Figure 2 ) overlap. The upper member UM may overlap only a portion of the frame area BZA. A portion of the frame pattern BM may be exposed without being covered by the upper member UM. According to an embodiment, the upper member UM may be omitted. According to an embodiment, the upper member UM may be replaced with an optical film including a polarizer and a retarder.

[0100] In an embodiment, although not shown in the drawings, an adhesive layer attaching the upper member UM and the window WM may be provided between the upper member UM and the window WM. The adhesive layer may be a pressure sensitive adhesive (PSA) film or an optically clear adhesive (OCA).

[0101] In an embodiment, the display module DM may be disposed below the upper member UM. The display module DM may overlap the bezel area BZA and the transmissive area TA. The display module DM may completely overlap the upper member UM in the bezel area BZA. When viewed in a plane, a side surface of the display module DM may be aligned with a side surface of the upper member UM, and a corner of the display module DM may be aligned with a corner of the upper member UM.

[0102] In an embodiment, in the bezel area BZA, the pad area PA of the display module DM may overlap with the upper member UM. The portion of the display module DM corresponding to the pad area PA may be coupled to the lower surface of the upper member UM through an adhesive layer. When the pad area PA overlaps with the upper member UM and the portion of the display module DM overlapping with the pad area PA is coupled to the upper member UM, when the circuit board FCB is coupled to the pad area PA, the upper member UM may fully support the pad area PA.

[0103] In an embodiment, the lower member LM may include a lower film PF and a cover panel CP. The lower member LM may further include a support plate and a digitizer.

[0104] In an embodiment, the lower film PF may expose the pad area PA of the display module DM. The area of ​​the lower film PF may be smaller than the area of ​​the display module DM. For example, the lower film PF may overlap only with the display area DM-DA. The lower film PF may be configured to define an opening area PF-OP corresponding to the non-display area DM-NDA therein. In another embodiment, the lower film PF may have substantially the same size as the display module DM. In this case, the lower film PF may be configured to define an opening area PF-OP corresponding to the pad area PA therein. The pad area PA may be exposed through the opening area PF-OP.

[0105] In an embodiment, the lower film PF may expose the pad area PA. The area of ​​the lower film PF may be smaller than the area of ​​the display module DM. For example, the lower film PF may overlap only with the display area DA. The lower film PF may have substantially the same size as the display module DM. The lower film PF may be configured to define an opening area PF-OP corresponding to the pad area PA therein. The pad area PA may be exposed through the opening area PF-OP.

[0106] In an embodiment, the cover panel CP may be disposed below the lower film PF. The cover panel CP may increase the resistance to the compressive force caused by the external pressure. Therefore, the cover panel CP may prevent the display module DM from being deformed. The cover panel CP may include a flexible plastic material such as polyimide or polyethylene terephthalate. In addition, the cover panel CP may be a colored film with low light transmittance. The cover panel CP may absorb light incident thereon from the outside. As an example, the cover panel CP may be a black synthetic resin film. When the display device DD is viewed from the upper side of the window WM, the components disposed below the cover panel CP may not be seen by the user.

[0107] In an embodiment, although not shown in the figure, the support plate may be further arranged below the cover panel CP. The support plate may include a high-strength metal material. The support plate may include a reinforced fiber composite material. The support plate may include reinforcing fibers arranged in the base portion. The reinforcing fibers may be carbon fibers or glass fibers. The base portion may include a polymer resin. The base portion may include a thermoplastic resin. As an example, in an embodiment, the base portion may include a polyamide-based resin or a polypropylene-based resin. For example, in an embodiment, the reinforced fiber composite material may be a carbon fiber reinforced plastic (CFRP) or a glass fiber reinforced plastic (GFRP).

[0108] In an embodiment, the main circuit board MCB may be disposed on the lower surface of the circuit board FCB. The circuit board FCB may include an insulating film and a wire mounted on the insulating film. The main circuit board MCB may include a signal line (not shown) and an electronic component (not shown). The electronic component may be connected to the signal line and may be electrically connected to the display module DM. The electronic component may generate various electrical signals, for example, a signal for generating an image or a signal for sensing an external input, or may process the sensed signal. At the same time, the main circuit board MCB may be arranged to correspond to each of the electrical signals to be generated and processed, and three or more main circuit boards MCB may be arranged.

[0109] In an embodiment, although not shown in the drawings, the main circuit board MCB may include a driving chip DIC (refer to Figure 2 ).

[0110] In the implementation mode and with reference to Figure 2 and Figure 3 , the circuit board FCB may be coupled to the rear surface of the display module DM (rear surface bonding). Since the non-display area DM-NDA of the display module DM is not bent, defects that occur when the display module DM is bent may be prevented in the non-display area DM-NDA. In addition, the size of the frame area BZA of the window WM required to cover the non-display area DM-NDA of the display module DM may be reduced.

[0111] Figure 4 is a cross-sectional view of a display module DM according to an embodiment.

[0112] In the implementation mode and with reference to Figure 4 The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may include a base layer BL, a circuit layer DP-CL, a display element layer DP-ED and an encapsulation layer TFE.

[0113] In an embodiment, the circuit layer DP-CL may be disposed on the upper surface of the base layer BL. The base layer BL may be a flexible substrate that is bendable, foldable, or rollable. The base layer BL may be a glass substrate, a metal substrate, or a polymer substrate, however, it should not be limited thereto or thereby. According to an embodiment, the base layer BL may be an inorganic layer, an organic layer, or a composite material layer. The base layer BL may have substantially the same shape as the display panel DP.

[0114] In an embodiment, the base layer BL may have a multi-layer structure. For example, the base layer BL may include a first synthetic resin layer, a second synthetic resin layer, and an inorganic layer disposed between the first synthetic resin layer and the second synthetic resin layer. Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide-based resin, however, it should not be particularly limited.

[0115] In an embodiment, the circuit layer DP-CL may be disposed on the base layer BL. The circuit layer DP-CL may include a plurality of insulating layers, a plurality of semiconductor patterns, a plurality of conductive patterns, and a plurality of signal lines. The circuit layer DP-CL may include a pixel driving circuit. Hereinafter, unless otherwise specified, the expression "components A and B are disposed on the same layer" means that components A and B are formed by the same process and contain the same material or have the same stacking structure. Conductive patterns or semiconductor patterns disposed on the same layer may be interpreted as described above.

[0116] In an embodiment, the display element layer DP-ED may be disposed on the circuit layer DP-CL. The display element layer DP-ED may include a light emitting element. For example, the light emitting element may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro-LED, or a nano-LED.

[0117] In an embodiment, the encapsulation layer TFE may be disposed on the display element layer DP-ED. The encapsulation layer TFE may protect the display element layer DP-ED (i.e., the light emitting element) from moisture, oxygen, and foreign matter such as dust particles. The encapsulation layer TFE may include at least one encapsulation inorganic layer. The encapsulation layer TFE may include a stacked structure in which a first encapsulation inorganic layer, an encapsulation organic layer, and a second encapsulation inorganic layer are sequentially stacked.

[0118] In an embodiment, the input sensing layer ISL may be directly disposed on the display panel DP. The input sensing layer ISL may sense the user's input by an electromagnetic induction method or a capacitive method. The display panel DP and the input sensing layer ISL may be formed by a continuous process. The expression "the input sensing layer ISL is directly disposed on the display panel DP" used herein may mean that no intervening element is disposed between the input sensing layer ISL and the display panel DP. That is, a separate adhesive layer may not be disposed between the input sensing layer ISL and the display panel DP.

[0119] Figure 5 is a plan view of a display panel DP according to an embodiment. Figure 6 is a cross-sectional view of a display module DM according to an embodiment.

[0120] In the implementation mode and with reference to Figure 5 , the display panel DP may include a scan drive circuit SDC, a plurality of signal lines SGL, and a plurality of pixels PX. The pixels PX may be arranged in the display area DM-DA. Each of the pixels PX may include a light emitting element and a pixel drive circuit connected to the light emitting element. The scan drive circuit SDC, the signal lines SGL, and the pixel drive circuit may include Figure 4 The circuit layer DP-CL is shown.

[0121] In an embodiment, the scan drive circuit SDC may include a gate drive circuit. The gate drive circuit may generate a plurality of scan signals and may sequentially output the scan signals to a plurality of scan lines GL described later. The scan drive circuit SDC may also include a light emitting drive circuit different from the gate drive circuit. The light emitting drive circuit may also output the scan signals to another group of scan lines.

[0122] In an implementation, the scan driving circuit SDC may include a plurality of thin film transistors formed through the same process as the pixel driving circuit (eg, a low temperature polysilicon (LTPS) process or a low temperature polycrystalline oxide (LTPO) process).

[0123] In an embodiment, the signal line SGL may include a scan line GL, a data line DL, a power line PL, and a control signal line CSL. Each of the scan lines GL may be connected to a corresponding pixel PX among the pixels PX, and each of the data lines DL may be connected to a corresponding pixel PX among the pixels PX. The power line PL may be connected to the pixel PX. The data line DL may provide a data signal to the pixel PX. The control signal line CSL may provide a control signal to the scan drive circuit SDC.

[0124] In an embodiment, the power line PL may be provided in plurality. As an example, the power line PL may include a first power line receiving a first power supply voltage and a second power line receiving a second power supply voltage having a higher level than the first power supply voltage. The first power supply voltage may be provided to the pixel PX via the first power line, and the second power supply voltage may be provided to the pixel PX via the second power line. Figure 5 1 and 2 show one control signal line CSL as a representative example, however, in another embodiment, a plurality of control signal lines CSL may be provided.

[0125] In an embodiment, the scan line GL, the data line DL, and the power line PL may overlap the display area DM-DA and the non-display area DM-NDA, and the control signal line CSL may overlap the non-display area DM-NDA. Each of the signal lines SGL may have an integral shape, but may include a plurality of portions disposed on different layers. The different portions distinguished from each other by the insulating layer may be connected to each other via contact holes defined to pass through the insulating layer. For example, the data line DL may include a first portion disposed in the display area DM-DA and a second portion disposed in the non-display area DM-NDA and disposed on a different layer from the first portion. The first portion and the second portion may include materials different from each other and may have stacked structures different from each other.

[0126] In an embodiment, the signal line SGL may be electrically connected to the pad area PA. Figure 3 The main circuit board MCB is shown.

[0127] Figure 6 According to the embodiment, Figure 5 The cross section of the display module DM corresponding to the pixel PX.

[0128] In an embodiment, the pixel driving circuit PC driving the light emitting element LD may include a plurality of pixel driving elements. The pixel driving circuit PC may include a plurality of transistors S-TFT and O-TFT and a capacitor Cst. The transistor may include a silicon transistor S-TFT and an oxide transistor O-TFT. Figure 6 A silicon transistor S-TFT and an oxide transistor O-TFT are shown as representative examples of the transistor. Figure 6 The pixel driving circuit PC of FIG. 1 is only an example, and components of the pixel driving circuit PC should not be limited thereto or thereby. The pixel driving circuit PC may include only one type of transistor among a silicon transistor S-TFT and an oxide transistor O-TFT.

[0129] In the implementation mode and with reference to Figure 6, the base layer BL has a single-layer structure. The base layer BL may include a synthetic resin such as polyimide. The base layer BL may be formed by coating a synthetic resin layer on a working substrate (or a carrier substrate). When the display module DM is completed through a subsequent process, the working substrate may be removed.

[0130] In the implementation mode and with reference to Figure 6 , a first shielding electrode (or shielding electrode) BML1 may be disposed on the base layer BL. The first shielding electrode BML1 may receive a bias voltage. The first shielding electrode BML1 may receive a first power supply voltage. The first shielding electrode BML1 may prevent the potential caused by the polarization phenomenon from affecting the silicon transistor S-TFT. The first shielding electrode BML1 may prevent external light from reaching the silicon transistor S-TFT. According to an embodiment, the first shielding electrode BML1 may be a floating electrode isolated from other electrodes or lines. The first shielding electrode BML1 may be disposed to correspond to the silicon transistor S-TFT. The first shielding electrode BML1 may include a metal material, such as molybdenum.

[0131] In an embodiment, a barrier layer BRL may be disposed on the base layer BL and the first shielding electrode BML1. The barrier layer BRL may prevent foreign matter from entering therein from the outside. The barrier layer BRL may include at least one inorganic layer. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in plurality, and the silicon oxide layer may be alternately stacked with the silicon nitride layer.

[0132] In an embodiment, a buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL may prevent metal atoms or impurities from diffusing from the base layer BL to the first semiconductor pattern SC1 disposed thereon. The buffer layer BFL may include at least one inorganic layer. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer.

[0133] In an implementation, the first semiconductor pattern SC1 may be disposed on the buffer layer BFL. The first semiconductor pattern SC1 may include a silicon semiconductor. As an example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the first semiconductor pattern SC1 may include low temperature polycrystalline silicon.

[0134] In an embodiment, the first semiconductor pattern SC1 may have different electrical characteristics depending on whether it is doped. The first semiconductor pattern SC1 may include a first region having relatively high conductivity and a second region having relatively low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second region may be a non-doped region, or may be a region doped at a lower concentration than that of the first region. In an embodiment, the first semiconductor pattern SC1 may be an N-type transistor.

[0135] In an embodiment, the first region may have a greater conductivity than that of the second region and may be substantially used as an electrode or a signal line. The second region may substantially correspond to a channel region (or an active region) of a transistor. In other words, a portion of the first semiconductor pattern SC1 may be a channel of a transistor, another portion of the first semiconductor pattern SC1 may be a source or drain of the transistor, and the remaining portion of the first semiconductor pattern SC1 may be a connection electrode or a connection signal line.

[0136] In an implementation, a source region SE1, a channel region AC1 (or active region), and a drain region DE1 of the silicon transistor S-TFT may be formed of the first semiconductor pattern SC1. The source region SE1 and the drain region DE1 may extend from the channel region AC1 in opposite directions to each other.

[0137] In an embodiment, the first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the first semiconductor pattern SC1. The first insulating layer 10 may be an inorganic layer. The first insulating layer 10 may have a single-layer structure of a silicon oxide layer, however, it should not be limited thereto or thereby. The inorganic layer of the circuit layer DP-CL described later may have a single-layer or multi-layer structure, and may include at least one of silicon nitride, silicon oxynitride, and silicon oxide, however, it should not be limited thereto or thereby.

[0138] In an embodiment, a gate (or gate electrode) GT1 of the silicon transistor S-TFT may be disposed on the first insulating layer 10. The gate GT1 may be a portion of a metal pattern. The gate GT1 may overlap the channel region AC1. The gate GT1 may be used as a mask in a process of doping the first semiconductor pattern SC1. The first electrode CE10 of the capacitor Cst may be disposed on the first insulating layer 10. Figure 6 Unlike what is shown, the gate electrode GT1 and the first electrode CE10 may be provided integrally with each other.

[0139] In an embodiment, the second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the gate GT1. An upper electrode may be further disposed on the second insulating layer 20 to overlap the gate GT1. The second electrode CE20 may be disposed on the second insulating layer 20 to overlap the first electrode CE10. When viewed in a plane, the upper electrode may be disposed integrally with the second electrode CE20.

[0140] In an embodiment, the second shielding electrode BML2 may be disposed on the second insulating layer 20. The second shielding electrode BML2 may be disposed to correspond to the oxide transistor O-TFT. According to an embodiment, the second shielding electrode BML2 may be omitted. According to an embodiment, the first shielding electrode BML1 may extend to a lower portion of the oxide transistor O-TFT and may replace the second shielding electrode BML2.

[0141] In an embodiment, the third insulating layer 30 may be disposed on the second insulating layer 20. The second semiconductor pattern SC2 may be disposed on the third insulating layer 30. The second semiconductor pattern SC2 may include a channel region AC2 of the oxide transistor O-TFT. The second semiconductor pattern SC2 may include a metal oxide semiconductor. The second semiconductor pattern SC2 may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ).

[0142] In an embodiment, the metal oxide semiconductor may include a plurality of regions SE2, AC2, and DE2 that are distinguished from each other according to whether the transparent conductive oxide is reduced. The conductivity of the region in which the transparent conductive oxide is reduced (hereinafter, referred to as the reduction region) is greater than the conductivity of the region in which the transparent conductive oxide is not reduced (hereinafter, referred to as the non-reduction region). The reduction region may substantially serve as a source / drain or signal line of a transistor. The non-reduction region may substantially correspond to a semiconductor region (or channel) of a transistor. In other words, a portion of the second semiconductor pattern SC2 may be a semiconductor region of a transistor, another portion of the second semiconductor pattern SC2 may be a source region SE2 / drain region DE2 of the transistor, and the remainder of the second semiconductor pattern SC2 may be a signal transmission region.

[0143] In an embodiment, a fourth insulating layer 40 may be disposed on the third insulating layer 30. Figure 6 As shown, the fourth insulating layer 40 may cover the second semiconductor pattern SC2. According to an embodiment, the fourth insulating layer 40 may be an insulating pattern that overlaps the gate electrode GT2 of the oxide transistor O-TFT and exposes the source region SE2 and the drain region DE2.

[0144] In an embodiment, the gate GT2 of the oxide transistor O-TFT may be disposed on the fourth insulating layer 40. The gate GT2 of the oxide transistor O-TFT may be a part of the metal pattern. The gate GT2 of the oxide transistor O-TFT may overlap with the channel region AC2.

[0145] In an implementation, the fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the gate GT2. Each of the first to fifth insulating layers 10 to 50 may be an inorganic layer, respectively.

[0146] In an embodiment, the first connection pattern CNP1 and the second connection pattern CNP2 may be disposed on the fifth insulating layer 50. The first connection pattern CNP1 and the second connection pattern CNP2 may be formed by the same process, and therefore, the first connection pattern CNP1 and the second connection pattern CNP2 may include the same material and the same stack structure. The first connection pattern CNP1 may be connected to the drain region DE1 of the silicon transistor S-TFT via a first pixel contact hole PCH1 defined to pass through each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50. The second connection pattern CNP2 may be connected to the source region SE2 of the oxide transistor O-TFT via a second pixel contact hole PCH2 defined to pass through each of the fourth insulating layer 40 and the fifth insulating layer 50. The connection relationship of the first connection pattern CNP1 and the second connection pattern CNP2 relative to the silicon transistor S-TFT and the oxide transistor O-TFT should not be limited thereto or thereby.

[0147] In an embodiment, the sixth insulating layer 60 may be disposed on the fifth insulating layer 50. The third connection pattern CNP3 may be disposed on the sixth insulating layer 60. The third connection pattern CNP3 may be connected to the first connection pattern CNP1 via a third pixel contact hole PCH3 defined to pass through the sixth insulating layer 60. The data line DL may be disposed on the sixth insulating layer 60. The seventh insulating layer 70 may be disposed on the sixth insulating layer 60 and may cover the third connection pattern CNP3 and the data line DL. The third connection pattern CNP3 and the data line DL may be formed by the same process, and therefore, the third connection pattern CNP3 and the data line DL may include the same material and the same stack structure. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be an organic layer.

[0148] In an embodiment, the first shielding electrode BML1, the gate electrode GT1 of the silicon transistor S-TFT, the second electrode CE20, and the gate electrode GT2 of the oxide transistor O-TFT may include molybdenum (Mo) having good heat resistance, an alloy including molybdenum (Mo), titanium (Ti), or an alloy including titanium (Ti). The first connection pattern CNP1 and the second connection pattern CNP2 may include aluminum having high conductivity. The first connection pattern CNP1 and the second connection pattern CNP2 may have a three-layer structure of titanium / aluminum / titanium.

[0149] In an embodiment, the light emitting element LD may include an anode (or first electrode) AE, a light emitting layer EL, and a cathode (or second electrode) CE. The anode AE ​​of the light emitting element LD may be disposed on the seventh insulating layer 70. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE ​​may have a stacked structure of ITO / Ag / ITO stacked sequentially. The positions of the anode AE ​​and the cathode CE may be interchanged.

[0150] In an embodiment, the pixel defining layer PDL may be disposed on the seventh insulating layer 70. The pixel defining layer PDL may be an organic layer. The pixel defining layer PDL may have a light absorbing property and may have a black color. As an example, the pixel defining layer PDL may include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal material such as chromium, or a metal oxide. The pixel defining layer PDL may correspond to a light blocking pattern having a light blocking property.

[0151] In an embodiment, the pixel defining layer PDL may cover a portion of the anode AE. As an example, an opening PDL-OP may be defined by the pixel defining layer PDL to expose a portion of the anode AE. The light emitting area LA may be defined to correspond to the opening PDL-OP. In an embodiment, a hole control layer may be provided between the anode AE ​​and the light emitting layer EL. The hole control layer may include a hole transport layer and may further include a hole injection layer. The electron control layer may be provided between the light emitting layer EL and the cathode CE. The electron control layer may include an electron transport layer and may further include an electron injection layer.

[0152] In an embodiment, the encapsulation layer TFE may cover the light emitting element LD. The encapsulation layer TFE may include a first encapsulation insulating layer IL1, a second encapsulation insulating layer IL2, and a third encapsulation insulating layer IL3. However, the present invention should not be limited thereto or thereby, and in an embodiment, the encapsulation layer TFE may also include a plurality of inorganic layers and a plurality of organic layers.

[0153] In an embodiment, the first encapsulation insulating layer IL1 may be an inorganic layer. The first encapsulation insulating layer IL1 may prevent external moisture or oxygen from entering the light emitting element LD. As an example, the first encapsulation insulating layer IL1 may include silicon nitride, silicon oxide, or a combination thereof. The first encapsulation insulating layer IL1 may be formed by a chemical vapor deposition process.

[0154] In an embodiment, the second encapsulation insulating layer IL2 may be an organic layer. The second encapsulation insulating layer IL2 may be disposed on the first encapsulation insulating layer IL1 and may be in contact with the first encapsulation insulating layer IL1. The second encapsulation insulating layer IL2 may provide a flat surface on the first encapsulation insulating layer IL1. Uneven portions formed on the upper surface of the first encapsulation insulating layer IL1 or particles present on the upper surface of the first encapsulation insulating layer IL1 may be covered by the second encapsulation insulating layer IL2, and thus, the surface state of the upper surface of the first encapsulation insulating layer IL1 may be prevented from affecting the components formed on the second encapsulation insulating layer IL2. In addition, the second encapsulation insulating layer IL2 may relieve stress between layers in contact with each other. The second encapsulation insulating layer IL2 may be formed by a solution process such as a spin coating process, a slit coating process, or an inkjet process.

[0155] In an embodiment, the third encapsulation insulating layer IL3 may be disposed on the second encapsulation insulating layer IL2 and may cover the second encapsulation insulating layer IL2. The third encapsulation insulating layer IL3 may be stably formed on a relatively flat surface compared to being placed on the first encapsulation insulating layer IL1. The third encapsulation insulating layer IL3 may encapsulate moisture emitted from the second encapsulation insulating layer IL2 and may prevent moisture from leaking to the outside.

[0156] In an embodiment, the third encapsulation insulating layer IL3 may be optically transparent. The third encapsulation insulating layer IL3 may have a transmittance equal to or greater than about 90% in the visible light wavelength range. The third encapsulation insulating layer IL3 may have a relatively higher transmittance than the first encapsulation insulating layer IL1. The third encapsulation insulating layer IL3 may be an inorganic layer. The third encapsulation insulating layer IL3 may include silicon oxide (SiO x ) or silicon oxynitride (SiON). The third encapsulation insulating layer IL3 may be formed by a chemical vapor deposition process. Meanwhile, each of the first encapsulation insulating layer IL1, the second encapsulation insulating layer IL2, and the third encapsulation insulating layer IL3 may include a plurality of layers and should not be particularly limited.

[0157] In an embodiment, the input sensing layer ISL may include at least one conductive layer (or at least one sensor conductive layer) and at least one insulating layer (or at least one sensor insulating layer). In an embodiment, the input sensing layer ISL may include a first sensor insulating layer IS-IL1, a first conductive layer ICL1, a second sensor insulating layer IS-IL2, a second conductive layer ICL2, and a third sensor insulating layer IS-IL3. Figure 6 The conductive lines of the first conductive layer ICL1 and the conductive lines of the second conductive layer ICL2 are schematically shown.

[0158] In an embodiment, the first sensor insulating layer IS-IL1 may be directly disposed on the display panel DP. The first sensor insulating layer IS-IL1 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. Each of the first conductive layer ICL1 and the second conductive layer ICL2 may have a single-layer structure or a multi-layer structure of a plurality of layers stacked in the third direction DR3. The first conductive layer ICL1 and the second conductive layer ICL2 may include conductive wires defining electrodes in a grid shape. The conductive wires of the first conductive layer ICL1 and the conductive wires of the second conductive layer ICL2 may be connected to each other via contact holes defined to pass through the second sensor insulating layer IS-IL2, or may not be connected to each other. The connection relationship between the conductive wires of the first conductive layer ICL1 and the conductive wires of the second conductive layer ICL2 may be determined according to the type of sensor formed as the input sensing layer ISL.

[0159] In an embodiment, the first conductive layer ICL1 and the second conductive layer ICL2 having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium zinc tin oxide (ITZO), etc. In addition, the transparent conductive layer may include a conductive polymer such as PEDOT, a metal nanowire, graphene, etc.

[0160] In an embodiment, the first conductive layer ICL1 and the second conductive layer ICL2 having a multi-layer structure may include a plurality of metal layers. The metal layer may have a three-layer structure of titanium / aluminum / titanium. The first conductive layer ICL1 and the second conductive layer ICL2 having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer. The second sensor insulating layer IS-IL2 may be disposed between the first conductive layer ICL1 and the second conductive layer ICL2. The third sensor insulating layer IS-IL3 may cover the second conductive layer ICL2. According to an embodiment, the third sensor insulating layer IS-IL3 may be omitted. The second sensor insulating layer IS-IL2 and the third sensor insulating layer IS-IL3 may include an inorganic layer or an organic layer.

[0161] Figure 7 is a plan view of a display panel DP according to an embodiment. In detail, Figure 7 is a plan view of the display panel DP when viewed in the third direction DR3.

[0162] In the implementation mode and with reference to Figure 7 The pad electrode PD may be disposed on the rear surface of the display panel DP. In detail, the pad electrode PD may be disposed in the pad area PA. The pad electrode PD may be disposed in plural. The pad electrode PD may be arranged in the second direction DR2.

[0163] In an embodiment, the signal lines SGL (refer to Figure 5 ) can be electrically connected to the Figure 3 As an example, in an embodiment, the signal line SGL may be arranged in the pad area PA and may be connected to the pad electrode PD spaced apart from the signal line SGL in the first direction DR1 through the connection electrode. Although not shown in the figure, the pad electrode PD may be provided on the rear surface of the display panel DP and may be electrically connected to the flexible circuit board FCB (refer to Figure 2 ). The connection between the circuit board FCB and the signal line SGL will be described in detail later.

[0164] Figure 8 is an enlarged plan view of a portion of a display device according to an embodiment. Fig. 9A According to the implementation method Figure 8 A cross-sectional view of a portion of the display device taken along line II-II'. Fig. 9B According to the implementation method Figure 8 A cross-sectional view of a portion of the display device taken along line II-II'. Figure 8 , Fig. 9A and Fig. 9B is a view showing a structure in which a circuit board FCB is attached to a display panel DP according to an embodiment.

[0165] In the implementation mode and with reference to Figure 8 and Fig. 9A The display device DD may include a plurality of pad electrodes PD. The pad electrodes PD may be connected to Figure 6 The first shielding electrode BML1 shown is disposed on the same layer. The pad electrode PD and the first shielding electrode BML1 may be formed by the same process. As an example, by disposing a single metal layer on the base layer BL and patterning the metal layer, the pad electrode PD and the first shielding electrode BML1 may be formed in the non-display area DM-NDA and the display area DM-DA, respectively. Although not shown in the figure, the pad electrode PD may be electrically connected to the display area DM-DA via a separate connection electrode. Figure 5The data line DL is shown.

[0166] In an embodiment, the pad electrode PD may be exposed to the outside through the lower surface BL-LS of the base layer BL to allow the circuit board FCB to be coupled to the pad electrode PD on the rear surface side of the display panel DP, however, the present invention should not be limited thereto or thereby. According to an embodiment, the pad electrode PD may be exposed to the outside through a contact hole rather than directly exposed to the outside. The lower surface BL-LS of the base layer BL may face the upper surface BL-US of the base layer BL in the third direction DR3.

[0167] In an embodiment, the base layer BL may include a first sub-base layer SBL1, a first base inorganic layer BIL1, a second sub-base layer SBL2, and a second base inorganic layer BIL2 sequentially stacked. The first base inorganic layer BIL1 may be disposed on the first sub-base layer SBL1, the second sub-base layer SBL2 may be disposed on the first base inorganic layer BIL1, and the second base inorganic layer BIL2 may be disposed on the second sub-base layer SBL2.

[0168] In an embodiment, the first sub-base layer SBL1 and the second sub-base layer SBL2 may include a synthetic resin material, such as polyimide. The first base inorganic layer BIL1 and the second base inorganic layer BIL2 may include an inorganic material. As an example, the first base inorganic layer BIL1 and the second base inorganic layer BIL2 may include silicon nitride, silicon oxynitride, or silicon oxide. The second base inorganic layer BIL2 may include a plurality of layers. As an example, the second base inorganic layer BIL2 may include a first sub-base inorganic layer BIL-S1 and a second sub-base inorganic layer BIL-S2. The first sub-base inorganic layer BIL-S1 may include amorphous silicon (a-Si). The second sub-base inorganic layer BIL-S2 may include an inorganic material. As an example, in an embodiment, the second sub-base inorganic layer BIL-S2 may include silicon nitride, silicon oxynitride, or silicon oxide.

[0169] In an embodiment, the base layer BL may be provided with a base opening (or first opening) BL-OP defined therethrough to expose the pad electrode PD to the outside. The base layer BL may include a first side surface B-S1 and a second side surface B-S2 facing the first side surface B-S1 to define the base opening BL-OP. The first side surface B-S1 and the second side surface B-S2 may be referred to as one side surface and the other side surface of the base layer BL. Reference Figure 8, the basic opening BL-OP may be provided in plurality to correspond to the pad electrode PD. The width of the basic opening BL-OP in the first direction DR1 may be uniform in the third direction DR3, however, it should not be limited thereto or thereby. According to an embodiment, the width of the basic opening BL-OP in the first direction DR1 may gradually increase in the third direction DR3.

[0170] In an embodiment, the base opening BL-OP may include a plurality of sub-openings BL-SOP1, BL-SOP2, BL-SOP3, and BL-SOP4. The sub-openings BL-SOP1, BL-SOP2, BL-SOP3, and BL-SOP4 may include a first sub-opening BL-SOP1, a second sub-opening BL-SOP2, a third sub-opening BL-SOP3, and a fourth sub-opening BL-SOP4. The first sub-opening BL-SOP1 may be defined to pass through the second base inorganic layer BIL2, the second sub-opening BL-SOP2 may be defined to pass through the second sub-base layer SBL2, the third sub-opening BL-SOP3 may be defined to pass through the first base inorganic layer BIL1, and the fourth sub-opening BL-SOP4 may be defined to pass through the first sub-base layer SBL1. The pad electrode PD may be exposed to the outside via the second sub-opening BL-SOP2 defined to pass through the second sub-base layer SBL2.

[0171] In an embodiment, the pad electrode PD may extend in the first direction DR1 and may be arranged in the second direction DR2, however, the shape and arrangement of the pad electrode PD should not be limited thereto or thereby. The pad electrode PD may overlap the non-display area DM-NDA. As an example, in an embodiment, the pad electrode PD may be arranged in the pad area PA.

[0172] In the implementation mode and Fig. 9A As shown, a portion of the pad electrode PD may be disposed in the base opening BL-OP. The base opening BL-OP may completely penetrate the base layer BL. The pad electrode PD may be embedded in the circuit layer DP-CL disposed on the base layer BL. The pad electrode PD included in the circuit layer DP-CL may be exposed to the outside via the base opening BL-OP completely penetrating the base layer BL.

[0173] In an embodiment, the pad electrode PD may be disposed on the base layer BL, and may include a first pad portion PD-P1 that does not overlap with the base opening BL-OP and a second pad portion PD-P2 that overlaps with the base opening BL-OP. The first pad portion PD-P1 may be directly disposed on the second base inorganic layer BIL2. The first pad portion PD-P1 and the second pad portion PD-P2 may overlap with each other. Figure 6The first shielding electrode BML1 on the base layer BL is shown to be formed by the same process. The first pad portion PD-P1 and the second pad portion PD-P2 may include the same material as the first shielding electrode BML1. The first pad portion PD-P1 and the second pad portion PD-P2 may include a metal material, such as molybdenum.

[0174] In an implementation, the second pad portion PD-P2 may be disposed in the pad area PA. Figure 8 The pad electrode PD shown may correspond to Fig. 9A The second pad portion PD-P2 is shown. The second pad portion PD-P2 may be disposed in the first sub-opening BL-SOP1. The second pad portion PD-P2 may be exposed to the outside through the second sub-opening BL-SOP2.

[0175] In an embodiment, although not shown in the drawings, the display panel DP may include a first voltage line and a second voltage line, which receive different voltages from each other. The first voltage line may receive a first voltage, and the second voltage line may receive a second voltage higher than the first voltage. According to an embodiment, the first voltage may be a first power supply voltage, and the second voltage may be a second power supply voltage.

[0176] In an embodiment, the circuit board FCB may be attached to the display panel DP after being bent to the rear surface of the display panel DP. The adhesive layer AF may be provided between the circuit board FCB and the lower surface BL-LS of the base layer BL. The circuit board FCB may be fixed to the lower surface BL-LS of the base layer BL by the adhesive layer AF. As an example, the circuit board FCB may be provided to be spaced apart from the base opening BL-OP.

[0177] In an embodiment, the circuit board FCB may include a base film BF and a bump electrode BMP disposed on the base film BF. The base film BF may be formed as a single body and may be electrically connected to a plurality of bump electrodes BMP. In this case, the base film BF may include a plurality of wires therein, however, it should not be limited thereto or thereby. According to an embodiment, the base film BF may be attached only to the bump electrode BMP and may not be electrically connected to the bump electrode BMP. The base film BF may include a synthetic resin material, such as polyimide. The bump electrode BMP may be disposed on the base film BF.

[0178] In an embodiment, when viewed in a plane, the bump electrode BMP may overlap with the first pad portion PD-P1 of the pad electrode PD, but not overlap with the second pad portion PD-P2 of the pad electrode PD. The bump electrode BMP may be electrically connected to the pad electrode PD. The bump electrode BMP may be formed to correspond to the pad electrode PD. That is, one bump electrode BMP may correspond to one pad electrode PD. The bump electrode BMP may extend in the first direction DR1 and may be arranged in the second direction DR2. When viewed in a plane, the size of the pad electrode PD may be larger than the size of the bump electrode BMP.

[0179] In an embodiment, the adhesive layer AF may be disposed between the base film BF and the pad electrode PD. According to an embodiment, the adhesive layer AF may include a non-conductive material. As an example, the adhesive layer AF may include a non-conductive film. The edge of the adhesive layer AF may be aligned substantially parallel to the first side surface B-S1 of the base layer BL in the third direction DR3.

[0180] In an embodiment, the bump electrode BMP may be electrically connected to the pad electrode PD. Figure 2 ) may further include a metal pattern MP that electrically connects the bump electrode BMP and the pad electrode PD. The metal pattern MP may be disposed on the pad electrode PD and the bump electrode BMP, and may electrically connect the pad electrode PD and the bump electrode BMP. The metal pattern MP may be provided in a number corresponding to each of the number of the pad electrodes PD and the number of the bump electrodes BMP.

[0181] In an embodiment, each of the metal patterns MP can be obtained by curing metal ink. The metal pattern MP may include solder paste. The metal pattern MP may be formed of a metal ink containing silver or copper. The metal pattern MP may be arranged to correspond to the pad electrode PD exposed by the base opening BL-OP. The metal pattern MP may be formed by curing the metal ink and patterning the cured metal ink. The metal pattern MP may be formed at a low temperature, and the pad electrode PD and the bump electrode BMP may be combined and electrically connected without performing a pressing process at a high temperature.

[0182] In an embodiment, each of the metal patterns MP may include a first portion MP-P1 in contact with the pad electrode PD and a second portion MP-P2 in contact with the bump electrode BMP of the circuit board FCB. The first portion MP-P1 may overlap with the base opening BL-OP and may be disposed in the base opening BL-OP. In detail, the first portion MP-P1 may be disposed in the second sub-opening BL-SOP2, the third sub-opening BL-SOP3, and the fourth sub-opening BL-SOP4, respectively. The first portion MP-P1 may be in contact with the pad electrode PD at the boundary between the first sub-opening BL-SOP1 and the second sub-opening BL-SOP2, respectively. The first portion MP-P1 may be in direct contact with the first side surface B-S1 and the second side surface B-S2 in the base opening BL-OP. That is, the first portion MP-P1 may be disposed to fill the base opening BL-OP and may cover the first side surface B-S1 and the second side surface B-S2.

[0183] In an embodiment, the second portion MP-P2 may be arranged not to overlap with the base opening BL-OP. The second portion MP-P2 may be arranged to cover the bump electrode BMP exposed to the outside. One end of the second portion MP-P2 may be in contact with the side surface of the base film BF. As another example, the one end of the second portion MP-P2 may not be in contact with the side surface of the base film BF. According to an embodiment, the one end of the second portion MP-P2 may be formed to completely cover the side surface of the base film BF. The first portion MP-P1 and the second portion MP-P2 may be formed integrally with each other. That is, in the metal pattern MP, the first portion MP-P1 and the second portion MP-P2 are portions that are distinguished from each other based on the base opening BL-OP for ease of explanation. The pad electrode PD may be electrically connected to the bump electrode BMP through the first portion MP-P1 and the second portion MP-P2 that are integrally arranged with each other.

[0184] In an embodiment, the pad electrode PD embedded in the circuit layer DP-CL may be exposed through the base opening BL-OP that completely penetrates the base layer BL, and the metal pattern MP may be directly connected to the pad electrode PD exposed through the base opening BL-OP. Figure 2 ) method, a connection electrode may not be required between the pad electrode PD and the metal pattern MP, and thus, the manufacturing method of the display device DD may be simplified.

[0185] In the implementation mode and with reference to Fig. 9B , display device DD (reference Figure 2) may further include an adhesive resin AR, at least a portion of which is disposed in the base opening BL-OP. The adhesive resin AR may include an optically transparent resin. However, the material used for the adhesive resin AR should not be limited thereto or thereby, and may include a conventional adhesive. As an example, the adhesive resin AR may include a pressure-sensitive adhesive (PSA) or an optically clear adhesive (OCA).

[0186] In an embodiment, a portion of the adhesive resin AR may be disposed in the base opening BL-OP, and another portion of the adhesive resin AR may be disposed outside the base opening BL-OP and may cover the metal pattern MPa. The adhesive resin AR and the metal pattern MPa may be disposed to fill the base opening BL-OP. The metal pattern MPa may be in contact with the first side surface B-S1 and may cover the first side surface B-S1. A portion of the adhesive resin AR may be in contact with the second side surface B-S2 and may cover the second side surface B-S2. The adhesive resin AR may cover the metal pattern MPa exposed to the outside. Since the adhesive resin AR and the metal pattern MPa are disposed to completely fill the base opening BL-OP, when the display device DD (reference Figure 2 ) receives an external impact and bends around the base opening BL-OP, the possibility of cracks occurring inside the display device DD can be reduced.

[0187] Fig. 10A and Fig. 10B According to the implementation method Figure 8 A cross-sectional view of a portion of the display device taken along line II-II'. Fig. 10A and Fig. 10B In the Fig. 9A and Fig. 9B Detailed description of the elements that are the same as the elements in .

[0188] In the implementation mode and with reference to Fig. 10A , a second opening D-OP may be formed through the circuit layer DP-CLa. In detail, the second opening D-OP may be formed to pass through the barrier layer BRLa, the buffer layer BFLa, and the first insulating layer 10a of the circuit layer DP-CLa. The pad electrode PDa disposed on the first insulating layer 10a may be exposed to the outside via the second opening D-OP. When viewed in a plane, the second opening D-OP may overlap with the base opening BL-OP. The width of the second opening D-OP in the first direction DR1 may be substantially the same as the width of the base opening BL-OP in the first direction DR1. The second opening D-OP may be formed by the same process as the base opening BL-OP. That is, the second opening D-OP and the base opening BL-OP may have a continuous hole structure.

[0189] In an embodiment, the pad electrode PDa may be disposed on the first insulating layer 10a. Figure 6 The gate electrode GT1 (corresponding to the gate electrode GT1 described above) on the first insulating layer 10 shown in FIG. 1 is formed into the pad electrode PDa by the same process. That is, the pad electrode PDa and the gate electrode GT1 (refer to FIG. 1 ) are formed into the pad electrode PDa by the same process. Figure 6 ) may be disposed on the same layer. The pad electrode PDa may include the same material as the gate electrode GT1. The pad electrode PDa may include molybdenum (Mo), an alloy including molybdenum (Mo), titanium (Ti), or an alloy including titanium (Ti). However, the present invention should not be limited thereto or thereby, and the pad electrode PDa may be disposed on the second shielding electrode BML2 (reference Figure 6 ) or a gate electrode GT2 (corresponding to the gate electrode GT2 described above) disposed on the fourth insulating layer 40 (refer to Figure 6 ) are formed by the same process.

[0190] In an embodiment, the metal pattern MPb may include a first portion MP-P1a in contact with the pad electrode PDa and a second portion MP-P2 in contact with the bump electrode BMP of the circuit board FCB. The first portion MP-P1a may be disposed in the second opening D-OP and the base opening BL-OP. The first portion MP-P1a may be formed to fill the second opening D-OP and the base opening BL-OP. The pad electrode PDa may be electrically connected to the bump electrode BMP through the first portion MP-P1a and the second portion MP-P2.

[0191] In the implementation mode and with reference to Fig. 10B , a second opening D-OPa may be formed through the circuit layer DP-CLb. In detail, the second opening D-OPa may be formed to pass through the barrier layer BRLa, the buffer layer BFLa, and each of the first insulating layer 10a, the second insulating layer 20a, the third insulating layer 30a, the fourth insulating layer 40a, and the fifth insulating layer 50a of the circuit layer DP-CLb. The pad electrode PDb disposed on the fifth insulating layer 50a may be exposed through the second opening D-OPa. When viewed in a plane, the second opening D-OPa may overlap with the base opening BL-OP. The width of the second opening D-OPa in the first direction DR1 may be substantially the same as the width of the base opening BL-OP in the first direction DR1. The second opening D-OPa may be formed by the same process as the base opening BL-OP. That is, the second opening D-OPa and the base opening BL-OP may have a continuous hole structure.

[0192] In an embodiment, the pad electrode PDb may be disposed on the fifth insulating layer 50a. Figure 6The first connection pattern CNP1 (or connection pattern) on the fifth insulating layer 50 shown is formed by the same process. The pad electrode PDb may include the same material as the first connection pattern CNP1. The pad electrode PDb may include aluminum, which has high conductivity. The pad electrode PDb may have a three-layer structure of titanium / aluminum / titanium, however, the present invention should not be limited thereto or thereby. According to an embodiment, the pad electrode PDb may be disposed on the sixth insulating layer 60 (reference Figure 6 ) on the third connection pattern CNP3 (reference Figure 6 ) are formed by the same process.

[0193] In an embodiment, the metal pattern MPc may include a first portion MP-P1b in contact with the pad electrode PDb and a second portion MP-P2 in contact with the bump electrode BMP of the circuit board FCB. The first portion MP-P1b may be disposed in the second opening D-OPa and the base opening BL-OP. The first portion MP-P1b may be formed to fill the second opening D-OPa and the base opening BL-OP. The pad electrode PDb may be electrically connected to the bump electrode BMP through the first portion MP-P1b and the second portion MP-P2.

[0194] Fig.11 is a flowchart illustrating a method of manufacturing a display device according to an embodiment. FIG. 12A to FIG. 12I is a view showing a process of a method for manufacturing a display device according to an embodiment. Fig.11 and FIG. 12A to FIG. 12I In the same reference numerals, Figures 1 to 10B The same elements are described herein, and therefore, detailed description of the same elements will be omitted.

[0195] In the implementation mode and with reference to Fig.11 and FIG. 12A to FIG. 12I , display device DD (reference Figure 2 ) may include forming a preliminary base layer BL-P (step S100), forming a circuit layer DP-CL (step S200), forming a base layer BL (step S300), placing a circuit board FCB (step S400) and forming a metal pattern MP (step S500).

[0196] In the implementation mode and with reference to Fig.11 and FIG. 12A to FIG. 12D , a step of forming a preliminary base layer BL-P (step S100 ) may be performed.

[0197] In the implementation mode and with reference to Fig. 12A , forming a preliminary base layer BL-P (reference Fig.12D) (step S100 ) may include: forming a first preliminary sub base layer SBL1 -P; and forming a first preliminary base inorganic layer BIL1 -P on the first preliminary sub base layer SBL1 -P.

[0198] In the implementation mode and with reference to Fig. 12B , forming a preliminary base layer BL-P (reference Fig.12D ) (step S100) may also include: performing a first preliminary basic inorganic layer BIL1-P (reference Fig. 12A ) is first initially etched. In detail, a photoresist layer PR may be placed on the first preliminary base inorganic layer BIL1-P, and a first initial etching of the first preliminary base inorganic layer BIL1-P may be performed, and thus a third sub-opening BL-SOP3 may be formed. When a base opening BL-OP (refer to Figure 12G ), a first preliminary etching of the first preliminary base inorganic layer BIL1-P may be performed to prevent residues from remaining on the first preliminary base inorganic layer BIL1-P. According to an embodiment, the first preliminary etching may be omitted. Although not shown in the figure, a preliminary photoresist layer may be provided on the first preliminary base inorganic layer BIL1-P, and the preliminary photoresist layer may be patterned using a mask to form a photoresist layer PR. The first base inorganic layer BIL1 may be formed after the first preliminary etching, and the third sub-opening BL-SOP3 is defined to pass through the first base inorganic layer BIL1.

[0199] In the implementation mode and with reference to Fig. 12C , forming the preliminary base layer BL-P (step S100) may further include: forming a second preliminary sub-base layer SBL2-P on the first base inorganic layer BIL1; and forming a second preliminary base inorganic layer BIL2-P on the second preliminary sub-base layer SBL2-P. The second preliminary base inorganic layer BIL2-P may include a plurality of layers. As an example, the second preliminary base inorganic layer BIL2-P may include a first sub-preliminary inorganic layer BIL-P1 and a second sub-preliminary inorganic layer BIL-P2 disposed on the first sub-preliminary inorganic layer BIL-P1.

[0200] In the implementation mode and with reference to Fig.12D The forming of the preliminary base layer BL-P (step S100) may further include: forming a second preliminary base inorganic layer BIL2-P (reference Fig. 12C ) is subjected to secondary preliminary etching. In detail, the first sub-opening BL-SOP1 may be formed by placing a photoresist layer PR on the second preliminary base inorganic layer BIL2-P and performing secondary preliminary etching on the second preliminary base inorganic layer BIL2-P. When the base opening BL-OP is formed in a subsequent process (see Figure 12G), a secondary preliminary etching of the second preliminary base inorganic layer BIL2-P may be performed to prevent residues from remaining on the second preliminary base inorganic layer BIL2-P. According to an embodiment, the secondary preliminary etching may be omitted. Although not shown in the drawings, a preliminary photoresist layer may be provided on the second preliminary base inorganic layer BIL2-P, and the preliminary photoresist layer may be patterned using a mask to form a photoresist layer PR. The second base inorganic layer BIL2 may be formed after the secondary preliminary etching, and the first sub-opening BL-SOP1 is defined to pass through the second base inorganic layer BIL2. The second base inorganic layer BIL2 may include a first sub-base inorganic layer BIL-S1 and a second sub-base inorganic layer BIL-S2.

[0201] In the implementation mode and with reference to FIG. 12A to FIG. 12D , a preliminary base layer BL-P including a first preliminary sub base layer SBL1-P, a first base inorganic layer BIL1, a second preliminary sub base layer SBL2-P, and a second base inorganic layer BIL2 may be provided.

[0202] In the implementation mode and with reference to Fig.11 , Fig.12E and Fig.12F , the step of forming the circuit layer DP-CL (step S200 ) may be performed after forming the preliminary base layer BL-P (step S100 ).

[0203] In the implementation mode and with reference to Fig.12E , forming the circuit layer DP-CL (step S200) may include: placing a pad electrode PD on the preliminary base layer BL-P. A portion of the pad electrode PD may be disposed on the second base inorganic layer BIL2, and another portion of the pad electrode PD may be disposed on the second preliminary sub-base layer SBL2-P. Specifically, the other portion of the pad electrode PD may be disposed in the first sub-opening BL-SOP1. Figure 6 and Fig.12E , the pad electrode PD and the first shielding electrode BML1 may be formed by the same process. As an example, in an embodiment, each of the pad electrode PD and the first shielding electrode BML1 may be formed by forming a metal layer on the preliminary base layer BL-P and patterning the metal layer.

[0204] In the implementation mode and with reference to Fig.12F , forming the circuit layer DP-CL (step S200) may further include: placing a barrier layer BRL (or an inorganic layer) on the pad electrode PD. In detail, after placing the barrier layer BRL on the pad electrode PD, a process of inverting the structure including the preliminary base layer BL-P and the circuit layer DP-CL may be performed. Fig.12F It is not shown in detail, but the circuit layer DP-CL may have Fig. 9A The same configuration as shown in the circuit layer DP-CL.

[0205] In the implementation mode and with reference to Fig.11 , Fig.12F and Figure 12G , the step of forming the base layer BL (step S300 ) may be performed after forming the circuit layer DP-CL (step S200 ).

[0206] In the implementation mode and with reference to Fig.12F and Figure 12G , forming the base layer BL (step S300) may include: etching the preliminary base layer BL-P. In detail, the base opening BL-OP may be formed by placing a photoresist layer PR on the preliminary base layer BL-P and etching the preliminary base layer BL-P. The pad electrode PD may be exposed via the base opening BL-OP that completely penetrates the base layer BL. The width of the pad electrode PD exposed to the outside in the first direction DR1 may be the same as the width of the base opening BL-OP in the first direction DR1.

[0207] In the implementation mode and with reference to Fig.11 and Fig.12H , the step of placing the circuit board FCB (step S400 ) may be performed after forming the base layer BL (step S300 ).

[0208] In the implementation mode and with reference to Fig.12H , the circuit board FCB may be disposed on the lower surface BL-LS of the base layer BL. The adhesive layer AF may be disposed between the circuit board FCB and the lower surface BL-LS of the base layer BL. The circuit board FCB may be fixed to the lower surface BL-LS of the base layer BL by the adhesive layer AF.

[0209] In an embodiment, the circuit board FCB may include a base film BF and a bump electrode BMP disposed on the base film BF. The base film BF may be formed as a single body and may be electrically connected to the bump electrode BMP. The bump electrode BMP may be fixed to the lower surface BL-LS of the base layer BL by an adhesive layer AF. Although not shown in the figure, the circuit board FCB may be attached to the lower surface BL-LS of the base layer BL when in a bent state.

[0210] In the implementation mode and with reference to Fig.11 and Fig.12I , the step of forming the metal pattern MP (step S500 ) may be performed after placing the circuit board FCB (step S400 ).

[0211] In the implementation mode and with reference to Fig.12I, the metal pattern MP may include a first portion MP-P1 in contact with the pad electrode PD and a second portion MP-P2 in contact with the bump electrode BMP of the circuit board FCB. The first portion MP-P1 may overlap with the base opening BL-OP and may be disposed in the base opening BL-OP. The second portion MP-P2 may be disposed so as not to overlap with the base opening BL-OP. The second portion MP-P2 may be disposed so as not to overlap with the base opening BL-OP. The second portion MP-P2 may be disposed so as to cover the bump electrode BMP exposed to the outside. The metal pattern MP may be formed by curing metal ink. The metal pattern MP may be formed by curing the metal ink at a low temperature and patterning the cured metal ink. The pad electrode PD and the bump electrode BMP may be electrically connected to each other and may be bonded to each other through the metal pattern MP.

[0212] In the implementation mode and with reference to Fig.12I and Fig. 9B , the manufacturing method of the display device DD may further include forming an adhesive resin AR for covering the metal pattern MPa in the base opening BL-OP after forming the metal pattern MPa (step S500). The adhesive resin AR may include an optically transparent resin. However, the material for the adhesive resin AR should not be limited thereto or thereby, and the adhesive resin AR may include a conventional adhesive. As an example, the adhesive resin AR may include a pressure-sensitive adhesive (PSA) or an optically clear adhesive (OCA). A portion of the adhesive resin AR may be disposed in the base opening BL-OP, and another portion of the adhesive resin AR may be disposed outside the base opening BL-OP and may cover the metal pattern MPa. The adhesive resin AR and the metal pattern MPa may be disposed to fill the base opening BL-OP.

[0213] In the implementation mode and with reference to Fig.11 and FIG. 12A to FIG. 12I , display device DD (reference Figure 2 The manufacturing method of the display device DD may include forming a base opening BL-OP that completely penetrates the base layer BL to expose the pad electrode PD embedded in the circuit layer DP-CL. Since the pad electrode PD is electrically connected to the bump electrode BMP via the metal pattern MP provided in the base opening BL-OP that completely penetrates the base layer BL, a connection electrode may not be required between the pad electrode PD and the bump electrode BMP, and as a result, the manufacturing method of the display device DD may be simplified.

[0214] FIG. 13A to FIG. 13C is a flowchart illustrating a method of manufacturing a display device according to an embodiment. FIG. 13A to FIG. 13C The process included in the step of forming the circuit layer DP-CL (step S200) is shown. FIG. 13A to FIG. 13C In the description, the same reference numerals denote Figures 1 to 12IThe same elements are described herein, and therefore, detailed description of the same elements will be omitted.

[0215] In the implementation mode and with reference to Figure 6 , Fig.12E and Fig.13A , placing the pad electrode PD on the preliminary base layer BL-P may include: forming a metal layer on the preliminary base layer BL-P (step S210); and etching the metal layer to form the pad electrode PD and the first shielding electrode (or shielding electrode) BML1 (step S220). Fig.12E When the pad electrode PD is shown, a metal layer may be formed on the preliminary base layer BL-P, and the metal layer may be patterned to form the pad electrode PD disposed in the non-display area DM-NDA and the first shielding electrode BML1 disposed in the display area DM-DA. However, the present invention should not be limited thereto or thereby, and the gate electrode GT1 disposed on the first insulating layer 10 and the first connection pattern CNP1 disposed on the fifth insulating layer 50 may be formed by patterning the metal layer.

[0216] In the implementation mode and with reference to Figure 6 , 9A to 10B as well as Fig.12E and Fig. 13B , forming the circuit layer DP-CL (step S200) may include: forming a pad electrode PDa and a gate electrode GT1 (step S230). A metal layer may be formed on the first insulating layer 10a to form Fig. 10A The pad electrode PDa is shown, and the metal layer may be patterned to form the pad electrode PDa disposed in the non-display area DM-NDA and the gate electrode GT1 disposed in the display area DM-DA.

[0217] In the implementation mode and with reference to Figure 6 , 9A to 10B , Fig.12E and Fig. 13C , forming the circuit layer DP-CL (step S200) may include: forming a pad electrode PDb and a first connection pattern (or connection pattern) CNP1 connected to the first semiconductor pattern SC1 (step S240). A metal layer may be formed on the fifth insulating layer 50a to form Fig. 10B The pad electrode PDb shown, and the metal layer may be patterned to form the pad electrode PDb disposed in the non-display area DM-NDA and the first connection pattern CNP1 disposed in the display area DM-DA.

[0218] Although the embodiments of the present invention have been described, it should be understood that the present invention should not be limited to these embodiments, but various changes and modifications may be made by those skilled in the art within the spirit and scope of the present invention.

[0219] Thus, the present invention should not be limited to any single embodiment described herein. Additionally, the embodiments or portions of these embodiments may be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A display device, comprising: A display panel for displaying images; A circuit board connected to the display panel; as well as A metal pattern electrically connects the display panel and the circuit board, Wherein, the display panel comprises: Base layer; and a circuit layer disposed on the base layer and including a pad electrode exposed to the outside via a first opening defined through the base layer, Wherein, the metal pattern comprises: a first portion overlapping the first opening and contacting the pad electrode; and The second portion does not overlap with the first opening and contacts with the circuit board.

2. The display device according to claim 1, wherein: The pad electrode comprises: a first pad portion disposed on the base layer and not overlapping the first opening; and The second pad portion overlaps the first opening.

3. The display device according to claim 2, wherein: The base layer includes: a sub-base layer in contact with the circuit board; and The base inorganic layer is arranged on the sub-base layer.

4. The display device according to claim 3, wherein: The first opening comprises: a first sub-opening defined to pass through the base inorganic layer; and A second sub-opening is defined to pass through the sub-base layer.

5. The display device according to claim 4, wherein: The second pad portion is disposed in the first sub-opening, and the second pad portion is exposed to the outside through the second sub-opening.

6. The display device according to claim 2, wherein: The circuit layer comprises: transistors; and A shielding electrode is disposed under the transistor and overlaps the semiconductor pattern of the transistor.

7. The display device according to claim 6, wherein: The first pad portion and the shielding electrode are disposed on the same layer.

8. The display device according to claim 6, wherein: The circuit layer includes an inorganic layer disposed on the base layer, the pad electrode is disposed on the inorganic layer, and the inorganic layer includes a second opening corresponding to the first opening, the pad electrode is exposed through the second opening.

9. The display device according to claim 8, wherein: The circuit layer further includes a connection pattern connected to the semiconductor pattern, wherein the first pad portion and the connection pattern are disposed on the same layer.

10. The display device according to claim 8, wherein: The transistor further includes a gate electrode overlapping the semiconductor pattern, wherein the first pad portion and the gate electrode are disposed on the same layer.

11. The display device according to claim 6, wherein: The circuit layer further includes at least one signal line connected to the transistor, wherein the pad electrode is electrically connected to the signal line.

12. The display device according to claim 1, wherein: The first portion is disposed in the first opening.

13. The display device according to claim 12, wherein: The first portion covers one side surface of the base layer defining the first opening.

14. The display device according to claim 13, further comprising an adhesive resin, at least a portion of which is disposed in the first opening, wherein The adhesive resin covers the metal pattern.

15. The display device according to claim 14, wherein: The adhesive resin covers the other side surface of the base layer facing the one side surface of the base layer.

16. The display device according to claim 14, wherein: The metal pattern and the adhesive resin are disposed to fill the first opening.

17. The display device according to claim 1, wherein: The circuit board comprises: basement membrane; and A bump electrode is provided between the base film and the base layer, wherein the bump electrode is electrically connected to the pad electrode via the metal pattern.

18. The display device according to claim 17, wherein: Each of the bump electrode and the pad electrode is provided in plural, wherein the metal pattern is provided in plural to correspond to the bump electrode and the pad electrode. 19 . The display device of claim 17 , further comprising an adhesive layer disposed between the bump electrode and the base layer.

20. The display device according to claim 1, wherein: The circuit board is disposed to be spaced apart from the first opening.

21. Electronic devices, including: case; An electronic module is disposed in the housing; as well as A display device is arranged to overlap with the electronic module, and the display device comprises: A display panel for displaying images; a circuit board connected to the display panel; and A metal pattern electrically connects the display panel and the circuit board, The display panel comprises: Base layer; and a circuit layer disposed on the base layer and including a pad electrode exposed to the outside via a first opening defined through the base layer, Wherein, the metal pattern comprises: a first portion overlapping the first opening and contacting the pad electrode; and The second portion does not overlap with the first opening and contacts with the circuit board.

22. A method for manufacturing a display device, comprising: Forming a preliminary base layer; placing pad electrodes on the preliminary base layer to form a circuit layer; etching the preliminary base layer to form a base layer, defining a first opening through the base layer to expose the pad electrode to the outside; placing a circuit board on the lower surface of the base layer; as well as A metal pattern is formed to electrically connect the pad electrode and the circuit board, wherein the metal pattern comprises: a first portion overlapping the first opening and contacting the pad electrode; and The second portion does not overlap with the first opening and contacts with the circuit board.

23. The method according to claim 22, wherein: Forming the preliminary base layer includes: forming a first preliminary sub-base layer; forming a first preliminary base inorganic layer on the first preliminary sub-base layer; forming a second preliminary sub-base layer on the first preliminary base inorganic layer; and A second preliminary base inorganic layer is formed on the second preliminary sub-base layer.

24. The method according to claim 23, wherein: Forming the preliminary base layer further includes: Before forming the second preliminary sub-base layer, performing a first preliminary etching on the first preliminary base inorganic layer to form a first base inorganic layer; and Before the pad electrode is disposed on the preliminary base layer, the second preliminary base inorganic layer is subjected to secondary preliminary etching to form a second base inorganic layer.

25. The method according to claim 24, wherein: Placing the pad electrode on the preliminary base layer includes placing the pad electrode in a sub-opening formed through the second base inorganic layer by the secondary preliminary etching.

26. The method of claim 22, wherein: Forming the circuit layer includes placing an inorganic layer on the preliminary base layer, wherein the pad electrode is disposed on the inorganic layer.

27. The method according to claim 26, wherein: Forming the base layer includes: etching the preliminary base layer to form the first opening; and The inorganic layer is etched to form a second opening corresponding to the first opening, and the pad electrode is exposed to the outside through the second opening.

28. The method according to claim 27, wherein: The second opening is formed simultaneously with the first opening.

29. The method according to claim 27, wherein: Forming the circuit layer further includes: forming a metal layer on the inorganic layer; and The metal layer is etched to form the pad electrode.

30. The method of claim 29, wherein: Forming the circuit layer further includes: forming a shield electrode; and A transistor including a semiconductor pattern is formed on the shielding electrode, wherein the semiconductor pattern overlaps the shielding electrode.

31. The method of claim 22, wherein: Forming the circuit layer includes: forming a shielding electrode on the preliminary base layer, and Wherein, the pad electrode and the shielding electrode are formed simultaneously.

32. The method of claim 30, wherein: The transistor further includes a gate electrode overlapping the semiconductor pattern, and Wherein, the pad electrode and the gate electrode are formed simultaneously.

33. The method of claim 30, wherein: Forming the circuit layer further includes forming a connection pattern connected to the semiconductor pattern, wherein the pad electrode and the connection pattern are formed simultaneously.

34. The method of claim 22, further comprising: An adhesive resin is formed after forming the metal pattern, at least a portion of the adhesive resin is disposed in the first opening, wherein the adhesive resin covers the metal pattern.

Images