Semiconductor device

Abstract

The present invention addresses the problem of protecting a plurality of semiconductor chips mounted on a silicon interposer from an ESD current without increasing the chip area. To this end, a semiconductor device has a substrate and a plurality of semiconductor chips provided on the substrate. Each of the plurality of semiconductor chips has a plurality of chip power supply lines and a circuit connected to the plurality of chip power supply lines. A signal output from the circuit of the semiconductor chip is input to a circuit of another semiconductor chip. The substrate has a plurality of substrate power supply lines connected to the plurality of chip power supply lines of the plurality of semiconductor chips, respectively, and a plurality of substrate clamp circuits connected to the plurality of types of substrate power supply lines, respectively.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] There is a known technology for mounting a plurality of semiconductor chips (bare chips) on a silicon interposer. There is a known technology for providing an I / O (Input / Output) circuit on a bare chip to connect the bare chip to the outside or another bare chip. There is a known technology for suppressing the destruction of components caused by ESD (Electro-Static Discharge) current by configuring a protection circuit (clamp circuit) between a power line and a ground line.

[0003] <Prior Art Literature>

[0004] <Patent Documents>

[0005] Patent Document 1: U.S. Patent Application Publication No. 2021 / 0193647

[0006] Patent Document 2: U.S. Patent No. 9245852

[0007] Patent Document 3: U.S. Patent No. 8040645

[0008] Patent Document 4: U.S. Patent No. 11398469

[0009] Patent Document 5: Japanese Patent Application Publication No. 2013-065870

[0010] Patent Document 6: U.S. Patent Application Publication No. 2021 / 0313375

[0011] Patent Document 7: U.S. Patent No. 9412708 Summary of the invention

[0012] <Problems to be Solved by the Invention>

[0013] When multiple semiconductor chips supplied with different power supply voltages are mounted on a silicon interposer, the wiring provided by the silicon interposer and the multiple semiconductor chips may sometimes become a discharge path for the ESD current. For example, when the input and output circuits of multiple semiconductor chips are connected by signal lines, when the power supply voltage changes due to the ESD current flowing in the power supply line of the semiconductor chip, overvoltage may be applied to components such as transistors provided in the input and output circuits. When a protection circuit is configured for each semiconductor chip in order to protect components such as transistors of the semiconductor chip from the influence of the ESD current, the chip area may increase.

[0014] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to suppress an increase in chip area and protect a plurality of semiconductor chips mounted on a silicon interposer from the influence of ESD current.

[0015] <Methods used to solve the problem>

[0016] In one embodiment of the present invention, a semiconductor device comprises: a substrate; a first substrate power line, a second substrate power line and a third substrate power line, wherein the first substrate power line is arranged on the substrate, the second substrate power line is supplied with a voltage different from that of the first substrate power line, and the third substrate power line is supplied with a voltage different from that of the first substrate power line; a first substrate clamping circuit is arranged on the substrate and configured between the first substrate power line and the second substrate power line; a second substrate clamping circuit is arranged on the substrate and configured between the first substrate power line and the third substrate power line; a first semiconductor chip and a second semiconductor chip are arranged on the substrate; a first chip power line is arranged on the substrate; The first semiconductor chip is provided and electrically connected to the first substrate power line; a second chip power line is provided in the first semiconductor chip and electrically connected to the second substrate power line; a first circuit is provided in the first semiconductor chip and configured between the first chip power line and the second chip power line; a third chip power line is provided in the second semiconductor chip and electrically connected to the first substrate power line; a fourth chip power line is provided in the second semiconductor chip and electrically connected to the third substrate power line; and a second circuit is provided in the second semiconductor chip and configured between the third chip power line and the fourth chip power line, and a signal output from the first circuit is input to the second circuit.

[0017] <Effects of the Invention>

[0018] According to the disclosed technology, it is possible to suppress an increase in chip area and protect a plurality of semiconductor chips mounted on a silicon interposer from an ESD current. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a block diagram for explaining the problems of a semiconductor device in which a plurality of semiconductor chips are mounted on a silicon interposer.

[0020] Figure 2 This is a block diagram showing an example of the semiconductor device in the first embodiment.

[0021] Figure 3 It is shown Figure 2 A cross-sectional view schematically showing the connection between a silicon interposer and each chip.

[0022] Figure 4 It is shown Figure 2 A circuit diagram of an example of an internal circuit mounted on a semiconductor chip.

[0023] Figure 5 It is shown Figure 2 Circuit diagram of an example of a clamp circuit.

[0024] Figure 6 It is shown in Figure 2 A perspective top view of an example of the configuration of a silicon interposer and wiring and circuits formed in each chip.

[0025] Figure 7 It is shown Figure 2 A cross-sectional view schematically illustrating the structure of a silicon interposer.

[0026] Figure 8 This is a block diagram showing an example of a semiconductor device in the second embodiment.

[0027] Fig. 9 Show Figure 8 A perspective top view of an example of the configuration of a silicon interposer and wiring and circuits formed in each chip.

[0028] Fig.10 This is a block diagram showing an example of a semiconductor device in the third embodiment.

[0029] Fig.11 yes Fig.10 A perspective top view of an example of the configuration of a silicon interposer and wiring and circuits formed in each chip.

[0030] Fig.12 This is a block diagram showing an example of a semiconductor device in the fourth embodiment.

[0031] Fig.13 This is a block diagram showing an example of a semiconductor device in the fifth embodiment.

[0032] Fig.14 It is shown Fig.13 An explanatory diagram of an example of an ESD protection circuit.

[0033] Fig.15 It is an explanatory diagram showing another example of the ESD protection circuit.

[0034] Explanation of symbols

[0035] BID1, BID2, BID3: Bidirectional diodes

[0036] BM: Bump

[0037] C1: Capacitor

[0038] CIR1A, CIR1B: Internal circuit

[0039] CIR2A, CIR2B: Internal circuit

[0040] CIR3A, CIR3B: Internal circuit

[0041] CLMP1, CLMP2, CLMP3: Clamping circuits

[0042] CLMP21, CLMP22, CLMP23: Clamping circuit

[0043] CLMP24, CLMP25, CLMP26: Clamping circuit

[0044] CLMP27, CLMP28, CLMP29: Clamping circuit

[0045] CP1, CP2, CP3: semiconductor chips

[0046] D2: diode

[0047] DIF: Diffusion Area

[0048] ESD1, ESD2, ESD3, ESD4, ESD: Protection Circuits

[0049] ESDCLMP: Clamping Circuit

[0050] EXT: external terminal

[0051] GT: Gate electrode

[0052] IN2: Input signal line

[0053] INTP: Silicon Interposer

[0054] IV1, IV2, IV3: Inverter

[0055] LNPN: Parasitic Lateral NPN Bipolar Transistor

[0056] ND1: Node

[0057] NM1, NM2, NM3: NMOS transistors

[0058] OBUF: Output Buffer

[0059] OUT1, OUT2: output signal

[0060] PAD: external signal terminal

[0061] PM1, PM3: PMOS transistors

[0062] R1, R2, R3: resistors

[0063] SEM0, SEM1, SEM2, SEM4, SEM5: Semiconductor devices

[0064] SIG, SIG1, SIG2, SIG3: signal lines

[0065] SUB: Substrate

[0066] VDD1, VDD2, VDD3: power supply lines

[0067] VDD1c, VDD2c, VDD3c: Power supply lines

[0068] VDDIO: External power supply terminal

[0069] VIA1, VIA2, BIA3: through hole

[0070] VSS: External ground terminal, ground wire

[0071] VSS1, VSS2, VSS3: Ground wires

[0072] VSS1c, VSS2c, VSS3c: Ground wires

[0073] WL: wiring layer. DETAILED DESCRIPTION

[0074] Hereinafter, the embodiments will be described using the accompanying drawings. Hereinafter, symbols indicating signals are also used as symbols indicating signal lines or signal terminals. Symbols indicating power supply voltages are also used as symbols indicating power supply lines or power supply terminals that supply power supply voltages.

[0075] Figure 1 A block diagram illustrating a problem of a semiconductor device in which a plurality of semiconductor chips are mounted on a silicon interposer is shown. Figure 1 The semiconductor device SEM0 shown in the figure has a plurality of semiconductor chips CP1, CP2, and CP3 (chips) mounted on a silicon interposer INTP, and has a so-called 2.5-dimensional packaging method. Figure 1 In the embodiment, three semiconductor chips CP1, CP2, and CP3 are mounted on the silicon interposer INTP. However, for example, two or four or more semiconductor chips may be mounted on the silicon interposer INTP.

[0076] For example, each semiconductor chip CP1, CP2, CP3 has a function of processing signals or data, and can also work in cooperation with each other. By using a plurality of core particles to realize the functions carried by the semiconductor device SEM0, each core particle can be manufactured using an appropriate semiconductor manufacturing process. Therefore, compared with the case where a plurality of core particles are integrated into a single chip, the increase in the manufacturing cost of the semiconductor device SEM0 can be suppressed.

[0077] The semiconductor chip CP1 has internal circuits CIR1A and CIR1B, a clamp circuit CLMP1, a power line VDD1c, and a ground line VSS1c. The internal circuits CIR1A and CIR1B are arranged between the ground line VSS1c and the power line VDD1c, and operate by receiving the power voltage VDD1c and the ground voltage VSS1c. The clamp circuit CLMP1 is arranged between the ground line VSS1c and the power line VDD1c, and protects the internal circuits CIR1A and CIR1B as protected circuits from ESD.

[0078] The semiconductor chip CP2 has internal circuits CIR2A and CIR2B, a clamp circuit CLMP2, a power line VDD2c, and a ground line VSS2c. The internal circuits CIR2A and CIR2B are arranged between the ground line VSS2c and the power line VDD2c, and operate by receiving the power voltage VDD2c and the ground voltage VSS2c. The clamp circuit CLMP2 is arranged between the ground line VSS2c and the power line VDD2c, and protects the internal circuits CIR2A and CIR2B as protected circuits from ESD.

[0079] The semiconductor chip CP3 has internal circuits CIR3A and CIR3B, a clamp circuit CLMP3, a power line VDD3c, and a ground line VSS3c. The internal circuits CIR3A and CIR3B are arranged between the ground line VSS3c and the power line VDD3c, and operate by receiving the power voltage VDD3c and the ground voltage VSS3c. The clamp circuit CLMP3 is arranged between the ground line VSS3c and the power line VDD3c, and protects the internal circuits CIR3A and CIR3B as protected circuits from ESD.

[0080] The output signal line OUT1 connected to the internal circuit CIR1B of the semiconductor chip CP1 is electrically connected to the signal line SIG formed in the silicon interposer ITNP via the bump BMP such as a micro bump. The signal line SIG is electrically connected to the input signal line IN2 connected to the internal circuit CIR2A of the semiconductor chip CP2 via the bump BMP. That is, the output signal OUT1 output from the internal circuit CIR1B is input to the internal circuit CIR2A.

[0081] In the following, the semiconductor chips CP1-CP3 are also referred to as chips CP1-CP3. In addition, when the semiconductor chips CP1-CP3 are described without distinction, they are also referred to as chips CPx. When the internal circuits CIR1A and CIR1B are described without distinction, they are also referred to as internal circuits CIR1x. When the internal circuits CIR2A and CIR2B are described without distinction, they are also referred to as internal circuits CIR2x. When the internal circuits CIR3A and CIR3B are described without distinction, they are also referred to as internal circuits CIR3x. When the internal circuits CIR1A, CIR1B, CIR2A, CIR2B, CIR3A, and CIR3B are described without distinction, they are also referred to as internal circuits CIRx. When the clamping circuits CLMP1-CLMP3 are described without distinction, they are also referred to as clamping circuits CLMPx.

[0082] For example, the internal circuit CIRx is an input-output circuit. The clamp circuit CLMP1 suppresses the destruction of the internal circuit CIR1x caused by the ESD current flowing into the chip CP1 in the process of mounting the chip CP1 on the silicon interposer ITNP. The clamp circuit CLMP2 suppresses the destruction of the internal circuit CIR2x caused by the ESD current flowing into the chip CP2 in the process of mounting the chip CP2 on the silicon interposer ITNP. The clamp circuit CLMP3 suppresses the destruction of the internal circuit CIR3x caused by the ESD current flowing into the chip CP3 in the process of mounting the chip CP3 on the silicon interposer ITNP.

[0083] The silicon interposer ITNP has a power line VDD1 electrically connected to the power line VDD1c of the chip CP1 via a bump BMP, a power line VDD2 electrically connected to the power line VDD2c of the chip CP2 via a bump BMP, and a power line VDD3 electrically connected to the power line VDD3c of the chip CP3 via a bump BMP. In addition, the silicon interposer ITNP and each chip CPx may also be electrically connected via TSV (Through Silicon Via). The silicon interposer ITNP has a ground line VSS electrically connected to the ground line VSS1c of the chip CP1, the ground line VSS2c of the chip CP2, and the ground line VSS3c of the chip CP3 via a bump BMP.

[0084] The silicon interposer ITNP has an external ground terminal VSS and external power supply terminals VDD1, VDD2, and VDD3 exposed on the surface. The external ground terminal VSS is electrically connected to the ground line VSS of the silicon interposer ITNP. The external power supply terminal VDD1 is electrically connected to the power supply line VDD1 of the silicon interposer ITNP. The external power supply terminal VDD2 is electrically connected to the power supply line VDD2 of the silicon interposer ITNP. The external power supply terminal VDD3 is electrically connected to the power supply line VDD3 of the silicon interposer ITNP.

[0085] The clamp circuit CLMP1 protects the internal circuit CIR1x from ESD by forming a current path between the power line VDD1c and the ground line VSS1c when ESD occurs. The clamp circuit CLMP2 protects the internal circuit CIR2x from ESD by forming a current path between the power line VDD2c and the ground line VSS2c when ESD occurs. The clamp circuit CLMP3 protects the internal circuit CIR3x from ESD by forming a current path between the power line VDD3c and the ground line VSS3c when ESD occurs.

[0086] The ESD described below is generated when a finger of a human body touches an external terminal of the semiconductor device SEM0 during transportation after manufacture or when the semiconductor device SEM0 is installed in a system. That is, the model of the ESD described below is a human body model (HBM).

[0087] In the semiconductor device SEM0, when each chip CPx is a chip manufactured by advanced technology, most transistors have low withstand voltage, thin wiring and high wiring resistance compared to chips manufactured by conventional technology. It is difficult for wiring with high resistance to fully discharge the ESD current. Therefore, the chip CPx manufactured by advanced technology, for example, in automotive applications requiring high reliability, sometimes finds it difficult to meet the ESD protection specifications. In the case of large-scale clamping circuits CLMPx provided in each chip CPx in order to enhance the withstand voltage of transistors and the like against ESD, the chip size will increase.

[0088] For example, in the human body model, when a positive ESD voltage is applied from the external power supply terminal VDD1 with respect to the external power supply terminal VDD2 (ESD application), Figure 1 The ESD current flows in the paths indicated by the dashed arrows and the single-dot chain lines. Since the discharge path indicated by the single-dot chain line includes the clamp circuits CLMP1 and CLMP2, the potential difference between the input side and the output side of the current tends to be larger than that in the discharge path indicated by the dashed line.

[0089] For example, since the rise of the power supply voltage VDD2 (VDD2c) lags behind the rise of the power supply voltage VDD1 (VDD1c) when ESD is applied, the high-level voltage of the output signal OUT1 from the internal circuit CIR1B may exceed the power supply voltage VDD2c. Therefore, for example, when the potential difference between the gate and the source (VDD2c) of the PMOS transistor of the internal circuit CIR2A receiving the input signal IN2 exceeds the withstand voltage of the transistor, the transistor may be destroyed.

[0090] (First Embodiment)

[0091] Figure 2 An example of a semiconductor device in the first embodiment is shown. Figure 1 The same elements are denoted by the same reference numerals, and detailed description thereof will be omitted. Figure 2 The semiconductor device SEM1 shown is Figure 1 The semiconductor device SEM0 has a so-called 2.5-dimensional packaging method in which a plurality of semiconductor chips CP1, CP2, and CP3 (chips) are mounted on a silicon interposer INTP. The silicon interposer INTP is an example of a substrate. The chip CP1 is an example of a first semiconductor chip, and the chip CP2 is an example of a second semiconductor chip.

[0092] The circuit structure of chips CP1, CP2, and CP3 is set to Figure 1 The values ​​of the power supply voltages VDD1, VDD2, and VDD3 may be the same as each other, or may be different from each other to the extent that the voltage level of the signal transmitted between the chips CPx does not need to be converted. In addition, in the process of mounting each chip CPx on the silicon interposer ITNP, when a countermeasure is adopted to prevent the ESD current from flowing into each chip CPx, each clamping circuit CLMPx may not be formed in each chip CPx.

[0093] Silicon interposer INTP Figure 1 Clamp circuits CLMP21, CLMP22, and CLMP23 are added to the structure. Clamp circuit CLMP21 is configured between ground line VSS and power line VDD1. Clamp circuit CLMP22 is configured between ground line VSS and power line VDD2. Clamp circuit CLMP31 is configured between ground line VSS and power line VDD3. Hereinafter, when clamp circuits CLMP21, CLMP22, CLMP23, etc. provided in silicon interposer INTP are described without distinction, they are also referred to as clamp circuit CLMP2x.

[0094] The ground line VSS is an example of a first substrate power line. The power line VDD1 and the power line VDD2 of the silicon interposer ITNP are examples of a second substrate power line and a third substrate power line, respectively. The clamp circuit CLMP21 is an example of a first substrate clamp circuit. The clamp circuit CLMP22 is an example of a second substrate clamp circuit.

[0095] The ground line VSS1c of the chip CP1 is an example of a first chip power line, and the power line VDD1c of the chip CP1 is an example of a second chip power line. The ground line VSS2c of the chip CP2 is an example of a third chip power line, and the power line VDD2c of the chip CP2 is an example of a fourth chip power line.

[0096] The internal circuits CIR1A and CIR1B are examples of a first circuit to be protected from ESD. The internal circuits CIR2A and CIR2B are examples of a second circuit to be protected. The clamp circuit CLMP1 is an example of a first chip clamp circuit, and the clamp circuit CLMP2 is an example of a second chip clamp circuit. The scale of the clamp circuit CLMPx of each chip CPx is smaller than the scale of the clamp circuit CLMP2x of the interposer ITNP. Regarding the scale of the clamp circuit CLMPx, use Figure 5 To explain.

[0097] In the semiconductor device SEM1, for example, in the human body model, when a positive ESD voltage is applied from the external power supply terminal VDD1 with reference to the external power supply terminal VDD2 (ESD application), Figure 2 The ESD current flows in the path shown by the dashed arrow. Figure 2 As shown, by forming clamp circuits CLMP21-CLMP23 between the power supply lines VDD1-VDD3 and the ground line VSS in the silicon interposer ITNP, it is possible to suppress the ESD current from flowing through the chips CPx and suppress the destruction of the elements in the chips CPx.

[0098] Figure 3 Shown as a cross-sectional view Figure 2 The bumps BMP to which each chip CPx is connected are electrically connected to the external terminals EXT via wiring in the silicon interposer ITNP, or are connected to other chips via the bumps BMP and wiring in the silicon interposer ITNP.

[0099] Figure 4 Show Figure 2 An example of internal circuits CIR1B and CIR2A mounted on semiconductor chips CP1 and CP2. For example, the internal circuit CIR1B has an output buffer including two inverters IV1 connected in series, receives an input signal IN1 from the preceding inverter IV1A, and outputs an output signal OUT1 from the succeeding inverter IV1B.

[0100] For example, the internal circuit CIR2A has an input buffer including two inverters IV2 connected in series, receives an input signal IN2 from the inverter IV2A at the previous stage, and outputs an output signal OUT2 from the inverter IV2B at the subsequent stage. In addition, the chip CP1 may also be equipped with circuits other than the output buffer, and the chip CP2 may also be equipped with circuits other than the input buffer. In addition, a signal may be transmitted from the output buffer formed in the chip CP2 to the input buffer formed in the chip CP1.

[0101] Figure 5 Show Figure 2 The example of the clamp circuit CLMP21 is shown in FIG. 1. In addition, the clamp circuits CLMP22 and CLMP23 may also be used in the same manner as in FIG. Figure 5 The clamp circuit CLMP21 is formed using a PMOS transistor PM1 or an NMOS transistor NM1.

[0102] The clamp circuit CLMP21 using the PMOS transistor PM1 includes a capacitor C1, a resistor R1, an inverter IV3, and a PMOS transistor PM1. The capacitor C1 and the resistor R1 are connected in series between the power line VDD1 and the ground line VSS via the node ND1, and function as an RC time constant circuit. The input of the inverter IV3 is connected to the node ND1, and the output is connected to the gate of the PMOS transistor PM1. The source and substrate of the PMOS transistor PM1 are connected to the power line VDD1, and the drain is connected to the ground line VSS.

[0103] In the clamp circuit CLMP21 using a PMOS transistor, when the system of the semiconductor device SEM1 is in operation, the input of the inverter IV3 is pulled down to a low level via the resistor R1, and the inverter IV3 outputs a high level. The PMOS transistor PM1 receives a high level at the gate and is turned off (OFF). In an ESD event in which an ESD voltage is applied to the power line VDD1, the input of the inverter IV3 becomes a high level due to the coupling effect of the capacitor C1, and the output is a low level. The PMOS transistor PM1 receives a high level at the source and a low level at the gate and is turned on (ON), and an ESD current flows from the power line VDD1 to the ground line VSS.

[0104] The clamp circuit CLMP21 using an NMOS transistor includes a resistor R1, a capacitor C1, an inverter IV3, and an NMOS transistor NM1. The resistor R1 and the capacitor C1 are connected in series between the power line VDD1 and the ground line VSS via the node ND1, and function as an RC time constant circuit. The input of the inverter IV3 is connected to the node ND1, and the output is connected to the gate of the NMOS transistor NM1. The drain of the NMOS transistor NM1 is connected to the power line VDD1, and the source and the substrate are connected to the ground line VSS.

[0105] In the clamp circuit CLMP21 using an NMOS transistor, when the system of the semiconductor device SEM1 is in operation, the input of the inverter IV3 is pulled up to a high level via the resistor R1, and a low level is output. The NMOS transistor NM1 is turned off by receiving a low level at the gate. In an ESD event in which an ESD voltage is applied to the power line VDD1, the input of the inverter IV3 is regarded as a low level due to the RC time constant based on the resistor R1 and the capacitor C1, and the inverter IV3 outputs a high level. The NMOS transistor NM1 is turned on by receiving a low level at the source and a high level at the gate, and an ESD current flows from the power line VDD1 to the ground line VSS.

[0106] In addition, the clamp circuit CLMPx formed in each chip CPx is the same circuit as the clamp circuit CLMP2x of the silicon interposer ITNP, and has a transistor and an RC time constant circuit through which a current flows when an overvoltage caused by ESD is generated. The size of the transistor of the clamp circuit CLMPx of each chip CPx is smaller than the size of the transistor of each clamp circuit CLMP2x of the silicon interposer ITNP. For example, the size of the transistor can also be represented by the gate width. In addition, the RC time constant of the RC time constant circuit of the clamp circuit CLMPx of each chip CPx can also be smaller than the RC time constant of the RC time constant circuit of each clamp circuit CLMP2x of the silicon interposer ITNP.

[0107] Figure 6 Shown in Figure 2 An example of the configuration of the wiring and circuit formed in the silicon interposer ITNP and each chip CPx. The ground line VSS and the power lines VDD1, VDD2, and VDD3 of the silicon interposer ITNP are configured to extend in the Y direction with intervals in the X direction. The power lines VDD1, VDD2, and VDD3 and the ground line VSS are alternately configured. In addition, in the silicon interposer ITNP, the ground line VSS that connects the ground lines VSS extending in the Y direction is configured to extend in the X direction.

[0108] The clamp circuit CLMP21 of the silicon interposer ITNP is disposed in a region where the power line VDD1 and the ground line VSS of the silicon interposer ITNP are disposed, and is electrically connected to the power line VDD1 and the ground line VSS via the via VIA1. Figure 6 The position shown may be any position as long as it overlaps with the power supply line VDD1 and the ground line VSS of the silicon interposer ITNP in a plan view.

[0109] The clamp circuit CLMP22 is disposed in a region where the power line VDD2 and the ground line VSS of the silicon interposer ITNP are disposed, and is electrically connected to the power line VDD2 and the ground line VSS via the via VIA1. The location where the clamp circuit CLMP22 is disposed is not limited to Figure 6 The position shown may be any position as long as it overlaps with the power supply line VDD2 and the ground line VSS of the silicon interposer ITNP in a plan view.

[0110] The clamp circuit CLMP23 is disposed in a region where the power line VDD3 and the ground line VSS of the silicon interposer ITNP are disposed, and is electrically connected to the power line VDD3 and the ground line VSS via the via VIA1. The location where the clamp circuit CLMP23 is disposed is not limited to Figure 6 The position shown may be any position as long as it overlaps with the power supply line VDD3 and the ground line VSS of the silicon interposer ITNP in a plan view.

[0111] The chip CP1 is arranged in a region where the power line VDD1 and the ground line VSS of the silicon interposer ITNP are arranged. The power line VDD1c and the ground line VSS1c of the chip CP1 are arranged to extend in the X direction with a gap in the Y direction, and are electrically connected to the power line VDD1 and the ground line VSS of the silicon interposer ITNP respectively via the through hole VIA2. The clamp circuit CLMP1 of the chip CP1 is electrically connected to the power line VDD1c and the ground line VSS of the chip CP1 via the through hole VIA3. The position where the clamp circuit CLMP1 is arranged is not limited to Figure 6 The position shown may be any position as long as it overlaps with the power supply line VDD1c and the ground line VSS1c of the chip CP1 in a plan view.

[0112] The chip CP2 is arranged in an area where the power line VDD2 and the ground line VSS of the silicon interposer ITNP are arranged. The power line VDD2c and the ground line VSS of the chip CP2 are arranged to extend in the X direction with a gap in the Y direction, and are electrically connected to the power line VDD2 and the ground line VSS of the silicon interposer ITNP respectively via the through hole VIA2. The clamping circuit CLMP2 of the chip CP2 is electrically connected to the power line VDD2c and the ground line VSS of the chip CP2 via the through hole VIA3. The position of configuring the clamping circuit CLMP2 is not limited to Figure 6 The position shown may be any position as long as it overlaps with the power supply line VDD2c and the ground line VSS of the chip CP2 when viewed from above.

[0113] The chip CP3 is arranged in an area where the power line VDD3 and the ground line VSS of the silicon interposer ITNP are arranged. The power line VDD3c and the ground line VSS of the chip CP3 are arranged to extend in the X direction with a gap in the Y direction, and are electrically connected to the power line VDD3 and the ground line VSS of the silicon interposer ITNP respectively via the through hole VIA2. The clamping circuit CLMP3 of the chip CP3 is electrically connected to the power line VDD3c and the ground line VSS of the chip CP3 via the through hole VIA3. The position of configuring the clamping circuit CLMP3 is not limited to Figure 6 The position shown may be any position as long as it overlaps with the power supply line VDD3c and the ground line VSS of the chip CP3 when viewed from above.

[0114] The vias VIA1 are provided to connect the wiring of the silicon interposer ITNP with each clamp circuit CLMP2x. The vias VIA2 are provided to connect the wiring of the silicon interposer ITNP with each wiring of each chip CPx. The vias VIA3 are provided to connect the wiring of each chip CPx with each clamp circuit CLMPx.

[0115] The clamp circuit CLMPx of each chip CPx is smaller in scale than the clamp circuit CLMP2x of the interposer ITNP. In addition, in each clamp circuit CLMPx, CLMP2x, the number of through holes connected to the power line and the ground line, and the number of connected power lines and ground lines are not limited to Figure 6 .

[0116] Figure 7 Shown as a cross-sectional view Figure 2 The silicon interposer ITNP has a substrate SUB and a plurality of wiring layers WL formed on the substrate SUB. The substrate SUB has a diffusion region DIF formed by impurity implantation, and a transistor structure is formed by the diffusion region DIF and a gate electrode GT formed on the diffusion region DIF via a gate insulating film.

[0117] Figure 2 The capacitor C1 of each clamp circuit CLMP2x of the interposer ITNP ( Figure 5 ) can be formed by, for example, a capacitor element using a gate capacitor included in a transistor structure formed on the substrate SUB. The resistor R1 ( Figure 5) For example, it can also be formed by a resistor element using a diffusion region DIF included in a transistor structure formed on the substrate SUB. Alternatively, the capacitor C1 or the resistor R1 of each clamp circuit CLMP2x can also be formed by a capacitor (comb capacitor) or a wiring resistor formed by wiring provided in the wiring layer WL. Furthermore, a diode or a thyristor can also be formed using a transistor structure.

[0118] As described above, in the first embodiment, by forming clamp circuits CLMP21-CLMP23 between each power line VDD1-VDD3 and the ground line VSS in the silicon interposer ITNP, the ESD current can be suppressed from flowing through the chips CP1-CP3, thereby suppressing the destruction of the components in the chips CP1-CP3.

[0119] By forming clamp circuits CLMP1-CLMP3 in chips CP1-CP3 respectively, it is possible to suppress destruction of internal circuits CIR1x, CIR2x, and CIR3x caused by ESD current flowing into chips CP1-CP3 during the process of mounting chips CP1-CP3 on silicon interposer ITNP.

[0120] By mounting the clamp circuits CLMP1 to CLMP3 , which are smaller in scale than the clamp circuits CLMP21 to CLMP23 , on the chips CP1 to CP3 , respectively, it is possible to suppress an increase in the chip size of the chips CP1 to CP3 .

[0121] (Second Embodiment)

[0122] Figure 8 An example of a semiconductor device in the second embodiment is shown. Figure 2 The same elements are denoted by the same reference numerals, and detailed description thereof will be omitted. Figure 8 The semiconductor device SEM2 shown is Figure 2 The semiconductor device SEM1 similarly has a so-called 2.5-dimensional packaging method in which a plurality of semiconductor chips CP1, CP2, and CP3 (chips) are mounted on a silicon interposer INTP.

[0123] In the semiconductor device SEM2, the chip CP1 is electrically connected to the ground line VSS1 of the silicon interposer ITNP, and the chips CP2 and CP3 are electrically connected to the ground line VSS2 of the silicon interposer ITNP. Therefore, the semiconductor device SEM2 has external ground terminals VSS1 and VSS2. The silicon interposer ITNP has: a ground line VSS1 electrically connected to the external ground terminal VSS1; a ground line VSS2 electrically connected to the external ground terminal VSS2; and a bidirectional diode BID1 arranged between the ground lines VSS1 and VSS2. The bidirectional diode BID1 can also be used Figure 7 The transistor structure is formed on the substrate SUB shown.

[0124] The clamp circuit CLMP21 is disposed between the ground line VSS1 and the power line VDD1 of the silicon interposer ITNP. The clamp circuit CLMP22 is disposed between the ground line VSS2 and the power line VDD2 of the silicon interposer ITNP. The clamp circuit CLMP23 is disposed between the ground line VSS2 and the power line VDD3 of the silicon interposer ITNP.

[0125] The ground line VSS1c of the chip CP1 is electrically connected to the ground line VSS1 of the silicon interposer ITNP via the bump BMP. The ground line VSS2c of the chip CP2 and the ground line VSS3c of the chip CP3 are electrically connected to the ground line VSS2 of the silicon interposer ITNP via the bump BMP. Figure 2 The elements of the semiconductor device SEM1 are the same.

[0126] The ground lines VSS1 and VSS2 of the silicon interposer ITNP are examples of the fourth substrate power line and the fifth substrate power line, respectively. The power line VDD3 of the silicon interposer ITNP is an example of the sixth substrate power line. The clamp circuit CLMP23 is an example of the third substrate clamp circuit. The bidirectional diode BID1 is an example of the first bidirectional diode. The ground line VSS3c of the chip CP3 is an example of the fifth chip power line, and the power line VDD3c of the chip CP3 is an example of the sixth chip power line.

[0127] By forming a bidirectional diode BID1 in the silicon interposer ITNP, current can flow mutually when a potential difference occurs between the ground lines VSS1 and VSS2. Thus, for example, when ESD occurs, ESD current can flow between the ground lines VSS1 and VSS2 and be discharged.

[0128] For example, in the human body model, when a positive ESD voltage is applied from the external power supply terminal VDD1 with respect to the external power supply terminal VDD2 (ESD application), the ESD current is Figure 8 The ESD current flows through the path including the bidirectional diode BID1 as indicated by the dashed arrow. Thus, it is possible to suppress the ESD current from flowing through each chip CPx and suppress the destruction of the elements in each chip CPx.

[0129] In addition, when the bidirectional diode BID1 is not formed in the silicon interposer ITNP, in order to suppress the ESD current from flowing through each chip CP1-CP3, for example, a bidirectional diode is formed in any one of the chips CP1-CP3. For example, when a bidirectional diode is formed in the chip CP1, the ground line VSS2 of the silicon interposer ITNP is electrically connected to the ground line VSS1c of the chip CP1 via the bump BMP (or TSV).

[0130] As a result, the number of bumps BMP (or TSV) may exceed the limit. In addition, since the chip size of the chip CP1 forming the bidirectional diode BID1 increases, the chip cost increases. The chip cost also increases as the yield rate decreases due to the increase in chip size. In addition, when each chip CPx is manufactured using advanced technology, there is sometimes no suitable bidirectional diode that can be mounted on the chip CPx.

[0131] Fig. 9 Shown in Figure 8 An example of the configuration of the silicon interposer ITNP and the wiring and circuits formed in each chip CP1-CP3. Figure 6 The same elements are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0132] Fig. 9 In addition to forming a bidirectional diode BID1 in the silicon interposer ITNP, Figure 6 The configuration of the circuit is the same. The bidirectional diode BID1 is arranged in the area where the ground lines VSS1 and VSS2 are arranged, and is electrically connected to the ground lines VSS1 and VSS2 via the through hole VIA1. The ground line VSS2 of the silicon interposer INTP is connected to the ground line VSS2c of the chip CP2 and the ground line VSS3c of the chip CP3. In addition, the position of the bidirectional diode BID1 is not limited to Fig. 9 The position shown may be any position as long as it overlaps with the ground lines VSS1 and VSS2 of the silicon interposer ITNP in a plan view.

[0133] As described above, in the second embodiment, the same effect as in the first embodiment can be obtained. For example, in the silicon interposer ITNP, a clamp circuit CLMP21 is formed between the power line VDD1 and the ground line VSS1, and clamp circuits CLMP22 and CLMP23 are formed between the power lines VDD2 and VDD3 and the ground line VSS2, respectively. Thus, the ESD current can be suppressed from flowing through the chips CP1-CP3, and the destruction of the components in the chips CP1-CP3 can be suppressed.

[0134] Furthermore, in the second embodiment, when the chips CP1-CP3 are connected to different ground lines VSS1 and VSS2, a bidirectional diode BID1 is formed in the silicon interposer ITNP to electrically connect the ground lines VSS1 and VSS2 to each other. Thus, when ESD occurs, the ESD current can flow between the ground lines VSS1 and VSS2 of the silicon interposer ITNP, and the ESD current can be discharged. As a result, the ESD current can be suppressed from flowing through the chips CP1-CP3, and the destruction of the components in the chips CP1-CP3 can be suppressed.

[0135] (Third Embodiment)

[0136] Fig.10 An example of a semiconductor device in the third embodiment is shown. Figure 8 The same elements are denoted by the same reference numerals, and detailed description thereof will be omitted. Fig.10 The semiconductor device SEM3 shown is Figure 8 The semiconductor device SEM2 similarly has a so-called 2.5-dimensional packaging method in which a plurality of semiconductor chips CP1, CP2, and CP3 (chips) are mounted on a silicon interposer INTP.

[0137] In the semiconductor device SEM3, the chip CP1 is electrically connected to the ground line VSS1 of the silicon interposer ITNP, the chip CP2 is electrically connected to the ground line VSS2 of the silicon interposer ITNP, and the chip CP3 is electrically connected to the ground line VSS3 of the silicon interposer ITNP. Therefore, the semiconductor device SEM3 has external ground terminals VSS1, VSS2, and VSS3. The silicon interposer ITNP has: a ground line VSS1 electrically connected to the external ground terminal VSS1; a ground line VSS2 electrically connected to the external ground terminal VSS2; and a ground line VSS3 electrically connected to the external ground terminal VSS3.

[0138] In addition, the silicon interposer ITNP includes: a bidirectional diode BID1 disposed between ground lines VSS1 and VSS2; a bidirectional diode BID2 disposed between ground lines VSS2 and VSS3; and a bidirectional diode BID3 disposed between ground lines VSS3 and VSS1. Each bidirectional diode BID1-BID3 can also be used Figure 7 The clamp circuit CLMP23 is formed by a transistor structure on the substrate SUB shown in FIG.

[0139] The ground line VSS3c of the chip CP3 is electrically connected to the ground line VSS3 of the silicon interposer ITNP via the bump BMP. Figure 8 The elements of the semiconductor device SEM2 are the same.

[0140] and Figure 8 Similarly, for example, in the human body model, when a positive ESD voltage is applied from the external power supply terminal VDD1 with respect to the external power supply terminal VDD2 (ESD application), the ESD current is Fig.10 The ESD current flows through the path including the bidirectional diode BID1 indicated by the dashed arrow. Thus, the ESD current can be suppressed from flowing through each chip CP, and the destruction of the elements in each chip CP can be suppressed.

[0141] Fig.11 Shown in Fig.10An example of the configuration of the silicon interposer ITNP and the wiring and circuits formed in each chip CP1-CP3. Figure 6 as well as Fig. 9 The same elements are denoted by the same reference numerals, and detailed description thereof will be omitted. Fig.11 In addition to forming bidirectional diodes BID2 and BID3 in the silicon interposer ITNP, Fig. 9 The circuit configuration is the same.

[0142] The bidirectional diode BID2 is arranged in the region where the ground lines VSS2 and VSS3 are arranged, and is electrically connected to the ground lines VSS2 and VSS3 via the through hole VIA1. The bidirectional diode BID3 is arranged in the region where the ground lines VSS3 and VSS1 are arranged, and is electrically connected to the ground lines VSS3 and VSS1 via the through hole VIA1. In addition, the position where the bidirectional diode BID2 is arranged is not limited to Fig.11 The position shown in the figure can be any position as long as it overlaps with the ground lines VSS2 and VSS3 of the silicon interposer ITNP in a plan view. The position where the bidirectional diode BID3 is arranged is not limited to Fig.11 The position shown may be any position as long as it overlaps with the ground lines VSS3 and VSS1 of the silicon interposer ITNP in a plan view.

[0143] As described above, in the third embodiment, the same effects as those of the first and second embodiments can be obtained. For example, in the silicon interposer ITNP, clamp circuits CLMP21-CLMP23 are formed between the power supply lines VDD1-VDD3 and the ground lines VSS1-VSS3, respectively. Thus, the ESD current can be suppressed from flowing through the chips CP1-CP3, and the destruction of the components in the chips CP1-CP3 can be suppressed.

[0144] When the chips CP1-CP3 are electrically connected to the grounding wires VSS1-VSS3 of the silicon interposer ITNP, bidirectional diodes BID1-BID3 are formed in the silicon interposer ITNP to electrically connect the grounding wires VSS1-VSS3 to each other. Thus, when ESD occurs, the ESD current can flow between the grounding wires VSS1-VSS3 of the silicon interposer ITNP, and the ESD current can be discharged. As a result, the ESD current can be suppressed from flowing through the chips CP1-CP3, and the destruction of the components in the chips CP1-CP3 can be suppressed.

[0145] (Fourth Embodiment)

[0146] Fig.12 An example of a semiconductor device in the fourth embodiment is shown. Fig.10 The same elements are denoted by the same reference numerals, and detailed description thereof will be omitted. Fig.12 The semiconductor device SEM4 shown is Fig.10 The semiconductor device SEM3 similarly has a so-called 2.5-dimensional packaging method in which a plurality of semiconductor chips CP1, CP2, and CP3 (chips) are mounted on a silicon interposer INTP.

[0147] The interposer ITNP of the semiconductor device SEM4 has clamp circuits CLMP24 and CLMP25 respectively arranged between the ground line VSS1 and the power lines VDD2 and VDD3. The interposer ITNP has clamp circuits CLMP26 and CLMP27 respectively arranged between the ground line VSS2 and the power lines VDD1 and VDD3. The interposer ITNP has clamp circuits CLMP28 and CLMP29 respectively arranged between the ground line VSS3 and the power lines VDD1 and VDD2. That is, the interposer ITNP has a cross-domain clamp circuit CLMP2x. Other elements of the semiconductor device SEM4 are similar to Fig.10 The elements of the semiconductor device SEM3 are the same.

[0148] The ground line VSS1 of the silicon interposer INTP is an example of a fourth substrate power line, the ground line VSS2 of the silicon interposer INTP is an example of a seventh substrate power line, and the ground line VSS3 of the silicon interposer INTP is an example of an eighth substrate power line. The clamp circuit CLMP24 is an example of a fourth substrate clamp circuit, and the clamp circuit CLMP25 is an example of a fifth substrate clamp circuit. The clamp circuit CLMP26 is an example of a sixth substrate clamp circuit, and the clamp circuit CLMP27 is an example of a seventh substrate clamp circuit. The clamp circuit CLMP28 is an example of an eighth substrate clamp circuit, and the clamp circuit CLMP29 is an example of a ninth substrate clamp circuit.

[0149] As described above, the fourth embodiment can also achieve the same effects as those of the first to third embodiments. For example, when ESD occurs, it is possible to suppress the ESD current from flowing through the chips CP1 to CP3, thereby suppressing the destruction of the elements in the chips CP1 to CP3.

[0150] (Fifth Embodiment)

[0151] Fig.13 An example of a semiconductor device in the fifth embodiment is shown. Figure 2 The same elements are denoted by the same reference numerals, and detailed description thereof will be omitted. Fig.13 The semiconductor device SEM5 shown is Figure 2 The semiconductor device SEM1 similarly has a so-called 2.5-dimensional packaging method in which a plurality of semiconductor chips CP1, CP2, and CP3 (chips) are mounted on a silicon interposer INTP.

[0152] The interposer ITNP includes: a signal line SIG1 electrically connected to an external signal terminal SIG1 and an input terminal of an internal circuit CIR1A of a chip CP1; and a protection circuit ESD1 for electrostatic discharge arranged between the signal line SIG1 and a ground line VSS. The interposer ITNP includes: a signal line SIG2 electrically connected to an external signal terminal SIG2 and an input terminal of an internal circuit CIR2A of a chip CP2; and a protection circuit ESD2 for electrostatic discharge arranged between the signal line SIG2 and a ground line VSS. The interposer ITNP includes: a signal line SIG3 electrically connected to an external signal terminal SIG3 and an input terminal of an internal circuit CIR3A of a chip CP3; and a protection circuit ESD3 for electrostatic discharge arranged between the signal line SIG3 and a ground line VSS.

[0153] The external signal terminal SIG1 is an example of a first signal terminal, and the external signal terminal SIG2 is an example of a second signal terminal. The signal line SIG1 is an example of a first signal line, and the signal line SIG2 is an example of a second signal line. The internal circuit CIR1A is an example of a first circuit, and the input terminal of the internal circuit CIR1A is an example of a first input terminal. The internal circuit CIR2A is an example of a second circuit, and the input terminal of the internal circuit CIR2A is an example of a second input terminal. The protection circuit ESD1 is an example of a first protection circuit, and the protection circuit ESD2 is an example of a second protection circuit.

[0154] The internal circuit CIR1A of the chip CP1 receives the signal SIG1 supplied to the external signal terminal SIG1 via the signal line SIG1 of the silicon interposer ITNP, and outputs the signal to the internal circuit CIR1B. The internal circuit CIR2A of the chip CP2 receives the signal SIG2 supplied to the external signal terminal SIG2 via the signal line SIG2 of the silicon interposer ITNP, receives the input signal IN2 from the chip CP1, and outputs the signal to the internal circuit CIR2B. The internal circuit CIR3A of the chip CP3 receives the signal SIG3 supplied to the external signal terminal SIG3 via the signal line SIG3 of the silicon interposer ITNP, and outputs the signal to the internal circuit CIR3B.

[0155] The protection circuit ESD1 is configured between the signal line SIG1 and the ground line VSS. When an ESD event occurs when an ESD voltage is applied to the external signal terminal SIG1, the ESD current flows to the ground line VSS, thereby protecting the internal circuit CIR1A from being damaged. The protection circuit ESD2 is configured between the signal line SIG2 and the ground line VSS. When an ESD event occurs when an ESD voltage is applied to the external signal terminal SIG2, the ESD current flows to the ground line VSS, thereby protecting the internal circuit CIR2A from being damaged. The protection circuit ESD3 is configured between the signal line SIG3 and the ground line VSS. When an ESD event occurs when an ESD voltage is applied to the external signal terminal SIG3, the ESD current flows to the ground line VSS, thereby protecting the internal circuit CIR3A from being damaged.

[0156] Fig.14 Show Fig.13 An example of an ESD protection circuit ESD1. Fig.13 The ESD protection circuits ESD2 and ESD3 are also Fig.14 same. Fig.14 The upper side shows the circuit structure of the ESD protection circuit ESD1. Fig.14 An example of a cross-sectional structure of an NMOS transistor NM2 included in the ESD protection circuit ESD1 is shown at the lower side of FIG.

[0157] The ESD protection circuit ESD1 includes a resistor R2 and an NMOS transistor NM2 arranged in series between the signal line SIG1 and the ground line VSS. The gate, source, and substrate of the NMOS transistor NM2 are connected to the ground line VSS, and the drain of the NMOS transistor NM2 is electrically connected to the signal line SIG1 via the resistor R2.

[0158] Thus, the NMOS transistor NM2 functions as a diode D2 whose anode is connected to the ground line VSS and whose cathode is connected to the signal line SIG1. Therefore, a negative ESD current can flow from the ground line VSS to the signal line SIG1 via the diode D2. In addition, the NMOS transistor NM2 functions as a parasitic lateral NPN bipolar transistor LNPN based on the source, substrate, and drain. The base of the parasitic lateral NPN bipolar transistor LNPN is electrically connected to the ground line VSS via the resistor R3. Therefore, a positive ESD current can flow from the signal line SIG1 to the ground line VSS via the parasitic lateral NPN bipolar transistor LNPN.

[0159] In addition, a fin transistor (FinFET) may be configured instead of the NMOS transistor NM2 as a planar transistor. In addition, a thyristor element may be used instead of the NMOS transistor NM2. In addition, the configuration of the resistor R2 may be omitted in each of the ESD protection circuits ESD1, ESD2, and ESD3. In addition, the gate GT of the NMOS transistor NM2 may be connected to a control circuit that controls the operation of the ESD protection circuit instead of the ground line VSS.

[0160] Fig.15 Another example of the ESD protection circuit is shown. Fig.15 The ESD protection circuit ESD4 shown is installed in the signal unit as a fail-safe I / O buffer. The ESD protection circuit ESD4 is implemented by an ESD protection diode formed in the signal unit and a parasitic bipolar transistor (parasitic diode) formed in the NMOS transistor NM3 of the output buffer OBUF. The output buffer OBUF has a PMOS transistor PM3 and an NMOS transistor NM3 connected in series between the power supply line VDDIO for I / O and the ground line VSS via a node of the external signal terminal PAD.

[0161] The power supply unit has an ESD clamp circuit ESDCLMP disposed between the external power supply terminal VDDIO and the external ground terminal VSS. For example, when a positive ESD voltage is applied to the external signal terminal PAD with reference to the power supply terminal VDDIO, as indicated by a thick solid arrow, an ESD current flows from the external signal terminal PAD to the external power supply line VDDIO via the parasitic bipolar transistor, the ground line VSS, and the clamp circuit ESDCLMP. In this way, the operation of the parasitic bipolar transistor is required in the ESD countermeasure when a positive ESD voltage is applied to the fail-safe I / O buffer.

[0162] When a negative ESD voltage is applied to the external signal terminal PAD based on the power terminal VDDIO, as indicated by the thick dashed arrow, an ESD current flows from the external power terminal VDDIO to the external signal terminal PAD via the clamp circuit ESDCLMP, the ground line VSS, and the ESD protection diode.

[0163] In addition, the discharge path when a positive or negative ESD voltage is applied to the signal pad PAD with reference to the ground terminal VSS is also the same as Fig.15 For example, in the ESD protection between the external signal terminal PAD and the external ground terminal VSS, a thyristor element may be added to the signal unit separately from the output buffer OBUF.

[0164] As described above, the fifth embodiment can also achieve the same effects as those of the first embodiment. For example, the clamp circuits CLMP21-CLMP23 of the silicon interposer ITNP can suppress the ESD current from flowing through the chips CP1-CP3, thereby suppressing the destruction of the elements in the chips CP1-CP3.

[0165] Furthermore, in the fifth embodiment, by configuring the ESD protection circuits ESD1-ESD3 in the silicon interposer ITNP, even when an ESD voltage is applied to an external signal terminal for inputting or outputting signals to or from the chips CP1-CP3, it is possible to suppress the ESD current from flowing through the chips CP1-CP3. As a result, it is possible to suppress the destruction of the elements in the chips CP1-CP3.

[0166] As mentioned above, the present invention has been described based on each embodiment, but the present invention is not limited to the requirements shown in the above embodiment. These points can be changed within the scope that does not impair the gist of the present invention and can be appropriately determined according to the application mode.

Claims

1. A semiconductor device comprising: substrate; a first substrate power line, a second substrate power line and a third substrate power line, wherein the first substrate power line is provided on the substrate, the second substrate power line is supplied with a voltage different from that of the first substrate power line, and the third substrate power line is supplied with a voltage different from that of the first substrate power line; a first substrate clamping circuit, which is disposed on the substrate and arranged between the first substrate power line and the second substrate power line; a second substrate clamping circuit, which is disposed on the substrate and arranged between the first substrate power line and the third substrate power line; A first semiconductor chip and a second semiconductor chip are disposed on the substrate; A first chip power line, which is disposed on the first semiconductor chip and is electrically connected to the first substrate power line; A second chip power line, which is disposed on the first semiconductor chip and is electrically connected to the second substrate power line; a first circuit, which is disposed in the first semiconductor chip and arranged between the first chip power line and the second chip power line; a third chip power line, which is disposed on the second semiconductor chip and is electrically connected to the first substrate power line; a fourth chip power line, which is disposed on the second semiconductor chip and is electrically connected to the third substrate power line; as well as a second circuit, which is disposed in the second semiconductor chip and arranged between the third chip power line and the fourth chip power line, A signal output from the first circuit is input to the second circuit.

2. The semiconductor device according to claim 1, comprising: a first chip clamp circuit, which is disposed on the first semiconductor chip and arranged between the first chip power line and the second chip power line; and The second chip clamp circuit is disposed on the second semiconductor chip and arranged between the third chip power line and the fourth chip power line.

3. The semiconductor device according to claim 2, wherein: The first substrate clamp circuit, the second substrate clamp circuit, the first chip clamp circuit, and the second chip clamp circuit have elements that flow current when an overvoltage occurs. The sizes of the elements of the first chip clamp circuit and the second chip clamp circuit are smaller than the sizes of the elements of the first substrate clamp circuit and the second substrate clamp circuit.

4. The semiconductor device according to claim 3, wherein: The first substrate clamp circuit, the second substrate clamp circuit, the first chip clamp circuit, and the second chip clamp circuit further include an RC time constant circuit including a resistor and a capacitor. The RC time constants of the first chip clamp circuit and the second chip clamp circuit are smaller than the RC time constants of the first substrate clamp circuit and the second substrate clamp circuit.

5. The semiconductor device according to claim 1, wherein The semiconductor device has a first bidirectional diode disposed on the substrate. The first substrate power line includes a fourth substrate power line and a fifth substrate power line electrically connected via the first bidirectional diode, The first chip power line is electrically connected to the fourth substrate power line, The third chip power line is electrically connected to the fifth substrate power line.

6. The semiconductor device according to claim 5, wherein: The first substrate clamp circuit is arranged between the fourth substrate power line and the second substrate power line. The second substrate clamp circuit is disposed between the fifth substrate power line and the third substrate power line.

7. The semiconductor device according to claim 5, comprising: a sixth substrate power line, which is provided on the substrate and is supplied with a voltage different from that of the first substrate power line; a third semiconductor chip disposed on the substrate; a fifth chip power line, which is disposed on the third semiconductor chip and is electrically connected to the fifth substrate power line; a sixth chip power line, which is disposed on the third semiconductor chip and is electrically connected to the sixth substrate power line; a third circuit, which is disposed in the third semiconductor chip and arranged between the fifth chip power line and the sixth chip power line; and The third substrate clamping circuit is disposed on the substrate and arranged between the fifth substrate power line and the sixth substrate power line.

8. The semiconductor device according to claim 7, wherein: The semiconductor device includes a second bidirectional diode and a third bidirectional diode disposed on the substrate. The fifth substrate power line includes a seventh substrate power line and an eighth substrate power line electrically connected via the second bidirectional diode, The fourth substrate power line is electrically connected to the eighth substrate power line via the third bidirectional diode, The third chip power line is electrically connected to the seventh substrate power line, The fifth chip power line is electrically connected to the eighth substrate power line.

9. The semiconductor device according to claim 8, wherein: The semiconductor device has one or more of a fourth substrate clamp circuit, a fifth substrate clamp circuit, a sixth substrate clamp circuit, a seventh substrate clamp circuit, an eighth substrate clamp circuit, and a ninth substrate clamp circuit, The fourth substrate clamp circuit is disposed on the substrate and arranged between the fourth substrate power line and the third substrate power line. The fifth substrate clamp circuit is disposed on the substrate and arranged between the fourth substrate power line and the sixth substrate power line. The sixth substrate clamp circuit is disposed on the substrate and arranged between the seventh substrate power line and the second substrate power line. The seventh substrate clamp circuit is disposed on the substrate and arranged between the seventh substrate power line and the sixth substrate power line. The eighth substrate clamp circuit is disposed on the substrate and arranged between the eighth substrate power line and the second substrate power line. The ninth substrate clamping circuit is disposed on the substrate and arranged between the eighth substrate power line and the third substrate power line.

10. The semiconductor device according to claim 1, comprising: A first signal terminal and a second signal terminal, which are arranged on the substrate; a first signal line, disposed on the substrate, electrically connecting the first signal terminal to a first input terminal of the first circuit; a second signal line, disposed on the substrate, electrically connecting the second signal terminal to a second input terminal of the second circuit; a first protection circuit for electrostatic discharge, which is arranged between the first signal line and the first substrate power line; as well as The second protection circuit for electrostatic discharge is arranged between the second signal line and the first substrate power line.

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