Electrostatic surge integrated protection circuit of high-reliability high-voltage driving chip

Abstract

The invention belongs to the field of electrostatic discharge (ESD) and electrical overstress (EOS) pulse protection of an integrated circuit, and particularly provides an electrostatic surge integrated protection circuit of a high-reliability high-voltage driving chip, which is used for solving the problems of easy latching, high trigger voltage, poor robustness, low starting speed and the like in a traditional high-voltage ESD / EOS protection scheme. The SCR structure, the Zener structure and the LDMOS structure are technically embedded, the voltage clamping capacity of the Zener diode, the high voltage endurance capacity of the LDMOS, the quick response characteristic of the composite transistor and the strong discharge capacity of the SCR are integrated, the electrostatic and surge integrated protection efficiency is achieved, and under the ESD / EOS electric stress effect, the electrostatic and surge integrated protection effect is achieved. The composite structure promotes orderly opening of the Zener structure, the SCR structure and the LDMOS structure under the action of positive feedback, so that ESD and EOS protection requirements of different pulse frequencies are met, the hysteresis effect and the trigger voltage are remarkably reduced, and the latch-up phenomenon is effectively avoided.

Description

Technical Field

[0001] The present invention belongs to the field of electrostatic discharge (ESD) and electrical over-stress (EOS) pulse protection of integrated circuits (ICs), and specifically provides an ESD / EOS integrated protection circuit with high voltage resistance and small hysteresis characteristics, which can be applied to the electrostatic and surge protection of high-voltage drive chips in complex electromagnetic environments, so as to improve the reliability, stability and service life of the chips and their application systems. Background Art

[0002] Electrostatic discharge (ESD) or surge, also known as electrical overstress (EOS), is one of the important reasons for the failure of electronic equipment. High-voltage driver chips are widely used in industrial control, power electronics, automotive electronics and other fields. They need to withstand high voltage and high power operating conditions in complex electromagnetic environments, which puts higher requirements on the transient overvoltage tolerance and long-term reliability of high-voltage driver chips. However, the current ESD / EOS protection technology for high-voltage driver chips still faces many challenges.

[0003] Due to advantages such as simple structure and good process compatibility, traditional bijunction transistors, gate-grounded NMOS and gate-connected power PMOS are widely used in high-voltage ESD / EOS protection. However, due to their poor current conduction uniformity and weak current discharge capacity per unit area, they are difficult to meet the high reliability requirements of high-voltage driver chips. The SCR structure has advantages in the high-voltage field due to its excellent current discharge capacity and high robustness, but its trigger voltage is high and the hysteresis voltage amplitude is large after turning on. It may not respond in time under transient stress, or cause latch-up effect, causing the protected circuit to be burned or signal disorder under ESD / EOS stress. As a voltage stabilizing structure, the Zener diode has good voltage clamping characteristics, which can effectively suppress large hysteresis phenomenon and avoid circuit damage or latch-up; however, when the Zener structure is used alone, the voltage resistance and overcurrent capacity of the Zener diode are limited, which is difficult to meet the electrostatic and surge protection requirements in high-voltage environments. Laterally diffused metal-oxide-semiconductor (LDMOS) devices are widely used in high-voltage drive circuits due to their excellent thermal stability and high withstand voltage characteristics. LDMOS devices can not only maintain stable performance under high temperature and high power conditions, but also improve the switching rate of the device, reduce the on-resistance, and enhance the anti-interference ability of the circuit. On this basis, the present invention provides an electrostatic surge integrated protection circuit for a high-reliability high-voltage driver chip to meet the high-reliability ESD / EOS integrated protection requirements of high-voltage driver chips in complex electromagnetic environments. Summary of the invention

[0004] The purpose of the present invention is to provide an electrostatic surge integrated protection circuit for a high-reliability high-voltage driver chip to solve the problems of easy latching, high trigger voltage, poor robustness and slow opening speed in traditional high-voltage ESD / EOS protection solutions. The present invention forms a multi-composite tube ESD / EOS integrated protection leakage path by technically embedding SCR structure, Zener structure and LDMOS structure, realizes fast opening and anti-latch characteristics, and improves the leakage capacity of the circuit; specifically, the present invention integrates the voltage clamping capability of the Zener diode, the high withstand voltage capability of the LDMOS, the fast response characteristics of the composite transistor and the strong leakage capacity of the SCR, realizes the integrated protection efficiency of electrostatic and surge, and under the action of ESD / EOS electrical stress, the composite structure in the present invention promotes the orderly opening of the Zener structure, SCR structure and LDMOS structure under the action of positive feedback, thereby meeting the ESD and EOS protection requirements of different pulse frequencies, not only significantly reducing the hysteresis effect and trigger voltage, but also effectively avoiding the latch phenomenon. In addition, the composite structure can be flexibly adjusted according to different protection level requirements, providing an efficient and reliable solution, and significantly improving the system reliability and working stability of the high-voltage driver chip.

[0005] To achieve the above object, the technical solution adopted by the present invention is:

[0006] An integrated electrostatic surge protection circuit for a high-reliability high-voltage driver chip, characterized in that the integrated electrostatic surge protection circuit for the high-reliability high-voltage driver chip is arranged on the same P-type silicon substrate (100);

[0007] The P-type silicon substrate (100) is provided with a first P-type epitaxial layer (101), an N-type buried layer (102), and a second P-type epitaxial layer (103) in sequence from left to right;

[0008] A first deep P well (104) is provided on the first P-type epitaxial layer (101), a deep N well (105) is provided on the N-type buried layer (102), and a second deep P well (106) is provided on the second P-type epitaxial layer (103);

[0009] A first P well (111) is provided in the first deep P well (104) region, and a first P+ injection region (113) is provided in the first P well (111) region; a first N well (107), a second P well (108), and a second N well (109) are provided in the deep N well (105) region from left to right, and a PB doping layer (110) is provided in the second P well (108) region; a first N+ injection region (115) is provided in the first N well (107) region; and a first N+ injection region (115) is provided in the second P well (108) region from left to right. There are a second P+ injection region (116), a second N+ injection region (117), a third N+ injection region (118), and a third P+ injection region (119), and the third N+ injection region (118) is located in the PB doping layer (110); a fourth P+ injection region (120) and a fourth N+ injection region (121) are sequentially arranged from left to right in the second N well (109) region; a third P well (112) is arranged in the second deep P well (106) region, and a fifth P+ injection region (114) is arranged in the third P well (112) region;

[0010] A polysilicon gate oxide layer (122) is provided between the third P+ injection region (119) and the fourth P+ injection region (120), and the polysilicon gate oxide layer (122) is arranged across the surfaces of the second P well (108) and the second N well (109);

[0011] The first P+ injection region (113), the fifth P+ injection region (114), the second P+ injection region (116), the second N+ injection region (117), and the third P+ injection region (119) are all connected to the cathode of the electrostatic surge integrated protection circuit, and the first N+ injection region (115), the third N+ injection region (118), the fourth P+ injection region (120), the fourth N+ injection region (121), and the polysilicon gate oxide layer (122) are all connected to the electrostatic surge integrated protection circuit.

[0012] Furthermore, in the electrostatic surge integrated protection circuit, the parasitic resistance of the second N well (109) forms a first resistor R1, the parasitic resistance of the P well (108) forms a second resistor R2, and the second N well (109), the P well (108) and the second N+ injection region (117) constitute an NPN transistor T n1 The fourth P+ injection region (120), the second N-well (109) and the P-well (108) constitute a PNP transistor; the fourth P+ injection region (120), the polysilicon gate oxide layer (122), the second N-well (109), the P-well (108) and the third P+ injection region (119) constitute an LDMOS power transistor M1; the second N+ injection region (117), the PB doped layer (110) and the P-well (108) constitute a Zener transistor Z D .

[0013] Furthermore, the Zener diode Z D The cathode of the Zener tube Z is connected to the anode of the electrostatic surge integrated protection circuit. D The anode of the NPN transistor T n1 One end of the second resistor R2 is connected to the anode of the electrostatic surge integrated protection circuit, and the other end is connected to the PNP transistor T p1 The base of the PNP transistor T is connected to the substrate electrode of the LDMOS power tube M1; p1 The emitter of the PNP transistor T is connected to the anode of the electrostatic surge integrated protection circuit. p1 The base of the NPN transistor T n1 The collector of the PNP transistor T p1 The collector of the NPN transistor T n1 One end of the first resistor R1 is connected to the base of the NPN transistor T n1 The other end is connected to the cathode of the electrostatic surge integrated protection circuit; the NPN transistor T n1 The emitter of the LDMOS power tube M1 is connected to the cathode of the electrostatic surge integrated protection circuit; the source and gate of the LDMOS power tube M1 are respectively connected to the anode of the electrostatic surge integrated protection circuit, and the drain of the LDMOS power tube M1 is connected to the cathode of the electrostatic surge integrated protection circuit.

[0014] Furthermore, the electrostatic surge integrated protection circuit includes: a fast opening path, an SCR main discharge path and a voltage stabilizing clamping path; the fast opening path includes: a Zener tube Z D , the second resistor R2, the first resistor R1, the PNP transistor T p1 With NPN transistor T n1 ; The SCR main discharge path includes: PNP transistor T p1 、NPN transistor T n2 and the first resistor R1; the voltage stabilizing clamping path includes: a Zener tube Z D And LDMOS power tube M1.

[0015] Based on the above technical solution, the beneficial technical effects of the present invention are:

[0016] The present invention provides an integrated electrostatic surge protection circuit for a high-reliability high-voltage driver chip, which forms a multi-composite tube ESD / EOS integrated protection leakage path by technically embedding an SCR structure, a Zener structure and an LDMOS structure, realizes fast opening and anti-latch characteristics, and improves the leakage capacity of the circuit; the specific advantages are as follows:

[0017] 1) When the ESD or EOS electrical stress is small, the leakage current formed by the drift of minority carriers in the ESD / EOS integrated protection circuit flows through the Zener diode Z D , the second resistor R2, and the NPN transistor T n1 and the PNP transistor T p1 A common collector junction is formed on the first resistor R1 to form a first trigger current, and a parasitic NPN transistor composed of the third N+ injection region (118), the PB doped layer (110), the P well (108) and the second N+ injection region (117) can form a second trigger current. The first trigger current and the second trigger current can improve the response speed of the ESD / EOS integrated protection circuit and reduce the trigger voltage;

[0018] 2) When the ESD or EOS electrical stress is large, the voltage on the first resistor R1 in the ESD / EOS integrated protection circuit continues to increase, and the voltage on the NPN transistor T p1 and the second transistor T p1 Under the action of positive feedback, the voltage on the second resistor R2 is promoted to increase continuously, and an ESD or EOS current discharge channel of the SCR structure can be formed, thereby enhancing the robustness of the ESD / EOS integrated protection circuit;

[0019] 3) When the ESD or EOS electrical stress continues to increase, the LDMOS power tube M1 in the ESD / EOS integrated protection circuit is turned on and discharges current to achieve high-voltage triggering performance.

[0020] 4) When the ESD or EOS electrical stress increases and triggers the ESD / EOS integrated protection circuit to open, the Zener diode Z D The large retrace phenomenon of the on-state voltage caused by the large current discharge in the SCR structure can be suppressed, and the anti-latch capability of the ESD / EOS integrated protection circuit can be enhanced.

[0021] 5) When the ESD / EOS integrated protection circuit is applied to high-voltage driver chips in different power domains, the Zener diode Z can be adjusted according to the power domain voltage and circuit operating characteristics. D The number of cascade connections is increased to further enhance the voltage withstand and latch-up immunity capabilities of the ESD / EOS integrated protection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the structure of the integrated electrostatic surge protection circuit of the high-reliability high-voltage driver chip in an embodiment of the present invention.

[0023] Figure 2The figure is a quick start path diagram of the integrated electrostatic surge protection circuit of the high-reliability high-voltage driver chip in the embodiment of the present invention.

[0024] Figure 3 1 is a diagram of the main SCR discharge path of the electrostatic surge integrated protection circuit of the high-reliability high-voltage driver chip in an embodiment of the present invention.

[0025] Figure 4 The figure is a voltage stabilizing clamping path diagram of the electrostatic surge integrated protection circuit of the high-reliability high-voltage driver chip in the embodiment of the present invention.

[0026] Figure 5 Schematic diagram of the Zener tube cascade connection method of the electrostatic surge integrated protection circuit of the high-reliability high-voltage driver chip in the embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0028] This embodiment provides a high-reliability, high-voltage driver chip integrated electrostatic surge protection circuit (ESD / EOS integrated protection circuit), which is manufactured on the same P-type silicon substrate (100). The specific structure is as follows: Figure 1 As shown; the ESD / EOS integrated protection circuit is provided on the P-type silicon substrate (100) in sequence from left to right with a first P-type epitaxial layer (101), an N-type buried layer (102), and a second P-type epitaxial layer (103); a first deep P well (104) is provided on the first P-type epitaxial layer (101), a deep N well (105) is provided on the N-type buried layer (102), and a second deep P well (106) is provided on the second P-type epitaxial layer (103);

[0029] A first P well (111) is provided in the first deep P well (104) region, and a first P+ injection region (113) is provided in the first P well (111) region; a first N well (107), a second P well (108), and a second N well (109) are provided in the deep N well (105) region from left to right, and a PB doping layer (110) is provided in the second P well (108) region; a first N+ injection region (115) is provided in the first N well (107) region; and a first N+ injection region (115) is provided in the second P well (108) region from left to right. There are a second P+ injection region (116), a second N+ injection region (117), a third N+ injection region (118), and a third P+ injection region (119), and the third N+ injection region (118) is located in the PB doping layer (110); a fourth P+ injection region (120) and a fourth N+ injection region (121) are sequentially arranged from left to right in the second N well (109) region; a third P well (112) is arranged in the second deep P well (106) region, and a fifth P+ injection region (114) is arranged in the third P well (112) region;

[0030] A polysilicon gate oxide layer (122) is provided between the third P+ injection region (119) and the fourth P+ injection region (120), and the polysilicon gate oxide layer (122) is arranged across the surfaces of the second P well (108) and the second N well (109); the first P+ injection region (113), the fifth P+ injection region (114), the second P+ injection region (116), the second N+ injection region (117), and the third P+ injection region (119) are all connected to the cathode of the ESD / EOS integrated protection circuit, and the first N+ injection region (115), the third N+ injection region (118), the fourth P+ injection region (120), the fourth N+ injection region (121), and the polysilicon gate oxide layer (122) are all connected to the anode of the ESD / EOS integrated protection circuit.

[0031] The ESD / EOS integrated protection circuit of the high-reliability high-voltage driver chip includes: a Zener structure, a composite transistor structure, an SCR structure, an LDMOS structure and a metal wire, mainly composed of a first resistor R1, a second resistor R2, an NPN transistor T n1 、PNP transistor T p1 , LDMOS power tube M1, Zener tube Z D , anode and cathode;

[0032] The first resistor R1 is a parasitic resistor of the second N-well (109), the second resistor R2 is a parasitic resistor of the P-well (108), and the NPN transistor T n1The LDMOS power transistor M1 is composed of the second N well (109), the P well (108) and the second N+ injection region (117); the PNP transistor is composed of the fourth P+ injection region (120), the second N well (109) and the P well (108); the LDMOS power transistor M1 is composed of the fourth P+ injection region (120), the polysilicon gate oxide layer (122), the second N well (109), the P well (108) and the third P+ injection region (119); the Zener transistor Z D It is composed of the second N+ implantation region (117), the PB doping layer (110) and the P well (108).

[0033] In terms of working principle:

[0034] The ESD / EOS integrated protection circuit of the high-reliability high-voltage driver chip mainly includes: a fast-on path, an SCR main discharge path and a voltage-stabilizing clamping path;

[0035] The fast start path is as follows Figure 2 As shown, it includes: the Zener tube Z D , the second resistor R2, the first resistor R1, the PNP transistor T p1 and the NPN transistor T n1 ; The Zener tube Z D The cathode of the Zener tube Z is connected to the anode of the ESD / EOS protection circuit. D The anode of the NPN transistor T n1 One end of the second resistor R2 is connected to the anode of the ESD / EOS protection circuit, and the other end is connected to the PNP transistor T p1 The base of the PNP transistor T p1 The emitter of the PNP transistor T is connected to the anode of the ESD / EOS protection circuit. p1 The base of the NPN transistor T n1 The collector of the PNP transistor T p1 The collector of the NPN transistor T n1 One end of the first resistor R1 is connected to the base of the NPN transistor T n1 The other end is connected to the cathode of the ESD / EOS protection circuit; the NPN transistor T n1 The emitter of the Zener tube Z is connected to the cathode of the ESD / EOS protection circuit; wherein the Zener tube Z D Zener breakdown occurs, the PNP transistor T p1The base and collector of the NPN transistor T1 undergo avalanche breakdown, causing the voltage drop of the first resistor R1 to change faster than that of the second resistor R2. n1 than the PNP transistor T p1 First, it is turned on, and positive feedback occurs, causing the ESD / EOS integrated protection circuit to turn on; the drift current when it is not turned on has a regulating effect on the turning-on speed, which can improve the response speed of the ESD / EOS integrated protection circuit and reduce the trigger voltage;

[0036] The main discharge path of the SCR is as follows: Figure 3 As shown, it includes: the PNP transistor T p1 , the NPN transistor T n2 and the first resistor R1; when the voltage drop across the first resistor R1 reaches more than 0.7, the voltage drop across the second resistor R2 quickly also reaches more than 0.7, so that the main discharge path of the SCR is opened, thereby starting to discharge;

[0037] The voltage stabilization clamping path is as follows Figure 4 As shown, it includes: the Zener tube Z D and the LDMOS power tube M1; the Zener tube Z D The voltage can be clamped when the ESD / EOS integrated protection circuit is turned on, so as to suppress the large retrace phenomenon of the on-state voltage caused by the large current injection after the SCR main discharge path is triggered and turned on, thereby enhancing the voltage resistance and latch immunity capabilities of the ESD / EOS integrated protection circuit; the source and gate of the LDMOS power tube M1 are respectively connected to the anode of the ESD / EOS integrated protection circuit, the drain of the LDMOS power tube M1 is connected to the cathode of the ESD / EOS integrated protection circuit, and the substrate electrode of the LDMOS power tube M1 is connected to the anode of the ESD / EOS integrated protection circuit through the second resistor R2; the LDMOS power tube M1 is turned on and discharges current when the ESD / EOS electrical stress continues to increase, so as to realize the high-voltage triggering function;

[0038] When the ESD or EOS electrical stress is relatively small, the leakage current formed by minority carrier drift in the ESD / EOS integrated protection circuit flows through the Zener transistor ZD, the second resistor R2, and the collector junction shared by the NPN transistor Tn1 and the PNP transistor Tp1, and converges on the first resistor R1 to form a first trigger current. The parasitic NPN transistor composed of the third N+ injection region (118), the PB doped layer (110), the P well (108) and the second N+ injection region (117) can form a second trigger current. The first trigger current and the second trigger current can improve the response speed of the ESD / EOS integrated protection circuit and reduce the trigger voltage.

[0039] When the ESD or EOS electrical stress is large, the voltage on the first resistor R1 in the ESD / EOS integrated protection circuit is continuously increased, and under the positive feedback effect of the NPN transistor Tp1 and the second transistor Tp2, the voltage on the second resistor R2 is continuously increased, and an ESD or EOS current discharge channel of the SCR structure can be formed, thereby enhancing the robustness of the ESD / EOS integrated protection circuit;

[0040] When the ESD or EOS electrical stress continues to increase, the LDMOS power tube M1 in the ESD / EOS integrated protection circuit is turned on and discharges current to achieve high-voltage triggering performance;

[0041] When ESD or EOS electrical stress increases and triggers the ESD / EOS integrated protection circuit to open, the Zener diode ZD can suppress the large retrace phenomenon of the on-state voltage caused by the large current discharge in the SCR structure, thereby enhancing the anti-latch capability of the ESD / EOS integrated protection circuit.

[0042] In addition, the ESD / EOS integrated protection circuit is applied to high-voltage driver chips in different power domains, and the Zener tube Z can be adjusted according to the power domain voltage and circuit working characteristics. D The number of cascades further enhances the voltage withstand and latch immunity capabilities of the ESD / EOS integrated protection circuit, such as Figure 5 shown.

[0043] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. An integrated electrostatic surge protection circuit for a high-reliability high-voltage driver chip, characterized in that: The electrostatic surge integrated protection circuit is arranged on the same P-type silicon substrate (100); The P-type silicon substrate (100) is provided with a first P-type epitaxial layer (101), an N-type buried layer (102), and a second P-type epitaxial layer (103) in sequence from left to right; A first deep P well (104) is provided on the first P-type epitaxial layer (101), a deep N well (105) is provided on the N-type buried layer (102), and a second deep P well (106) is provided on the second P-type epitaxial layer (103); A first P well (111) is provided in the first deep P well (104) region, and a first P+ injection region (113) is provided in the first P well (111) region; a first N well (107), a second P well (108), and a second N well (109) are provided in the deep N well (105) region from left to right, and a PB doping layer (110) is provided in the second P well (108) region; a first N+ injection region (115) is provided in the first N well (107) region; and a first N+ injection region (115) is provided in the second P well (108) region from left to right. There are a second P+ injection region (116), a second N+ injection region (117), a third N+ injection region (118), and a third P+ injection region (119), and the third N+ injection region (118) is located in the PB doping layer (110); a fourth P+ injection region (120) and a fourth N+ injection region (121) are sequentially arranged from left to right in the second N well (109) region; a third P well (112) is arranged in the second deep P well (106) region, and a fifth P+ injection region (114) is arranged in the third P well (112) region; A polysilicon gate oxide layer (122) is provided between the third P+ injection region (119) and the fourth P+ injection region (120), and the polysilicon gate oxide layer (122) is arranged across the surfaces of the second P well (108) and the second N well (109); The first P+ injection region (113), the fifth P+ injection region (114), the second P+ injection region (116), the second N+ injection region (117), and the third P+ injection region (119) are all connected to the cathode of the electrostatic surge integrated protection circuit, and the first N+ injection region (115), the third N+ injection region (118), the fourth P+ injection region (120), the fourth N+ injection region (121), and the polysilicon gate oxide layer (122) are all connected to the electrostatic surge integrated protection circuit.

2. The electrostatic surge integrated protection circuit of the high-reliability high-voltage driver chip according to claim 1 is characterized in that: In the electrostatic surge integrated protection circuit, the parasitic resistance of the second N well (109) forms a first resistor R1, the parasitic resistance of the P well (108) forms a second resistor R2, and the second N well (109), the P well (108) and the second N+ injection region (117) constitute an NPN transistor T n1 The fourth P+ injection region (120), the second N-well (109) and the P-well (108) constitute a PNP transistor; the fourth P+ injection region (120), the polysilicon gate oxide layer (122), the second N-well (109), the P-well (108) and the third P+ injection region (119) constitute an LDMOS power transistor M1; the second N+ injection region (117), the PB doped layer (110) and the P-well (108) constitute a Zener transistor Z D .

3. The electrostatic surge integrated protection circuit of the high-reliability high-voltage driver chip according to claim 2 is characterized in that: The Zener diode Z D The cathode of the Zener diode Z is connected to the anode of the electrostatic surge integrated protection circuit. D The anode of the NPN transistor T n1 One end of the second resistor R2 is connected to the anode of the electrostatic surge integrated protection circuit, and the other end is connected to the PNP transistor T p1 The base of the PNP transistor T is connected to the substrate electrode of the LDMOS power tube M1; p1 The emitter of the PNP transistor T is connected to the anode of the electrostatic surge integrated protection circuit. p1 The base of the NPN transistor T n1 The collector of the PNP transistor T p1 The collector of the NPN transistor T n1 One end of the first resistor R1 is connected to the base of the NPN transistor T n1 The other end is connected to the cathode of the electrostatic surge integrated protection circuit; the NPN transistor T n1 The emitter of the LDMOS power tube M1 is connected to the cathode of the electrostatic surge integrated protection circuit; the source and gate of the LDMOS power tube M1 are respectively connected to the anode of the electrostatic surge integrated protection circuit, and the drain of the LDMOS power tube M1 is connected to the cathode of the electrostatic surge integrated protection circuit.

4. The electrostatic surge integrated protection circuit of the high-reliability high-voltage driver chip according to claim 2 is characterized in that: The electrostatic surge integrated protection circuit includes: a fast opening path, an SCR main discharge path and a voltage stabilizing clamping path; the fast opening path includes: a Zener tube Z D , the second resistor R2, the first resistor R1, the PNP transistor T p1 With NPN transistor T n1 ; The SCR main discharge path includes: PNP transistor T p1 、NPN transistor T n2 and the first resistor R1; the voltage stabilizing clamping path includes: a Zener tube Z D And LDMOS power tube M1.

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