Pixel arrangement structure, micro-display chip and preparation method

Abstract

The invention discloses a pixel arrangement structure, a micro-display chip and a preparation method, and belongs to the technical field of display, the pixel arrangement structure comprises a plurality of repetitive components which are arranged in an array along a first direction and a second direction; each repeating assembly is provided with a first symmetry axis M1 and a second symmetry axis M2 which are perpendicular to each other, each repeating assembly comprises at least two pixel units symmetrically arranged on the two sides of the first symmetry axis M1, each pixel unit comprises a plurality of sub-pixels, at least one sub-pixel is configured to be a first sub-pixel used for emitting first color light, and at least one sub-pixel is configured to be a second sub-pixel used for emitting second color light. At least one sub-pixel is configured to be a second sub-pixel for emitting second color light, and at least one sub-pixel is configured to be a third sub-pixel for emitting third color light; the second sub-pixel of each pixel unit is arranged on the second symmetry axis M2, the first sub-pixel and the third sub-pixel are symmetrically arranged on the two sides of the second symmetry axis M2, and the pixel density of the display chip can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel arrangement structure, a micro display chip and a preparation method thereof. Background Art

[0002] Micro-LED (Micro-Light Emitting Diode) is an advanced display technology based on tiny LED chips of 0.1 to 100 microns. It has the advantages of high brightness, high contrast, low power consumption and fast response time. It can provide a wide color gamut and realistic color performance, while having a long life and high reliability. Micro-LED has shown broad application prospects in consumer electronics, automotive displays and medical equipment.

[0003] However, the current pixel density of Micro-LED still needs to be improved. Summary of the invention

[0004] Purpose of the invention: The present application provides a pixel arrangement structure, a micro display chip and a preparation method, aiming to improve the pixel density of Micro-LED.

[0005] Technical solution: The embodiment of the present application provides a pixel arrangement structure, including:

[0006] A plurality of repeating components are arranged in an array along a first direction and a second direction perpendicular to each other;

[0007] Each of the repeating components has a first symmetry axis M1 and a second symmetry axis M2 that are perpendicular to each other, and an extension direction of the first symmetry axis M1 is located between the first direction and the second direction, and intersects the first direction and the second direction respectively;

[0008] Each of the repeating components comprises at least two pixel units symmetrically arranged on both sides of the first symmetry axis M1, each of the pixel units comprises a plurality of sub-pixels, at least one of the sub-pixels is configured as a first sub-pixel for emitting a first color light, at least one of the sub-pixels is configured as a second sub-pixel for emitting a second color light, and at least one of the sub-pixels is configured as a third sub-pixel for emitting a third color light;

[0009] In each of the pixel units, the second sub-pixel is disposed on the second symmetry axis M2, and the first sub-pixel and the third sub-pixel are symmetrically disposed on both sides of the second symmetry axis M2.

[0010] In some embodiments, the sub-pixel is provided with a first electrode, and the first electrode is used to connect to a first contact point so that the sub-pixel can be driven individually;

[0011] In each of the repeating components, the first electrodes of the sub-pixels are distributed on both sides of the first symmetry axis M1.

[0012] In some embodiments, in each of the repeating components, the plurality of first electrodes of the plurality of sub-pixels are symmetrically arranged about the first symmetry axis M1.

[0013] In some embodiments, in each of the pixel units, the first electrode of the second sub-pixel is extended along the second symmetry axis M2, and the first electrodes of the first sub-pixel and the third sub-pixel are symmetrically arranged on both sides of the second symmetry axis M2.

[0014] In some embodiments, the first electrode of each of the sub-pixels extends toward a side close to the first symmetry axis M1, and an extension direction of the first electrode of the second sub-pixel is perpendicular to the first symmetry axis M1, and an extension direction of the first electrode of the first sub-pixel and the third sub-pixel is inclined to the first symmetry axis M1.

[0015] In some embodiments, in each of the pixel units, the first sub-pixel, the second sub-pixel and the third sub-pixel are arranged in a triangle; and / or each of the repeating components is in a square.

[0016] In some embodiments, in each of the pixel units, the distance between the second sub-pixel and the first symmetry axis M1 is greater than the distance between the first sub-pixel and the first symmetry axis M1; and / or,

[0017] The distance between the second sub-pixel and the first symmetry axis M1 is greater than the distance between the third sub-pixel and the first symmetry axis M1; and / or,

[0018] The distance between the first sub-pixel and the second sub-pixel is equal to the distance between the third sub-pixel and the second sub-pixel; and / or,

[0019] The distance between the first sub-pixel and the first symmetry axis M1 is equal to the distance between the third sub-pixel and the first symmetry axis M1.

[0020] Accordingly, an embodiment of the present application provides a micro display chip, including:

[0021] Driver substrate;

[0022] As in the pixel arrangement structure described in any of the above embodiments, a plurality of repeated components of the pixel arrangement structure are arranged in an array on the driving substrate along a first direction and a second direction perpendicular to each other.

[0023] In some embodiments, the driving substrate includes a plurality of first contacts, each of which is connected to a first electrode of a sub-pixel of the pixel arrangement structure.

[0024] In some embodiments, a plurality of the first contacts connected to each of the pixel units are arranged along a direction parallel to the first symmetry axis M1.

[0025] In some embodiments, in each of the repeating components, a plurality of the first contacts connected to the first electrodes of a plurality of the sub-pixels are distributed on both sides of a first symmetry axis M1 and are symmetrically arranged with respect to the first symmetry axis M1.

[0026] In some embodiments, the distances between two adjacent first contacts are equal; and / or,

[0027] The first contact point is equidistant from the first symmetry axis M1 .

[0028] In some embodiments, the sub-pixels of the pixel arrangement structure include a light-emitting unit and a light conversion unit disposed on the light-emitting unit, the light-emitting unit and the light conversion unit of the first sub-pixel are superimposed to emit a first color light, the light-emitting unit and the light conversion unit of the second sub-pixel are superimposed to emit a second color light, and the light-emitting unit and the light conversion unit of the third sub-pixel are superimposed to emit a third color light.

[0029] In some embodiments, the sub-pixels of the pixel arrangement structure are selected from one of LED, Mini-LED, and Micro-LED. Accordingly, the present application embodiment also provides a method for preparing a micro display chip, comprising:

[0030] Providing a drive substrate;

[0031] A pixel arrangement structure as described in any of the above embodiments is formed on the driving substrate, and a plurality of repeated components of the pixel arrangement structure are arranged in an array on the driving substrate along a first direction and a second direction perpendicular to each other.

[0032] In some embodiments, forming the pixel arrangement structure on the driving substrate includes:

[0033] forming bonding layers on the driving substrate and the light-emitting material layer respectively, and bonding the light-emitting material layer to the driving substrate through the bonding layers;

[0034] forming a plurality of light-emitting units on the light-emitting material layer;

[0035] forming a passivation layer on the plurality of light-emitting units;

[0036] A plurality of first electrodes are formed, each of which connects one of the light emitting units and a first contact of the driving substrate.

[0037] In some embodiments, the light emitting material layer is an LED epitaxial layer.

[0038] Beneficial effects: The pixel arrangement structure of the embodiment of the present application includes: a plurality of repeating components, arranged in an array along a first direction and a second direction perpendicular to each other; each repeating component has a first symmetry axis M1 and a second symmetry axis M2 perpendicular to each other, and the extension direction of the first symmetry axis M1 is located between the first direction and the second direction, and intersects with the first direction and the second direction respectively; each repeating component includes at least two pixel units symmetrically arranged on both sides of the first symmetry axis M1, each pixel unit includes a plurality of sub-pixels, at least one sub-pixel is configured as a first sub-pixel for emitting a first color light, at least one sub-pixel is configured as a second sub-pixel for emitting a second color light, and at least one sub-pixel is configured as a third sub-pixel for emitting a third color light; in each pixel unit, the second sub-pixel is arranged on the second symmetry axis M2, and the first sub-pixel and the third sub-pixel are symmetrically arranged on both sides of the second symmetry axis M2. The present application arranges a plurality of repeating components in an array along a first direction and a second direction, and in the repeating components, at least two pixel units are symmetrically arranged on both sides of a first symmetry axis M1, the second sub-pixel of each pixel unit is arranged on a second symmetry axis M2, and the first sub-pixel and the third sub-pixel are symmetrically arranged on both sides of the second symmetry axis M2, so that the actual area occupied by each pixel unit is reduced, and the pixel density can be improved under the condition of the same total area.

[0039] The micro display chip and the manufacturing method of the embodiment of the present application may include all the technical features and technical effects of the above-mentioned pixel arrangement structure, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solution in the present application, the drawings required for use in the description of the implementation methods will be briefly introduced below. Obviously, the drawings described below are only some implementation methods of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 is a schematic diagram of a pixel arrangement structure in the first related art;

[0042] Figure 2 is a schematic diagram of a pixel arrangement structure in a second related art;

[0043] Figure 3 A schematic diagram of a pixel arrangement structure provided by an embodiment of the present application;

[0044] Figure 4 for Figure 3 Schematic diagram of the structure of the repeating components in the;

[0045] Figure 5 For along Figure 3 Schematic cross-sectional view of the AB line;

[0046] Figure 6 For along Figure 3 Schematic cross-sectional view of the CD line;

[0047] Figure 7 For along Figure 3 Schematic cross-sectional view of the midline EF;

[0048] Figure 8 A flowchart of a method for preparing a micro display chip provided in an embodiment of the present application;

[0049] Fig. 9 A schematic structural diagram of a step in a method for preparing a micro display chip provided in an embodiment of the present application;

[0050] Fig.10 A schematic structural diagram of another step in a method for preparing a micro display chip provided in an embodiment of the present application;

[0051] Fig.11 A schematic structural diagram of another step in a method for preparing a micro display chip provided in an embodiment of the present application;

[0052] Fig.12 A schematic structural diagram of another step in a method for preparing a micro display chip provided in an embodiment of the present application;

[0053] Fig.13 A schematic structural diagram of another step in a method for preparing a micro display chip provided in an embodiment of the present application;

[0054] Figure numerals: 100-repeating component; 110-pixel unit; 111-sub-pixel; 1110-light-emitting unit; 1110'-light-emitting material layer; 1111-first sub-pixel; 1112-second sub-pixel; 1113-third sub-pixel; 112-first electrode; 113-passivation layer; 200-driving substrate; 210-first contact; 220-second contact; 230-bonding layer; 300-mask layer; 110'-full-color pixel; 1111'-red pixel; 1112'-green pixel; 1113'-blue pixel; X-first direction; Y-second direction. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0056] In the description of the present application, it should be understood that the terms "thickness", "upper", "lower", "top", "bottom", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In the description of the present application, "multiple" means two or more, and at least one means one, two or more, unless otherwise clearly and specifically defined.

[0057] In the description of the present application, the meanings of “on,” “over,” and “on” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also means “on something” including the presence of intermediate components or layers therebetween, and “on something” or “over something” means not only “on something” or “over something,” but also includes the meaning of “on something” or “over something” without any intermediate components or layers therebetween.

[0058] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may also be used in this application to describe the relationship of one element or component to another element or component shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the drawings. The device may be otherwise oriented, rotated 90 degrees or at other orientations, and the spatially relative descriptors used in this application may be interpreted accordingly.

[0059] The term "layer" as used in this application refers to a portion of a material including an area with a certain thickness. A layer may extend over the entire underlying or superstructure, or may have an extent less than the underlying or superstructure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically and / or along a tapered surface. A layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0060] As a preface to this application, two pixel arrangement structures are introduced:

[0061] See also Figure 1 A pixel arrangement structure shown includes a plurality of full-color pixel points 110' arranged in an array, and a full-color pixel point 110' includes a red pixel point 1111', a blue pixel point 1113' and two green pixel points 1112'. Each full-color pixel point 110' has a width of d1 and a length of d2; d1 is equal to 7um, d2 is equal to 7um, and the area of ​​a full-color pixel point 110' is d1*d2, that is, the area of ​​a full-color pixel point 110' is 7um*7um.

[0062] See also Figure 2 Another pixel arrangement structure shown includes a plurality of full-color pixel points 110' arranged in an array, and one full-color pixel point 110' includes a red pixel point 1111', a blue pixel point 1113', and a green pixel point 1112'. The width of the four full-color pixel points 110' is d3, and the length is d4; d3 is equal to 10.5um, d4 is equal to 14um, and the area of ​​the four full-color pixel points 110' is d3*d4, that is, the area of ​​one full-color pixel point 110' is 10.5um*14um / 4.

[0063] In the arrangement of the above two pixel arrangement structures, the area of ​​a full-color pixel 100' is relatively large, resulting in a low pixel density of the display device. In view of this, the embodiment of the present application provides a new pixel arrangement structure, which can improve the pixel density (Pixels Per Inch, PPI) of the display device by optimizing the arrangement. The embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0064] See also Figures 3 to 7 The pixel arrangement structure provided in the embodiment of the present application includes a plurality of repeating components 100, each of which has the same structure, and the plurality of repeating components 100 are arranged in an array along a first direction X and a second direction Y that are perpendicular to each other. That is, at least one repeating component 100 and at least another repeating component 100 are arranged along the first direction X, and at least one repeating component 100 and at least another repeating component 100 are arranged along the second direction Y. Figure 3 In the illustrated embodiment, four repeating components 100 are included, and the four repeating components 100 are arranged in a substantially square structure.

[0065] See also Figure 4In the embodiment of the present application, each repeating component 100 has a first axis of symmetry M1 and a second axis of symmetry M2, and the first axis of symmetry M1 and the second axis of symmetry M2 are perpendicular to each other. The extension direction of the first axis of symmetry M1 is located between the first direction X and the second direction Y, and intersects with the first direction X and the second direction Y respectively. That is, the plane coordinate system is fitted with the first direction X and the second direction Y, and the extension direction of the first axis of symmetry M1 is the direction extending from the origin of the plane coordinate system toward a quadrant formed by the first direction X and the second direction Y. The figure formed by each repeating component 100 is an axisymmetric figure symmetrical about the first axis of symmetry M1. After the figure formed by the repeating component 100 is folded in half along the first axis of symmetry M1, the two parts of the figure can overlap. It should be noted that, based on the factor of processing accuracy, the figure formed by the repeating component 100 may not be a perfect axisymmetric figure, as long as it is roughly symmetrical about the first axis of symmetry M1.

[0066] Please combine Figure 3 and Figure 4 Each repeating assembly 100 includes at least two pixel units 110 symmetrically arranged on both sides of the first symmetry axis M1. Optionally, each repeating assembly 100 includes two pixel units 110, which are arranged on both sides of the first symmetry axis M1 and are symmetrical about the first symmetry axis M1. Figure 3 As a whole, the repeating component 100 is considered as a repeating component, and each repeating component includes eight pixel units 110. It should be noted that each pixel unit 110 is a full-color pixel point, and each pixel unit 110 includes a plurality of sub-pixels 111. Among them, at least one sub-pixel 111 is configured as a first sub-pixel 1111 for emitting a first color light, at least one sub-pixel 111 is configured as a second sub-pixel 1112 for emitting a second color light, and at least one sub-pixel 111 is configured as a third sub-pixel 1113 for emitting a third color light.

[0067] It can be understood that the first color light, the second color light and the third color light are lights of different colors. In some embodiments, the first color light, the second color light and the third color light are blue light, green light and red light respectively; or the first color light, the second color light and the third color light are blue light, red light and green light respectively; or the first color light, the second color light and the third color light are green light, blue light and red light respectively; or the first color light, the second color light and the third color light are green light, red light and blue light respectively; or the first color light, the second color light and the third color light are red light, blue light and green light respectively; the first color light, the second color light and the third color light are red light, green light and blue light respectively. Different color lights are emitted by the first sub-pixel 1111, the second sub-pixel 1112 and the third sub-pixel 1113 to form a full-color pixel point together, thereby realizing the RGB (Red, Green, Blue) full-color display of the display device.

[0068] In each pixel unit 110, the second sub-pixel 1112 is arranged on the second symmetry axis M2, and the first sub-pixel 1111 and the third sub-pixel 1113 are symmetrically arranged on both sides of the second symmetry axis M2. By setting the repeating component 100 to be a symmetrical structure about the first symmetry axis M1 and the second symmetry axis M2, each repeating component 100 is roughly presented as a square structure, which can reduce space occupation and improve pixel density.

[0069] Specifically, in each pixel unit 110, at least two sub-pixels 111 are arranged along the first direction X, and at least two sub-pixels 111 are arranged along the second direction Y. Figure 4 In the two pixel units 110 of the repeating component 100 shown, the first sub-pixels 1111 are symmetrical to each other, the second sub-pixels 1112 are symmetrical to each other, and the third sub-pixels 1113 are symmetrical to each other. The first sub-pixels 1111 and the second sub-pixels 1112 of the pixel unit 110 on the upper right side of the first symmetry axis M1 are arranged along the first direction X, and the second sub-pixels 1112 and the third sub-pixels 1113 are arranged along the second direction Y. The first sub-pixels 1111 and the second sub-pixels 1112 of the pixel unit 110 on the lower left side of the first symmetry axis M1 are arranged along the second direction Y, and the second sub-pixels 1112 and the third sub-pixels 1113 are arranged along the first direction X.

[0070] By arranging the pixel arrangement structure in the above manner, the area occupied by each pixel unit 110 (ie, a full-color pixel point) can be reduced. Figure 4 The width of each repeating element 100 is d5 and the length is d6; d5 is equal to 6um, d6 is equal to 6um, that is, the area of ​​each repeating element 100 is 6um*6um, so the area of ​​a pixel unit is 6um*6um / 2. Figure 1The structure shown can save 31um of area for each full-color pixel. 2 Compared to Figure 2 The structure shown can save 18.75um of area per full-color pixel. 2 , which can significantly improve the pixel density of the display chip or display device.

[0071] Please refer to the Figure 3 and Figure 4 In some embodiments, each sub-pixel 111 is provided with a first electrode 112, and the first electrode 112 is used to connect to the first contact 210 of the driving substrate 200, so that the sub-pixel 111 can be driven individually. In each repeating component 100, the multiple first electrodes 112 of the multiple sub-pixels 111 are distributed on both sides of the first symmetry axis M1. Figure 4 The multiple first electrodes 112 of the pixel unit 110 on the upper right side of the first symmetric axis M1 are distributed on the upper right side of the first symmetric axis M1, and the multiple first electrodes 112 of the pixel unit 110 on the lower left side of the first symmetric axis M1 are distributed on the lower left side of the first symmetric axis M1.

[0072] Optionally, the first electrode 112 of the second subpixel 1112 extends along a direction perpendicular to the first symmetry axis M1 , and the first electrode 112 of the first subpixel 1111 and the first electrode 112 of the third subpixel 1113 extend along a direction inclined to the first symmetry axis M1 .

[0073] Optionally, in each repeating assembly 100 , the plurality of first electrodes 112 of the plurality of sub-pixels 111 are symmetrically arranged about the first symmetry axis M1 .

[0074] Optionally, in each pixel unit 110 , the first electrode 112 of the second sub-pixel 1112 is extended along the second symmetry axis M2 , and the first electrodes 112 of the first sub-pixel 1111 and the third sub-pixel 1113 are symmetrically arranged on both sides of the second symmetry axis M2 .

[0075] Optionally, the first electrode 112 of each sub-pixel 111 extends toward a side close to the first symmetry axis M1, and the extension direction of the first electrode 112 of the second sub-pixel 1112 is perpendicular to the first symmetry axis M1, and the extension direction of the first electrode 112 of the first sub-pixel 1111 and the third sub-pixel 1113 is inclined to the first symmetry axis M1.

[0076] Please refer to the Figure 3 and Figure 4In some embodiments, in each pixel unit 110, the first sub-pixel 1111, the second sub-pixel 1112, and the third sub-pixel 1113 are arranged in a triangle. By arranging the pixel units 110 in a triangle, the space occupied by each pixel unit 110 can be effectively reduced, which helps to further improve the pixel density. Among them, the triangle can be roughly an isosceles right triangle, the second sub-pixel 1112 is closer to the right-angled vertex of the isosceles right triangle, and the first sub-pixel 1111 and the third sub-pixel 1113 are closer to the hypotenuse (first symmetry axis M1) of the isosceles right triangle. And / or, in some embodiments, each repeating component 100 is square, which can effectively reduce the space occupied by each repeating component 100 and help to improve the pixel density.

[0077] Please refer again Figure 4 In each pixel unit 110, the first sub-pixel 1111 and the third sub-pixel 1113 are respectively disposed on both sides of the second sub-pixel 1112, forming two right-angled sides of an isosceles right triangle, and the first symmetry axis M1 forms the hypotenuse of the isosceles right triangle. Moreover, the first sub-pixel 1111 and the third sub-pixel 1113 are closer to the first symmetry axis M1 than the second sub-pixel 1112.

[0078] That is to say, in this embodiment, the spacing between the second sub-pixel 1112 and the first symmetry axis M1 is greater than the spacing between the first sub-pixel 1111 and the first symmetry axis M1; and / or, the spacing between the second sub-pixel 1112 and the first symmetry axis M1 is greater than the spacing between the third sub-pixel 1113 and the first symmetry axis M1; and / or, the spacing between the first sub-pixel 1111 and the second sub-pixel 1112 is equal to the spacing between the third sub-pixel 1113 and the second sub-pixel 1112; and / or, the spacing between the first sub-pixel 1111 and the first symmetry axis M1 is equal to the spacing between the third sub-pixel 1113 and the first symmetry axis M1.

[0079] Accordingly, an embodiment of the present application further provides a micro display chip, which can be a Micro-LED display chip, comprising a driving substrate 200 and a pixel arrangement structure of any one of the above-mentioned embodiments arranged on the driving substrate 200, in which a plurality of repeating components 100 are arranged in an array on the driving substrate 200 along a first direction X and a second direction Y that are perpendicular to each other.

[0080] The driving substrate 200 includes a driving circuit for providing an electrical signal to each sub-pixel 111 in the repeating component 100 to control the brightness. The driving substrate 200 can be a silicon-based complementary metal oxide semiconductor (CMOS) driving board or a thin film transistor (TFT) driving board.

[0081] Please also read Figure 5 , Figure 6 and Figure 7 In some embodiments, each sub-pixel 111 includes a light emitting unit 1110 , and the light emitting unit 1110 includes a first doped semiconductor layer, a second doped semiconductor layer, and an active layer located therebetween.

[0082] Optionally, an active layer is arranged between the first doped semiconductor layer and the second doped semiconductor layer and provides light. The active layer is a layer that recombine electrons and holes provided from the first doped semiconductor layer and the second doped semiconductor layer, respectively, and outputs light of a specific wavelength, and the active layer may have a single quantum well structure or a multiple quantum well (MQW) structure and well layers and barrier layers alternately stacked.

[0083] Optionally, the first doped semiconductor layer is an n-type semiconductor layer, and the second doped semiconductor layer is a p-type semiconductor layer; for example, the first doped semiconductor layer may be n-type GaN, n-type InGaN, n-type AlInGaP, etc.; the second doped semiconductor layer may be p-type GaN, p-type InGaN or p-type AlInGaP, etc.

[0084] Optionally, the sub-pixel 111 in the micro display chip is selected from one of LED, Mini-LED, and Micro-LED.

[0085] In some embodiments, the size of each sub-pixel 111 is 0.1 to 10 micrometers, and the spacing between adjacent sub-pixels 111 is 1 to 10 micrometers.

[0086] like Figure 5 The driving substrate 200 includes a second contact 220 , and the second contact 220 is electrically connected to the second doped semiconductor layer of the sub-pixel 111 through a bonding layer 230 .

[0087] like Figure 6 and Figure 7As shown, the driving substrate 200 includes a plurality of first contacts 210, each of which is connected to a first electrode 112 of a sub-pixel 111 of the pixel arrangement structure and is electrically connected to the first doped semiconductor layer of the sub-pixel 111 through the first electrode 112. Each sub-pixel 111 is driven individually by the driving substrate 200.

[0088] Optionally, the micro display chip may be a common anode structure or a common cathode structure, or may be a structure in which the anode and cathode are independent of each other.

[0089] In some embodiments, the material of the first electrode 112 can be a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO) or zinc oxide (ZnO), or can also be Cr, Ti, Pt, Au, Al, Cu, Ge or Ni.

[0090] Please refer again Figure 4 In some embodiments, a plurality of first contacts 210 connected to each pixel unit 110 are arranged along a direction parallel to the first symmetry axis M1.

[0091] In some embodiments, in each repeating component 100 , a plurality of first contacts 210 connected to the first electrodes 112 of a plurality of sub-pixels 111 are distributed on both sides of the first symmetry axis M1 and are symmetrically arranged about the first symmetry axis M1 .

[0092] In some embodiments, the distance between two adjacent first contacts 210 is equal; and / or the distance between the first contacts 210 and the first symmetry axis M1 is equal.

[0093] In some embodiments, the distance between the first contact 210 and the first symmetry axis M1 is smaller than the distance between the light emitting unit 1110 of the sub-pixel 111 and the first symmetry axis M1.

[0094] See also Figure 7 In some embodiments, the spacing L4 between adjacent sub-pixels 111 is 1 to 10 micrometers, and the spacing between adjacent sub-pixels 111 is the distance between the central axes of the light-emitting units 1110 of two adjacent sub-pixels 111 extending in the thickness direction.

[0095] In some embodiments, in the repeating component 100, the first contacts 210 connected to the first sub-pixels 1111 have a first distance L1, and the two first sub-pixels 1111 have a second distance L2, satisfying: L1 <L2。

[0096] It can be understood that in the embodiment of the present application, by making the first distance L1 smaller than the second distance L2 in the repeating component 100, the area of ​​one pixel unit 110 can be reduced under the condition that the area of ​​the display device is the same, thereby improving the pixel density of the display device.

[0097] In some embodiments, the first contacts 210 connected to the second sub-pixels 1112 in the repeating component 100 have a third distance L3, and the two second sub-pixels 1112 have a fourth distance L4, satisfying: L3 <L4。

[0098] It can be understood that in the embodiment of the present application, by making the third distance L3 smaller than the fourth distance L4 in the repeating component 100, the area of ​​one pixel unit 110 can be reduced under the condition that the area of ​​the display device is the same, thereby improving the pixel density of the display device.

[0099] In some embodiments, in the repeating component 100, the first contacts 210 connected to the third sub-pixels 1113 have a fifth distance L5, and the two third sub-pixels 1113 have a sixth distance L6, satisfying: L5 <L6。

[0100] It can be understood that in the embodiment of the present application, by making the fifth distance L5 smaller than the sixth distance L6 in the repeating component 100, the area of ​​one pixel unit 110 can be reduced under the condition that the area of ​​the display device is the same, thereby improving the pixel density of the display device.

[0101] In some embodiments, the sub-pixel 111 of the pixel arrangement structure includes a light-emitting unit 1110 and a light conversion unit (not shown) disposed on the light-emitting unit 1110. The light-emitting unit 1110 and the light conversion unit of the first sub-pixel 1111 are superimposed to emit a first color light, the light-emitting unit 1110 and the light conversion unit of the second sub-pixel 1112 are superimposed to emit a second color light, and the light-emitting unit 1110 and the light conversion unit of the third sub-pixel 1113 are superimposed to emit a third color light. The light conversion unit may be made of a wavelength conversion material, or may be made of a transmissive reflective material.

[0102] In some embodiments, the micro display chip further includes a passivation layer 113 , and the passivation layer 113 covers the side surfaces of the light emitting units 1110 to electrically isolate the light emitting units 1110 .

[0103] In some embodiments, the material of the passivation layer 113 can be an inorganic material or an organic material. The inorganic material includes any one or a combination of SiO2, Al2O3, ZrO2, TiO2, Si3N4, and HfO2; the organic material includes any one or a combination of black matrix photoresist, color filter photoresist, polyimide, barrier glue (BANK), overcoat glue, near-ultraviolet negative photoresist, and styrene.

[0104] See also Figure 8 The present application embodiment provides a method for preparing a micro display chip, the method comprising:

[0105] S10: providing a driving substrate 200;

[0106] S20 : ​​forming a pixel arrangement structure of any of the above embodiments on the driving substrate 200 , so that a plurality of repeated components 100 of the pixel arrangement structure are arranged in an array on the driving substrate 200 along a first direction X and a second direction Y that are perpendicular to each other.

[0107] Specifically, a pixel arrangement structure is formed on the driving substrate 200, including:

[0108] like Fig. 9 , a bonding layer 230 is formed on the driving substrate 200 and the light-emitting material layer 1110', respectively, and the light-emitting material layer is bonded to the driving substrate 200 through the bonding layer 230. Among them, the light-emitting material layer 1110' can be an LED epitaxial layer, which is formed by one or more layers of semiconductor materials deposited on a substrate material by epitaxial growth technology. The bonding layer 230 can be plated on the driving substrate 200 and the light-emitting material layer 1110', and is a metal material for high-voltage and high-temperature bonding, and is also used for electrical connection between the second doped semiconductor layer and the second contact 220. Among them, the light-emitting material layer 1110' can be blue light GaN (blue light material).

[0109] like Fig.10 and Fig.11 , forming a plurality of light-emitting units 1110 on the light-emitting material layer 1110'. Specifically, the bonded sample is masked by mask layer 300, and the light-emitting unit 1110mesa is formed by mask etching. The material of the mask layer 300 may be organic resin, organic black matrix photoresist, or the like.

[0110] like Fig.12 , a passivation layer 113 is formed on the plurality of light emitting units 1110. Specifically, the passivation layer 113 covering the mesa of the light emitting unit 1110 is formed by coating and mask etching.

[0111] like Fig.13, forming a plurality of first electrodes 112, each of which connects a light-emitting unit 1110 and a first contact 210 of the driving substrate 200. Specifically, through masking, coating, and stripping, the first electrode 112 is formed to contact the first contact 210, and the Micro-LED manufacturing is completed.

[0112] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0113] The pixel arrangement structure, microdisplay chip and preparation method provided in the embodiments of the present application are introduced in detail above, and the principles and implementation methods of the present application are explained by using specific examples. The description of the above embodiments is only used to help understand the technical solution and its core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present application.

Claims

1. A pixel arrangement structure, characterized in that: include: A plurality of repeating components (100) are arranged in an array along a first direction (X) and a second direction (Y) that are perpendicular to each other; Each of the repeating components (100) has a first symmetry axis M1 and a second symmetry axis M2 that are perpendicular to each other, and the extension direction of the first symmetry axis M1 is located between the first direction (X) and the second direction (Y), and intersects the first direction (X) and the second direction (Y) respectively; Each of the repeating components (100) comprises at least two pixel units (110) symmetrically arranged on both sides of the first symmetry axis M1, each of the pixel units (110) comprises a plurality of sub-pixels (111), at least one of the sub-pixels (111) is configured as a first sub-pixel (1111) for emitting a first color light, at least one of the sub-pixels (111) is configured as a second sub-pixel (1112) for emitting a second color light, and at least one of the sub-pixels (111) is configured as a third sub-pixel (1113) for emitting a third color light; In each of the pixel units (110), the second sub-pixel (1112) is arranged on the second symmetry axis M2, and the first sub-pixel (1111) and the third sub-pixel (1113) are symmetrically arranged on both sides of the second symmetry axis M2.

2. The pixel arrangement structure according to claim 1, characterized in that: The sub-pixel (111) is provided with a first electrode (112), and the first electrode (112) is used to connect to a first contact (210), so that the sub-pixel (111) can be driven independently; In each of the repeating components (100), the plurality of first electrodes (112) of the plurality of sub-pixels (111) are distributed on both sides of the first symmetry axis M1.

3. The pixel arrangement structure according to claim 2, characterized in that: In each of the repeating components (100), the plurality of first electrodes (112) of the plurality of sub-pixels (111) are symmetrically arranged about the first symmetry axis M1.

4. The pixel arrangement structure according to claim 2, characterized in that: In each of the pixel units (110), the first electrode (112) of the second sub-pixel (1112) is extended along a second symmetry axis M2, and the first electrode (112) of the first sub-pixel (1111) and the third sub-pixel (1113) are symmetrically arranged on both sides of the second symmetry axis M2.

5. The pixel arrangement structure according to claim 4, characterized in that: The first electrode (112) of each of the sub-pixels (111) extends toward a side close to the first symmetry axis M1, and the extension direction of the first electrode (112) of the second sub-pixel (1112) is perpendicular to the first symmetry axis M1, and the extension directions of the first electrode (112) of the first sub-pixel (1111) and the third sub-pixel (1113) are inclined to the first symmetry axis M1.

6. The pixel arrangement structure according to claim 1, characterized in that: In each of the pixel units (110), the first sub-pixel (1111), the second sub-pixel (1112), and the third sub-pixel (1113) are arranged in a triangle; and / or each of the repeating components (100) is in a square.

7. The pixel arrangement structure according to claim 1, characterized in that: In each of the pixel units (110), the distance between the second sub-pixel (1112) and the first symmetry axis M1 is greater than the distance between the first sub-pixel (1111) and the first symmetry axis M1; and / or, The distance between the second sub-pixel (1112) and the first symmetry axis M1 is greater than the distance between the third sub-pixel (1113) and the first symmetry axis M1; and / or, The distance between the first sub-pixel (1111) and the second sub-pixel (1112) is equal to the distance between the third sub-pixel (1113) and the second sub-pixel (1112); and / or, The distance between the first sub-pixel (1111) and the first symmetry axis M1 is equal to the distance between the third sub-pixel (1113) and the first symmetry axis M1.

8. A micro display chip, characterized in that: include: A driving substrate (200); According to any one of claims 1 to 7, a plurality of repeated components (100) of the pixel arrangement structure are arranged in an array on the driving substrate (200) along a first direction (X) and a second direction (Y) that are perpendicular to each other.

9. The micro display chip according to claim 8, characterized in that: The driving substrate (200) comprises a plurality of first contacts (210), each of the first contacts (210) being connected to a first electrode (112) of a sub-pixel (111) of the pixel arrangement structure.

10. The micro display chip according to claim 9, characterized in that: A plurality of the first contacts (210) connected to each pixel unit (110) are arranged in an array along a direction parallel to the first symmetry axis M1.

11. The micro display chip according to claim 9, characterized in that: In each of the repeating components (100), a plurality of the first contacts (210) connected to the first electrodes (112) of a plurality of the sub-pixels (111) are distributed on both sides of a first symmetry axis M1 and are symmetrically arranged about the first symmetry axis M1.

12. The micro display chip according to claim 11, characterized in that: The distances between two adjacent first contacts (210) are equal; and / or, The first contact point (210) is equidistant from the first symmetry axis M1.

13. The micro display chip according to claim 8, characterized in that: The sub-pixel (111) of the pixel arrangement structure comprises a light-emitting unit (1110) and a light conversion unit arranged on the light-emitting unit (1110); the light-emitting unit (1110) and the light conversion unit of the first sub-pixel (1111) are superimposed to emit a first color light, the light-emitting unit (1110) and the light conversion unit of the second sub-pixel (1112) are superimposed to emit a second color light, and the light-emitting unit (1110) and the light conversion unit of the third sub-pixel (1113) are superimposed to emit a third color light.

14. The micro display chip according to claim 8, characterized in that: The sub-pixel (111) of the pixel arrangement structure is selected from one of LED, Mini-LED and Micro-LED.

15. A method for preparing a micro display chip, characterized in that: include: Providing a driving substrate (200); A pixel arrangement structure as claimed in any one of claims 1 to 8 is formed on the driving substrate (200), wherein a plurality of repeated components (100) of the pixel arrangement structure are arranged in an array on the driving substrate (200) along a first direction (X) and a second direction (Y) that are perpendicular to each other.

16. The method for preparing a micro display chip according to claim 15, characterized in that: The pixel arrangement structure is formed on the driving substrate (200), comprising: forming bonding layers (230) on the driving substrate (200) and the light-emitting material layer (1110'), respectively, and bonding the light-emitting material layer (1110') to the driving substrate (200) via the bonding layer (230); forming a plurality of light-emitting units (1110) on the light-emitting material layer (1110'); forming a passivation layer (113) on the plurality of light-emitting units (1110); A plurality of first electrodes (112) are formed, each of the first electrodes (112) connecting one of the light-emitting units (1110) and one of the first contacts (210) of the driving substrate (200).

17. The method for preparing a micro display chip according to claim 16, characterized in that: The light-emitting material layer (1110') is an LED epitaxial layer.

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