Semiconductor device assembly with circular segmented package edge

Abstract

Embodiments described herein relate to various semiconductor device assemblies. In some embodiments, a semiconductor device assembly includes: a circuit substrate including: a first substrate surface; a second substrate surface disposed opposite the first substrate surface; and a substrate edge extending from the first substrate surface to the second substrate surface; a series of holes arranged along the substrate edge of the circuit substrate, where each hole of the series of holes extends at least partially from the first substrate surface toward the second substrate surface; at least one die disposed on the first substrate surface; and a package housing disposed over the first substrate surface, where the package housing encapsulates the at least one die and the first substrate surface, and where the package housing fills each hole in the series of holes.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 387,432, filed on December 14, 2022, and entitled “SEMICONDUCTOR DEVICE ASSEMBLY WITH A CIRCULAR SEGMENTED PACKAGE EDGE” and U.S. Non-Provisional Patent Application No. 18 / 530,905, filed on December 6, 2023, and entitled “SEMICONDUCTOR DEVICE ASSEMBLY WITH A CIRCULAR SEGMENTED PACKAGE EDGE”. The disclosure of the prior application is considered part of and incorporated by reference into this patent application. Technical Field

[0003] The present disclosure generally relates to semiconductor devices and methods of forming semiconductor devices. For example, the present disclosure relates to a semiconductor device assembly having a rounded segmented package edge. Background Art

[0004] A semiconductor package includes a semiconductor substrate, one or more semiconductor electronic components coupled to and / or embedded in the semiconductor substrate, and a housing formed above the semiconductor substrate to encapsulate the one or more semiconductor electronic components. One or more semiconductor electronic components are interconnected by electrical interconnects to form one or more semiconductor devices, such as one or more integrated circuits (ICs) (e.g., one or more bare die or chips). For example, semiconductor electronic components and electrical interconnects may be manufactured on a semiconductor wafer before being cut into bare die or chips to form one or more ICs and then packaged. A semiconductor package may be referred to as a semiconductor chip package including one or more ICs. The semiconductor package protects the semiconductor electronic components and electrical interconnects from damage and includes means for connecting the semiconductor electronic components and electrical interconnects to external components (e.g., circuit substrates), such as via balls, pins, leads, contact pads, or other electrical interconnect structures. A semiconductor device assembly may be or may include a semiconductor package or one or more components of a semiconductor package (e.g., one or more semiconductor devices with or without a housing).

[0005] The electronic system assembly may include a plurality of semiconductor packages electrically coupled to a carrier substrate (e.g., a circuit substrate). The electronic system assembly may include additional system components electrically coupled to the carrier substrate. The carrier substrate may include electrical interconnects and conductive paths for interconnecting system components (including a plurality of semiconductor packages and other system components of the electronic system assembly). Thus, a plurality of semiconductor packages may be electrically connected to each other and / or to one or more additional system components via the carrier substrate to form the electronic system assembly. For example, other system components may include passive components (e.g., storage capacitors), processing units (e.g., central processing units (CPUs), graphics processing units (GPUs), microprocessors, and / or microcontrollers), control units (e.g., microcontrollers, memory controllers, and / or power management controllers), or one or more other electronic components. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram of an example device that can be fabricated using the techniques described herein.

[0007] Figure 2 is a diagram of an example memory device that can be fabricated using the techniques described herein.

[0008] Figure 3A An example circuit substrate assembly strip is illustrated according to one or more implementations.

[0009] Figure 3B Illustrated are top and perspective views of an example substrate edge along which a series of holes are formed according to one or more implementations.

[0010] Figure 4 A front view illustrating an example semiconductor device assembly that may be fabricated using the techniques described herein, in accordance with one or more implementations.

[0011] Figure 5A A front view illustrating an example semiconductor device assembly that may be fabricated using the techniques described herein, in accordance with one or more implementations.

[0012] Figure 5B Description of the invention according to one or more embodiments Figure 5A A top view of the semiconductor device assembly described in .

[0013] Figure 5C Description of the invention according to one or more embodiments Figure 5A A side view of the semiconductor device assembly illustrated in FIG.

[0014] Figures 6A to 6G A process flow of an example method of forming one or more semiconductor device assemblies is described.

[0015] Figure 7is a flow chart of an example method of forming an integrated assembly or memory device having a semiconductor package assembly with rounded segmented package edges.

[0016] Figure 8 is a flow chart of an example method of forming an integrated assembly or memory device having a semiconductor package assembly with rounded segmented package edges. DETAILED DESCRIPTION

[0017] A semiconductor package assembly may be a type of semiconductor device assembly that is constructed to house one or more dies. During manufacturing, one or more dies are mounted to a device region of a circuit substrate (e.g., an assembly strip) and a package housing material (e.g., a molding compound) is formed over the device region to encapsulate the one or more dies. For example, singulation is performed by sawing through the package housing material and the circuit substrate along a sawing path to separate the device region from the remainder of the circuit substrate and form a semiconductor package assembly whose package edge is defined by the sawing path along which the sawing is performed. Thus, the package edge defines the outer perimeter of the semiconductor device assembly.

[0018] In some cases, the die edge of the die may be positioned very close to the sawing path (e.g., the package edge). This scenario becomes more common as the size of semiconductor device assemblies becomes smaller and more compact. As the size of semiconductor device assemblies decreases, the sawing path used to make the package edge moves closer to the die edge of the die covered by the package shell material. Due to the sawing performed along the sawing path, vibrations are generated during singulation. Cracks at the circuit substrate (particularly at the die edge) may occur during sawing due to mechanical stress generated by vibration, where the circuit substrate is most susceptible to vibration. Therefore, substrate cracks (e.g., crack lines) may be formed during singulation. Substrate cracks may cause delamination between the package shell material and the circuit substrate to occur at the substrate crack, resulting in possible failure of the semiconductor package assembly.

[0019] The mechanical stress applied to the circuit substrate at the die edge during singulation (e.g., due to vibration) increases as the distance between the die edge and the saw path decreases. For example, die edge to package edge distances of less than 100 micrometers (μm) are becoming more common. The circuit substrate at the die edge is increasingly susceptible to cracking when the die edge to package edge distance is less than 100 μm. Thus, substrate cracks formed at the die edge are becoming more common as the size of semiconductor device assemblies decreases.

[0020] In some implementations, the weakest zone of the circuit substrate is offset from the die edge to the saw path (eg, to the package edge). Thus, the occurrence of substrate cracks formed during singulation can be reduced or completely prevented.

[0021] For example, in some implementations, a series of holes are formed in the circuit substrate along one or more saw paths to offset the weakest zone of the circuit substrate from the die edge to the saw path where the series of holes are formed (e.g., to the package edge). The series of holes is configured to simplify the singulation process, thereby preventing cracks from occurring in the circuit substrate at the die edge. For example, by forming the series of holes along the die path, vibrations that would have been transmitted to the die edge during singulation can be reduced. Thus, substrate cracks at the die edge can be prevented even when the distance between the die edge and the saw path is reduced.

[0022] During the singulation process, cutting is performed along the sawing path through the series of holes, leaving a portion of each hole (e.g., as a circular segment) as part of the substrate edge of the circuit substrate. This substrate edge coincides with the package edge of the semiconductor package assembly. In addition, the package shell material is used to fill the series of holes during the encapsulation process (e.g., before singulation). In this way, the package shell material is mechanically (e.g., structurally) interlocked with the circuit substrate at the substrate edge / package edge. Therefore, the holes filled after singulation remain at the substrate edge, which can provide additional mechanical strength to the substrate edge.

[0023] In some embodiments, the series of holes are blind holes that partially extend through the circuit substrate. In some embodiments, the series of holes are through holes that extend completely through the circuit substrate. In either case, the encapsulation shell material can be used to fill the series of holes, thereby improving the mechanical strength of the circuit substrate at the edge of the substrate.

[0024] Figure 1 1 is a diagram of an example apparatus 100 that can be manufactured using the techniques described herein. Apparatus 100 may include any type of device or system that includes one or more integrated circuits 105. For example, apparatus 100 may include a memory device, a flash memory device, a NAND memory device, a NOR memory device, a random access memory (RAM) device, a read-only memory (ROM) device, a dynamic RAM (DRAM) device, a static RAM (SRAM) device, a solid state disk (SSD), a microchip, and / or a system-on-a-chip (SoC), among other examples. In some cases, apparatus 100 may be referred to as a semiconductor package, an assembly, a semiconductor device assembly, or an integrated assembly.

[0025] like Figure 1, the apparatus 100 may include one or more integrated circuits 105 (shown as a first integrated circuit 105-1 and a second integrated circuit 105-2) disposed on a substrate 110. The integrated circuit 105 may include any type of circuit, such as an analog circuit, a digital circuit, a radio frequency (RF) circuit, a power supply, a power management circuit, an input-output (I / O) chip, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), and / or a memory device (e.g., a NAND memory device, a NOR memory device, a RAM device, or a ROM device). The integrated circuit 105 may be mounted on a surface of the substrate 110 or otherwise disposed on the surface. Although the apparatus 100 is shown as including two integrated circuits 105 as an example, the apparatus 100 may include a different number of integrated circuits 105.

[0026] In some implementations, the integrated circuit 105 can include a single semiconductor die 115 (sometimes referred to as a die), as shown by the first integrated circuit 105-1. In some implementations, the integrated circuit 105 can include multiple semiconductor dies 115 (sometimes referred to as dies), as shown by the second integrated circuit 105-2, which is shown to include five semiconductor dies 115-1 to 115-5.

[0027] like Figure 1 , for an integrated circuit 105 that includes multiple dies 115, the dies 115 may be stacked on top of each other to reduce the footprint of the device 100. In some implementations, there may be spacers between the dies 115 that are adjacent to each other in the stack to achieve electrical separation and heat dissipation. The stacked dies 115 may include three-dimensional electrical interconnects (e.g., through silicon vias (TSVs)) for routing electrical signals between the dies 115. Although the integrated circuit 105-2 is shown as including five dies 115, the integrated circuit 105 may include a different number of dies 115 (e.g., at least two dies 115). A first die 115-1 (sometimes referred to as a bottom die or base die) may be disposed on the substrate 110, a second die 115-2 may be disposed on the first die 115-1, and so on. Although Figure 1 The die 115 are shown stacked in a straight stack (e.g., with aligned die edges), but in some embodiments, the die 115 may be stacked in a different arrangement, such as a tiled stack (e.g., with misaligned die edges that provide space for wire bonding near the edges of the die 115).

[0028] Device 100 may include housing 120 that protects internal components of device 100 (e.g., integrated circuit 105) from damage and environmental elements (e.g., particles) that may cause malfunction of device 100. Housing 120 may be a molding compound, plastic (e.g., epoxy plastic), ceramic, or another type of material, depending on the functional requirements of device 100.

[0029] In some implementations, the device 100 can be included as part of a higher-level system (e.g., a computer, a mobile phone, a network device, an SSD, a vehicle, or an Internet of Things device), for example, by electrically connecting the device 100 to a circuit board 125 (e.g., a printed circuit board). For example, the substrate 110 can be disposed on the circuit board 125 such that the electrical contacts 130 (e.g., bonding pads) of the substrate 110 are electrically connected to the electrical contacts 135 (e.g., bonding pads) of the circuit board 125.

[0030] In some implementations, the substrate 110 can be mounted on the circuit board 125 using solder balls 140 (e.g., arranged in a ball grid array), which can be melted to form a physical and electrical connection between the substrate 110 and the circuit board 125. Additionally or alternatively, the substrate 110 can be mounted on and / or electrically connected to the circuit board 125 using another type of connector (e.g., pins or leads). Similarly, the integrated circuit 105 can include electrical pads (e.g., bonding pads) that are electrically connected to corresponding electrical pads (e.g., bonding pads) of the substrate 110 using electrical bonds (e.g., wire bonds, bump bonds, or the like). The interconnections between the integrated circuit 105, the substrate 110, and the circuit board 125 enable the integrated circuit 105 to receive and transmit signals to other components of the device 100 and / or higher-level systems.

[0031] As indicated above, provide Figure 1 As an example. Other examples may differ from the Figure 1 Described example.

[0032] Figure 2 2 is a diagram of an example memory device 200 that can be manufactured using the techniques described herein. Figure 1An example of the described apparatus 100. The memory device 200 may be any electronic device configured to store data in a memory. In some implementations, the memory device 200 may be an electronic device configured to persistently store data in the non-volatile memory 205. For example, the memory device 200 may be a hard drive, an SSD, a flash memory device (e.g., a NAND flash memory device or a NOR flash memory device), a universal serial bus (USB) thumb drive, a memory card (e.g., a secure digital (SD) card), a secondary storage device, a non-volatile memory express (NVMe) device, and / or an embedded multimedia card (eMMC) device.

[0033] As shown, the memory device 200 may include a nonvolatile memory 205, a volatile memory 210, and a controller 215. The components of the memory device 200 may be mounted or otherwise disposed on a substrate 220. In some implementations, the nonvolatile memory 205 includes stacked semiconductor dies 225, as described above in conjunction with Figure 1 described.

[0034] The non-volatile memory 205 may be configured to maintain stored data after the memory device 200 is powered off. For example, the non-volatile memory 205 may include a NAND memory or a NOR memory. The volatile memory 210 may require power to maintain the stored data and may lose the stored data after the memory device 200 is powered off. For example, the volatile memory 210 may include one or more latches and / or RAM, such as DRAM and / or SRAM. As an example, the volatile memory 210 may cache data read from or written to the non-volatile memory 205, and / or may cache instructions to be executed by the controller 215.

[0035] The controller 215 may be any device configured to communicate with the non-volatile memory 205, the volatile memory 210, and the host device (e.g., via a host interface of the memory device 200). For example, the controller 215 may include a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some implementations, the memory device 200 may be included in a system including a host device. The host device may include one or more processors configured to execute instructions and store data in the non-volatile memory 205.

[0036] The controller 215 may be configured to control the operation of the memory device 200, for example, by executing one or more instructions (sometimes referred to as commands). For example, the memory device 200 may store the one or more instructions as firmware, and the controller 215 may execute the one or more instructions. Additionally or alternatively, the controller 215 may receive the one or more instructions from the host device via the host interface, and may execute the one or more instructions. For example, the controller 215 may transmit signals to and / or receive signals from the non-volatile memory 205 and / or the volatile memory 210 based on the one or more instructions, such as transferring (e.g., writing or programming) data to the non-volatile memory 205 (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes of the non-volatile memory 205), transferring (e.g., reading) data from the non-volatile memory 205, and / or erasing all or a portion of the non-volatile memory 205.

[0037] As indicated above, provide Figure 2 As an example. Other examples may differ from the Figure 2 Describe the example. Provide Figure 2 The number and arrangement of components shown in FIG. are examples. In fact, compared to Figure 2 There may be additional components, fewer components, different components, or differently arranged components than those shown in FIG.

[0038] Figure 3A An example circuit substrate assembly strip 300 is illustrated according to one or more implementations. The circuit substrate assembly strip 300 may be a printed circuit board (PCB) assembly strip or another type of circuit substrate on which various device components are mounted. The circuit substrate assembly strip 300 includes a plurality of device regions 302, which are shown as four device regions 302-1 to 302-4. Each device region 302 is configured to become part of a separate semiconductor device assembly after a singulation process. Thus, each device region 302 is configured to have a set of corresponding device components mounted thereto, which will be covered by the housing material and ultimately singulated as parts of separate semiconductor device assemblies. The set of corresponding device components may include, for example, one or more integrated circuits (e.g., one or more bare dies), one or more controllers (e.g., microcontrollers, memory controllers, etc.), and one or more passive components (e.g., capacitors or resistors).

[0039] According to the present example, four semiconductor device assemblies can be generated from the four device regions 302-1 to 302-4 based on a one-to-one correspondence. However, it will be appreciated that the number of device regions may be less than or greater than four. Each semiconductor device assembly is a combination of the above Figure 1 An example of the apparatus 100 described herein. In some implementations, each semiconductor device assembly may be similar to a combination of Figure 2The memory device 200 is described as a memory device.

[0040] Each device region 302 is delineated by a plurality of first singulation paths 304 shown as first singulation paths 304-1 to 304-3 and a plurality of second singulation paths 306 shown as second singulation paths 306-1 to 306-3. The first singulation paths 304 extend parallel to the y-axis and the second singulation paths 306 extend parallel to the x-axis. In some implementations, the first singulation paths 304 and the second singulation paths 306 are zigzag paths along which the device regions 302 are singulated (e.g., separated) by sawing. After singulation, each device region 302 is defined by substrate edges formed by singulation (e.g., sawing) along the first singulation paths 304 and the second singulation paths 306. These substrate edges may be portions of corresponding package edges of a semiconductor device assembly. In other words, each substrate edge may coincide with a package edge of a corresponding semiconductor device assembly.

[0041] Additionally, a series of holes 308 can be formed along some or all of the first singulation path 304 and the second singulation path 306. In some implementations, the series of holes 308 are through holes that extend completely through the circuit substrate assembly strip 300. In some implementations, the series of holes 308 are blind holes that extend only partially through the circuit substrate assembly strip 300.

[0042] The plurality of series of holes 308 are shown as series of holes 308-1 through 308-6 formed along the substrate edge of the device region 302. In the present example, the series of holes 308 are formed along the first singulation path 304. Thus, the device region 302 is demarcated by the series of holes 308 along its substrate edge extending parallel to the y-axis. In other words, the substrate edge extending parallel to the y-axis is the perforated edge formed by the series of holes 308. The substrate edge extending parallel to the y-axis (which also corresponds to the package edge extending parallel to the y-axis) can each be very close (e.g., less than 100 μm) to the die edge of the die mounted to the device region 302 of the circuit substrate assembly strip 300.

[0043] As a result of the series of holes 308 formed along the first singulation path 304, the weak zone of the circuit substrate assembly strip 300 is offset away from the die edge to the substrate edge defined by the first singulation path 304 including the series of holes 308. During singulation, a cut through the series of holes 308 is performed, substantially cutting the series of holes 308 in half along the first singulation path 304. Thus, adjacent device regions 302, when separated, will each include a portion of the series of holes 308 that was previously shared along a boundary line (e.g., along a singulation path).

[0044] For example, the device area 302-1 includes the first remaining portion of the series of holes 308-2 and the device area 302-2 includes the second remaining portion of the series of holes 308-2. The first remaining portion of the series of holes 308-2 has a first shape that can be defined by a first circular segment and the second remaining portion of the series of holes 308-2 has a second shape that can be defined by a second circular segment. As defined herein, a circular segment is a shape defined by an arc and a chord of a circle. In other words, a circular segment has a perimeter bounded by an arc and a chord of a circle. A semicircle is an example of a circular segment. In some implementations, the first remaining portion and the second remaining portion may be referred to as a half hole. In some implementations, the first remaining portion and the second remaining portion may be referred to as a toothed hole. In some implementations, the substrate edge that includes the remaining portion of one of the series of holes 308 may be referred to as a circular segmented edge, wherein each hole of the series of holes 308 defines a corresponding concave segment of the substrate edge.

[0045] The first shape defined by the first circular segment and the second shape defined by the first circular segment may both be substantially semicircular, or the first shape defined by the first circular segment may be equal to or greater than a semicircular and the second shape defined by the second circular segment may be less than a semicircular, or the first shape defined by the first circular segment may be less than a semicircular and the second shape defined by the second circular segment may be equal to or greater than a semicircular, or the first shape defined by the first circular segment may be less than a semicircular and the second shape defined by the second circular segment may be less than a semicircular. The first shape and the second shape may depend on the alignment of an actual singulation path made through the series of holes 308-2 (e.g., the actual position of the saw blade) relative to the central axis of the series of holes 308-2. For example, the actual singulation path may vary according to typical manufacturing tolerances, such that the actual singulation path may be aligned with the central axis of the series of holes 308-2 or may deviate from the central axis of the series of holes 308-2 according to typical manufacturing tolerances.

[0046] The series of holes 308 facilitates cutting (e.g., sawing) because the circuit substrate assembly strip 300 has been weakened by the series of holes 308 extending along the first singulation path 304. Thus, the series of holes 308 reduces the amount of vibration transmitted to the circuit substrate assembly strip 300 where the die edges are located, which reduces or prevents the occurrence of substrate cracks forming at the die edges. The size, density, and / or spacing of the holes 308 can be optimized to remove even the slightest vibration felt at the die edges of the die when undergoing the cutting or sawing process. Additionally, the surface within each hole 308 can be created to have one or more different physical properties (e.g., roughness, etc.) than the surface of the substrate edge formed due to cutting or sawing along the singulation path. For example, creation (e.g., drilling) of a series of holes 308 and sawing along the corresponding first singulation path 304 may be performed during separate process steps, and thus the surface of the circuit substrate assembly strip 300 within each hole 308 may have one or more different physical properties (e.g., roughness, etc.) than the surface of the circuit substrate assembly strip 300 formed by sawing along the corresponding first singulation path 304.

[0047] It will be further appreciated that in some implementations, the series of holes 308 can be formed along the second singulation path 306 in addition to or as an alternative to the series of holes 308 formed along the first singulation path 304. The placement of the series of holes 308 can depend on the device configuration of the semiconductor device assembly and the placement of the dies in each device area 302, wherein, for example, the series of holes 308 are formed when the die edges are very close to the first singulation path 304 and / or the second singulation path 306 used to form the substrate edge and the package edge of the semiconductor device assembly.

[0048] The circuit substrate assembly strip 300 may further include interconnect pads 310 (such as bond fingers or another type of bond pad or contact pad) for providing electrical connection to device components placed on the device region 302 .

[0049] As indicated above, provide Figure 3A As an example. Other examples may differ from the Figure 3A Described example.

[0050] Figure 3B A top view 312 and a perspective view 314 illustrate an example substrate edge along which a series of holes 308 are formed according to one or more implementations. Figure 3A As described above, the substrate edge also corresponds to the package edge of the semiconductor device assembly. The package edge is the outer boundary of the semiconductor device assembly. Therefore, the substrate edge is part of the package edge (eg, part of the outer boundary of the semiconductor device assembly).

[0051] The device region 302 is formed by singulation (eg, sawing) applied along the singulation paths of the device region 302. Figure 3B . The substrate edge includes the remainder of the series of holes 308 (e.g., a concave segment or a circular segment). Therefore, the substrate edge can be referred to as a circular segmented edge. Therefore, the substrate edge includes a series of concave segments or circular segments provided along the length of the substrate edge. In other words, the substrate edge is perforated by the remainder of the series of holes 308.

[0052] As above combined Figure 3A As depicted, the remainder of the series of holes 308 has a shape that may be defined by a segment of a circle. A segment of a circle has a perimeter bounded by an arc of a circle (eg, a concave edge) and a chord (eg, a straight edge of the substrate edge).

[0053] As indicated above, provide Figure 3B As an example. Other examples may differ from the Figure 3B Described example.

[0054] Figure 4 A front view of an example semiconductor device assembly 400 that can be manufactured using the techniques described herein according to one or more implementations is illustrated. The semiconductor device assembly 400 is a semiconductor device assembly 400 that is fabricated using the techniques described herein in accordance with one or more implementations. Figure 1 An example of the apparatus 100 is described. In some implementations, the semiconductor device assembly 400 can be a semiconductor packaging assembly.

[0055] The semiconductor device assembly 400 may include any type of device or system including one or more integrated circuits 405. For example, the semiconductor device assembly 400 may include a memory device, a flash memory device, a NAND memory device, a NOR memory device, a RAM device, a ROM device, a DRAM device, an SRAM device, an SSD, a microchip, and / or a SoC device, among other examples. In some cases, the semiconductor device assembly 400 may be referred to as a semiconductor package, a semiconductor chip package, an assembly, or an integrated assembly. In some cases, the semiconductor device assembly 400 may be a memory device including at least one memory die.

[0056] like Figure 4, the semiconductor device assembly 400 may include one or more integrated circuits 405 disposed on a circuit substrate 410 (e.g., a PCB), which are shown as a first integrated circuit 405-1 and a second integrated circuit 405-2. The integrated circuits 405 may be mounted on or otherwise disposed on a first substrate surface 415 of the circuit substrate 410. In some implementations, the first integrated circuit 405-1 may be a control device, such as a controller or a power management IC. Although the semiconductor device assembly 400 is shown as including two integrated circuits 405 as an example, the semiconductor device assembly 400 may include a different number of integrated circuits 405.

[0057] In some implementations, the integrated circuit 405 may be a single die. For example, the first integrated circuit 405-1 may be a single die. In some implementations, the integrated circuit 405 may include a plurality of semiconductor dies 420, which are shown as five semiconductor dies 420-1 to 420-5. In some implementations, the dies 420-1 to 420-5 may be memory devices (e.g., flash memory dies), and the first integrated circuit 405-1 may be a memory controller configured to perform read / write operations with the dies 420-1 to 420-5. However, it will be appreciated that the dies 420-1 to 420-5 may be any type of device, including those mentioned above.

[0058] The semiconductor device assembly 400 may include a housing 425 (e.g., a packaging housing) that protects internal components of the semiconductor device assembly 400 (e.g., the integrated circuit 405) from damage and environmental elements (e.g., particles) that may cause the semiconductor device assembly 400 to malfunction. The housing 425 is disposed over the first substrate surface 415 to encapsulate the integrated circuit 405. The housing 425 may also partially or completely encapsulate the first substrate surface 415. Depending on the functional requirements of the semiconductor device assembly 400, the housing 425 may be a packaging molding, a molding compound, a plastic (e.g., an epoxy plastic), a ceramic, or another type of material.

[0059] The circuit substrate 410 may include internal conductive structures (e.g., redistribution layers) embedded therein and electrical contacts 430 arranged at a second substrate surface 435 of the circuit substrate 410. The internal conductive structures may be connected to the electrical contacts 430 to electrically connect to an external device. The semiconductor device assembly 400 may further include solder balls 440, or another type of connector, electrically connected to the electrical contacts 430. The solder balls 440 may be used to mount the semiconductor device assembly 400 to, for example, a carrier substrate or an external device.

[0060] The first integrated circuit 405-1 has a die edge 445 disposed proximate to a first package edge 450 of the semiconductor device assembly 400. The first package edge 450 is formed by a first substrate edge 455 positioned at a first side of the circuit substrate 410 and a first housing edge 460 positioned at a first side of the housing 425. The first substrate edge 455 extends along the z-axis between the first substrate surface 415 and the second substrate surface 435. In some implementations, the first substrate edge 455 coincides with the first housing edge 460, such as Figure 4 As shown in .

[0061] Prior to singulation, a first package edge 450 is arranged along a first singulation path. The first package edge 450 is formed by cutting through the housing 425 and the circuit substrate 410 along the first singulation path (for example, by sawing). The first substrate edge 455 includes a first series of holes 465 arranged along the first substrate edge 455. Each hole 465 extends at least partially from the first substrate surface 415 toward the second substrate surface 435. Each hole 465 is a remainder of a series of holes, such as the series of holes 308 formed in a circuit substrate assembly strip, such as the circuit substrate assembly strip 300. The first series of holes 465 can be blind holes or through holes, each having a circular segment shape.

[0062] The size, density, and / or spacing of the holes 308 may be optimized to remove even the slightest vibrations felt at the die edge 445 while undergoing the singulation process. Additionally, the surface within each hole 465 may be produced to have one or more different physical properties (e.g., roughness, etc.) than the surface of the first substrate edge 455 formed as a result of singulation performed along the first singulation path. For example, the roughness of the surface of the first substrate edge 455 produced by sawing may be different than the roughness of the surface within each hole 465 produced by drilling used to produce the holes 308. For example, the creation (e.g., drilling) of the series of holes 308 formed along the first singulation path and the sawing along the first singulation path may be performed during separate process steps, and thus the surface of the circuit substrate 410 within each hole 308 may have one or more different physical properties (e.g., roughness, etc.) than the surface of the first substrate edge 455 formed by sawing along the first singulation path.

[0063] Furthermore, the housing 425 extends into each of the first series of holes 465, thereby filling each of the first series of holes 465. For example, the housing material used to form the housing 425 may be applied to the first substrate surface 415 prior to singulation. Thus, the housing material is not only disposed onto the first substrate surface 415 and over the integrated circuits 405, but the housing material is also disposed within the series of holes (e.g., series of holes 308) formed in the circuit substrate assembly strip. A portion of the housing material disposed within the series of holes remains within the first series of holes 465 after singulation as part of the housing 425 and more specifically as part of the first package edge 450. Thus, the housing 425 is mechanically interlocked with the first substrate edge 455. This may provide additional structural support and protection to the circuit substrate 410 at the first substrate edge 455 (e.g., at the first package edge 450).

[0064] The die 420-1 has a die edge 470 disposed proximate to a second package edge 475 of the semiconductor device assembly 400. The second package edge 475 is formed by a second substrate edge 480 positioned at a second side of the circuit substrate 410 and a second housing edge 485 positioned at a second side of the housing 425. The second substrate edge 480 extends along the z-axis between the first substrate surface 415 and the second substrate surface 435. In some implementations, the second substrate edge 480 coincides with the second housing edge 485, such as Figure 4 As shown in .

[0065] Prior to singulation, a second package edge 475 is arranged along a second singulation path. The second package edge 475 is formed by cutting through the housing 425 and the circuit substrate 410 along the second singulation path (for example, by sawing). The second substrate edge 480 includes a second series of holes 490 arranged along the second substrate edge 480. Each hole 490 extends at least partially from the first substrate surface 415 toward the second substrate surface 435. Each hole 490 is a remainder of a series of holes, such as a series of holes 308 formed in a circuit substrate assembly strip, such as the circuit substrate assembly strip 300. The second series of holes 490 may be blind holes or through holes, each having a circular segment shape.

[0066] The size, density, and / or spacing of the holes 308 may be optimized to remove even the slightest vibrations felt at the die edge 470 while undergoing the singulation process. Additionally, the surface within each hole 490 may be created to have one or more different physical properties (e.g., roughness, etc.) than the surface of the second substrate edge 480 formed as a result of singulation performed along the second singulation path. For example, the roughness of the surface of the second substrate edge 480 created by sawing may be different than the roughness of the surface within each hole 490 created by drilling used to create the holes 308. For example, the creation (e.g., drilling) of the series of holes 308 formed along the second singulation path and the sawing along the second singulation path may be performed during separate process steps, and thus the surface of the circuit substrate 410 within each hole 308 may have one or more different physical properties (e.g., roughness, etc.) than the surface of the second substrate edge 480 formed by sawing along the second singulation path.

[0067] Furthermore, the housing 425 extends into each of the second series of holes 490, thereby filling each of the second series of holes 490. For example, the housing material used to form the housing 425 may be applied to the first substrate surface 415 prior to singulation. Thus, the housing material is not only disposed onto the first substrate surface 415 and over the integrated circuits 405, but the housing material is also disposed within the series of holes (e.g., series of holes 308) formed in the circuit substrate assembly strip. A portion of the housing material disposed within the series of holes remains within the second series of holes 490 after singulation as part of the housing 425 and more specifically as part of the second package edge 475. Thus, the housing 425 is mechanically interlocked with the second substrate edge 480. This may provide additional structural support and protection to the circuit substrate 410 at the second substrate edge 480 (e.g., at the second package edge 475).

[0068] As indicated above, provide Figure 4 As an example. Other examples may differ from the Figure 4 Describe the example. Provide Figure 4 The number and arrangement of components shown in FIG. are examples. In fact, compared to Figure 4 There may be additional components, fewer components, different components, or differently arranged components than those shown in FIG.

[0069] Figure 5A A front view illustrating an example semiconductor device assembly 500 that can be fabricated using the techniques described herein, according to one or more implementations. In some implementations, the semiconductor device assembly 500 can be a semiconductor packaging assembly.

[0070] Figure 5B A top view of a semiconductor device assembly 500 is illustrated in accordance with one or more implementations.

[0071] Figure 5C A side view of a semiconductor device assembly 500 is illustrated in accordance with one or more implementations.

[0072] The semiconductor device assembly 500 is a combination of the above Figure 1 1. An example of the apparatus 100 described herein. The semiconductor device assembly 500 may be considered a more compact version of the semiconductor device assembly 400. For example, the semiconductor device assembly 500 may include at least one die including a first die edge that is laterally arranged 100 μm or less from a first substrate edge and a second die edge that is arranged opposite the first die edge and laterally arranged 100 μm or less from a second substrate edge. Thus, the die may have two die edges that are very close to one of the substrate edges. In some embodiments, the first die edge and / or the second die edge may be arranged more than 100 μm from the first substrate edge and the second substrate edge, respectively, and still be considered very close to the substrate edge.

[0073] The semiconductor device assembly 500 may include any type of device or system including one or more integrated circuits 505. For example, the semiconductor device assembly 500 may include a memory device, a flash memory device, a NAND memory device, a NOR memory device, a RAM device, a ROM device, a DRAM device, an SRAM device, an SSD, a microchip, and / or a SoC device, among other examples. In some cases, the semiconductor device assembly 500 may be referred to as a semiconductor package, a semiconductor chip package, an assembly, or an integrated assembly. In some cases, the semiconductor device assembly 500 may be a memory device including at least one memory die.

[0074] like Figure 5A and 5B , a semiconductor device assembly 500 may include one or more integrated circuits 505 disposed on a circuit substrate 510 (eg, a PCB), which is shown as Figure 5B The first integrated circuit 505-1 and Figure 5A and 5B 500. The integrated circuit 505 may be mounted on or otherwise disposed on a first substrate surface 515 of the circuit substrate 510. In some implementations, the first integrated circuit 505-1 may be a control device, such as a controller or a power management IC. Although the semiconductor device assembly 500 is shown as including two integrated circuits 505 as an example, the semiconductor device assembly 500 may include a different number of integrated circuits 505.

[0075] In some implementations, the integrated circuit 505 may be a single die. For example, the first integrated circuit 505-1 may be a single die. In some implementations, the integrated circuit 505 may include a plurality of semiconductor dies 520, which are shown as five semiconductor dies 520-1 to 520-5. In some implementations, the dies 520-1 to 520-5 may be memory devices (e.g., flash memory dies), and the first integrated circuit 505-1 may be a memory controller configured to perform read / write operations with the dies 520-1 to 520-5. However, it will be appreciated that the dies 520-1 to 520-5 may be any type of device, including those mentioned above.

[0076] The semiconductor device assembly 500 may include a housing 525 (e.g., a packaging housing) that protects internal components of the semiconductor device assembly 500 (e.g., the integrated circuit 505) from damage and environmental elements (e.g., particles) that may cause the semiconductor device assembly 500 to malfunction. The housing 525 is disposed over the first substrate surface 515 to encapsulate the integrated circuit 505. The housing 525 may also partially or completely encapsulate the first substrate surface 515. Depending on the functional requirements of the semiconductor device assembly 500, the housing 525 may be a packaging molding, a molding compound, a plastic (e.g., an epoxy plastic), a ceramic, or another type of material.

[0077] The circuit substrate 510 may include internal conductive structures (e.g., redistribution layers) embedded therein and electrical contacts 530 arranged at a second substrate surface 535 of the circuit substrate 510. The internal conductive structures may be connected to the electrical contacts 530 to electrically connect to an external device. The semiconductor device assembly 500 may further include solder balls 540, or another type of connector, electrically connected to the electrical contacts 530. The solder balls 540 may be used to mount the semiconductor device assembly 500 to, for example, a carrier substrate or an external device.

[0078] The die 520-1 can have a first die edge 545 disposed proximate to a first package edge 550 of the semiconductor device assembly 500. The first package edge 550 can be formed by a first substrate edge 555 positioned at a first side of the circuit substrate 510 and a first housing edge 560 positioned at a first side of the housing 525. The first substrate edge 555 can extend along the z-axis between the first substrate surface 515 and the second substrate surface 535. In some implementations, the first substrate edge 555 can coincide with the first housing edge 560, such as Figure 5A As shown in .

[0079] Prior to singulation, a first package edge 550 is arranged along a first singulation path. The first package edge 550 may be formed by cutting through the housing 525 and the circuit substrate 510 along the first singulation path (e.g., by sawing). The first substrate edge 555 may include a first series of holes 565 arranged along the first substrate edge 555. Each hole 565 extends at least partially from the first substrate surface 515 toward the second substrate surface 535. Each hole 565 is a remainder of a series of holes, such as the series of holes 308 formed in a circuit substrate assembly strip, such as the circuit substrate assembly strip 300. The first series of holes 565 may be blind holes or through holes, each having a circular segment shape.

[0080] Furthermore, the housing 525 may extend into each of the first series of holes 565, thereby filling each of the first series of holes 565. For example, the housing material used to form the housing 525 may be applied to the first substrate surface 515 prior to singulation. Thus, the housing material is not only disposed onto the first substrate surface 515 and over the integrated circuits 505, but the housing material is also disposed within the series of holes (e.g., series of holes 308) formed in the circuit substrate assembly strip. A portion of the housing material disposed within the series of holes remains within the first series of holes 565 after singulation as part of the housing 525 and more specifically as part of the first package edge 550. Thus, the housing 525 may be mechanically interlocked with the first substrate edge 555. This may provide additional structural support and protection to the circuit substrate 510 at the first substrate edge 555 (e.g., at the first package edge 550).

[0081] The die 520-1 can have a second die edge 570 disposed proximate to a second package edge 575 of the semiconductor device assembly 500. The second package edge 575 can be formed by a second substrate edge 580 positioned at a second side of the circuit substrate 510 and a second housing edge 585 positioned at a second side of the housing 525. The second substrate edge 580 can extend along the z-axis between the first substrate surface 515 and the second substrate surface 535. In some implementations, the second substrate edge 580 can coincide with the second housing edge 585, such as Figure 5A As shown in .

[0082] Prior to singulation, a second package edge 575 is arranged along a second singulation path. The second package edge 575 may be formed by cutting through the housing 525 and the circuit substrate 510 along the second singulation path (e.g., by sawing). The second substrate edge 580 may include a second series of holes 590 arranged along the second substrate edge 580. Each hole 590 extends at least partially from the first substrate surface 515 toward the second substrate surface 535. Each hole 590 is a remainder of a series of holes, such as the series of holes 308 formed in a circuit substrate assembly strip, such as the circuit substrate assembly strip 300. The second series of holes 590 may be blind holes or through holes, each having a circular segment shape.

[0083] Furthermore, the housing 525 may extend into each of the second series of holes 590, thereby filling each of the second series of holes 590. For example, the housing material used to form the housing 525 may be applied to the first substrate surface 515 prior to singulation. Thus, not only is the housing material disposed onto the first substrate surface 515 and over the integrated circuits 505, but the housing material is also disposed within the series of holes (e.g., series of holes 308) formed in the circuit substrate assembly strip. A portion of the housing material disposed within the series of holes remains within the second series of holes 590 after singulation as part of the housing 525 and more specifically as part of the second package edge 575. Thus, the housing 525 is mechanically interlocked with the second substrate edge 580. This may provide additional structural support and protection to the circuit substrate 510 at the second substrate edge 580 (e.g., at the second package edge 575).

[0084] Figure 5B The top view of the semiconductor device assembly 500 shown in FIG. 5 shows a first series of holes 565 arranged along a first substrate edge 555 and a second series of holes 590 arranged along a second substrate edge 580. Figure 5B , an enlarged portion of the second substrate edge 580 is shown. As illustrated in this enlarged portion of the second substrate edge 580, each hole of the second series of holes 590 defines a respective concave segment of the second substrate edge 580. Similarly, each hole of the first series of holes 565 defines a respective concave segment of the first substrate edge 555.

[0085] Figure 5C 5 shows a second package edge 575 of the semiconductor device assembly 500. The housing 525 fills each of the second series of holes 590 and mechanically interlocks with the second substrate edge 580. Filling the holes 590 with the housing material of the housing 525 can provide additional structural support and protection to the circuit substrate 510 at the second substrate edge 580 (e.g., at the second package edge 575).

[0086] In this example, the second series of holes 590 are blind holes. In other words, the second series of holes 590 extend partially (e.g., not completely) from the first substrate surface 515 to the second substrate surface 535. Thus, the bottom of each hole 590 is defined by the circuit substrate 510 remaining after forming the second series of holes 590. In this example, the housing 525 is in direct contact with the circuit substrate 510 at the bottom of each hole 590. The use of blind holes can increase the amount of surface area of ​​the housing 525 and the circuit substrate 510 that are in contact with each other, which can result in better bonding contact and / or higher bonding strength between the housing 525 and the circuit substrate 510 and improved structural integrity of the semiconductor device assembly 500 (e.g., package).

[0087] In some implementations, using through holes for a series of holes (e.g., holes 565 and 590) can allow the housing material of the housing 525 to pass through the circuit substrate 510 and form over a portion of the second substrate surface 535. Thus, the housing 525 can be bonded to the second substrate surface 535 to improve the bond between the housing 525 and the circuit substrate 510 and improve the structural integrity of the semiconductor device assembly 500 (e.g., a package).

[0088] The circuit substrate 510 may include a solder mask formed on the first substrate surface 515 to cover the first substrate surface 515. The solder mask provides protection to the conductive traces of the circuit substrate 510 formed at the first substrate surface 515 and prevents solder bridges from forming between closely spaced contact pads. However, the solder mask may reduce the bonding strength of the housing 525 to the circuit substrate 510.

[0089] Thus, in some implementations, the solder mask can be removed from edge regions of the first substrate surface 515 at the first substrate edge 555 and the second substrate surface 580, exposing the first substrate surface 515. In the absence of solder mask at these edge regions, the housing 525 can be in direct contact with the first substrate surface 515 (e.g., to a prepreg layer or core layer of the circuit substrate 510), which can allow for better bonding of the housing 525 to the circuit substrate.

[0090] As indicated above, provide Figures 5A to 5C As an example. Other examples may differ from the Figures 5A to 5C Describe the example. Provide Figures 5A to 5C The number and arrangement of components shown in FIG. are examples. In fact, compared to Figures 5A to 5C There may be additional components, fewer components, different components, or differently arranged components than those shown in FIG.

[0091] Figures 6A to 6G The process flow of an example method 600 for forming one or more semiconductor device assemblies is described. In some implementations, the method may be performed by various semiconductor manufacturing equipment. Figures 6A to 6G One or more process operations.

[0092] like Fig. 6A , method 600 may include process 605, including fabricating a circuit substrate assembly strip having a plurality of device regions, and forming a plurality of series of holes along singulation paths for singulating the plurality of device regions. Thus, each device region may be delineated by a series of holes arranged along a respective singulation path, wherein each hole in the series of holes extends at least partially through the circuit substrate assembly strip. In some cases, adjacent device regions share a series of holes at a common boundary (e.g., at a common or shared singulation path). In some implementations, an interconnect pad may also be formed in each device region.

[0093] like Figure 6B , method 600 may include a die attach process 610, including attaching at least one die to each device region of the circuit substrate assembly strip. In some implementations, one or more passive components may also be attached to each device region of the circuit substrate assembly strip.

[0094] like Figure 6C As shown in , method 600 may include a wire bonding process 615 including forming wire bonds between the die and the interconnect pads in each device region.

[0095] like Fig.6D , method 600 may include an encapsulation process 620 including depositing a housing material on a top surface of the circuit substrate assembly strip. Depositing the housing material may include depositing the housing material over the die in each of the device regions and over each of the singulation paths so as to encapsulate the die in each of the device regions and to encapsulate each of the circulation paths. Depositing the housing material includes filling each of the series of holes with the housing material. The housing material may then be cured to form a housing (e.g., a package housing).

[0096] like Fig. 6E As shown in , method 600 may include a ball attach process 625 including attaching solder balls to a bottom surface of the circuit substrate assembly strip.

[0097] like Fig. 6F , method 600 may include a singulation process 630, including cutting through (e.g., sawing through) the housing material and circuit substrate assembly strip along each of the singulation paths to separate each of the device regions from each other to form a semiconductor device assembly corresponding to each device region. The singulation operation forms a package edge for each of the semiconductor package assemblies. The housing material deposited in the series of holes forms a portion of the package edge for the respective semiconductor package assembly.

[0098] like Figure 6GAs shown in , a separate semiconductor device assembly is created for each device region of the circuit substrate assembly strip. The casing material is mechanically interlocked with the circuit substrate of each semiconductor device assembly along the substrate edge that coincides with the package edge.

[0099] The method 600 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods described elsewhere herein.

[0100] Although FIG6 shows example blocks of method 600, in some implementations, method 600 may include additional processes, fewer processes, different processes, or differently arranged processes than those depicted in FIG6. In some implementations, method 600 may include forming structures of circuit substrate assembly strips and / or structures of semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500), integrated assemblies including semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500), and electronic system assemblies including semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500), any portions of circuit substrate assembly strips and / or structures of semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500) described herein, and / or any portions of integrated assemblies including semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500) described herein. For example, method 600 may include forming one or more of circuit substrate assembly strip 300 , semiconductor device assembly 400 , or portions of semiconductor device assembly 500 .

[0101] Figure 7 FIG. 7 is a flow chart of an example method 700 of forming an integrated assembly or memory device having a semiconductor package assembly with a rounded segmented package edge. In some implementations, the method may be performed by various semiconductor manufacturing equipment. Figure 7 One or more process boxes.

[0102] like Figure 7 As shown in FIG. 7 , method 700 may include attaching at least one die to a circuit substrate, the circuit substrate comprising a first substrate surface on which the at least one die is arranged, a second substrate surface arranged opposite to the first substrate surface, and a series of holes arranged along a first sawing path, wherein each hole in the series of holes extends at least partially from the first substrate surface toward the second substrate surface (box 710).

[0103] like Figure 7As further shown in FIG. 7 , method 700 may include depositing a casing material on a first substrate surface (including on a first sawing path) to encapsulate at least one die, wherein depositing the casing material includes filling the series of holes with the casing material (block 720 ).

[0104] like Figure 7 As further shown in FIG. 7 , the method 700 may include sawing through the casing material and the circuit substrate along a first sawing path to form a package edge of the semiconductor package assembly, wherein the casing material deposited in the series of holes forms a portion of the package edge (block 730 ).

[0105] The method 700 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods described elsewhere herein.

[0106] In a first aspect, the method 700 includes sawing through the housing material and the circuit substrate along a first sawing path to form a substrate edge of the circuit substrate as part of a package edge, and the housing material is mechanically interlocked with the circuit substrate along the substrate edge.

[0107] In a second aspect (alone or in combination with the first aspect), a substrate edge of the semiconductor package assembly includes a remaining portion of each hole in the series of holes, and the remaining portion of each hole in the series of holes has a perimeter defined by a circular segment.

[0108] In a third aspect (alone or in combination with one or more of the first and second aspects), each hole portion of the series of holes extends from the first substrate surface to the second substrate surface.

[0109] In a fourth aspect (combined with the third aspect), the bottom of each hole in the series of holes is defined by a circuit substrate, and the housing material is in direct contact with the circuit substrate along the bottom of each hole in the series of holes.

[0110] In a fifth aspect (alone or in combination with one or more of the first to second aspects), each hole in the series of holes extends completely from the first substrate surface to the second substrate surface.

[0111] although Figure 7 Example blocks of method 700 are shown, but in some embodiments, compared to Figure 7, method 700 may include additional boxes, fewer boxes, different boxes, or differently arranged boxes. In some implementations, method 700 may include forming structures of circuit substrate assembly strips and / or structures of semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500), integrated assemblies including semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500), and electronic system assemblies including semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500), any portions of circuit substrate assembly strips and / or structures of semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500) described herein, and / or any portions of integrated assemblies including semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500) described herein. For example, method 700 may include forming one or more of portions of circuit substrate assembly strip 300, semiconductor device assembly 400, or semiconductor device assembly 500, including but not limited to portions 308, 425, 450, 455, 460, 465, 475, 480, 485, 490, 550, 555, 560, 565, 575, 580, 585, and 590.

[0112] Figure 8 FIG. 8 is a flow chart of an example method 800 of forming an integrated assembly or memory device having a semiconductor package assembly with a rounded segmented package edge. In some implementations, the method may be performed by various semiconductor manufacturing equipment. Figure 8 One or more process boxes.

[0113] like Figure 8 As shown in , method 800 may include attaching at least one first die to a first device region of a circuit substrate (block 810).

[0114] like Figure 8 As further shown in, method 800 may include attaching at least one second die to a second device area of ​​a circuit substrate, wherein the circuit substrate includes a first substrate surface on which at least one first die and the at least one second die are arranged, and a second substrate surface arranged opposite to the first substrate surface, wherein the first device area and the second device area are defined by a series of holes arranged along a first singulation path, and wherein each hole in the series of holes extends at least partially from the first substrate surface toward the second substrate surface (box 820).

[0115] like Figure 8As further shown in, method 800 may include depositing a casing material on a first substrate surface, including depositing the casing material over at least one first die, at least one second die, and a first singulation path to encapsulate the at least one first die, the at least one second die, and the first singulation path, wherein depositing the casing material includes filling the series of holes with the casing material (box 830).

[0116] like Figure 8 8. Further shown in FIG. 8, method 800 may include cutting through the casing material and the circuit substrate along a first singulation path to separate a first device area and a second device area to form a first packaging edge of a first semiconductor package assembly corresponding to the first device area and to form a second packaging edge of a second semiconductor package assembly corresponding to the second device area, wherein the casing material deposited in the series of holes forms a portion of the first packaging edge and the second packaging edge (frame 840).

[0117] Method 800 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods described elsewhere herein.

[0118] In a first aspect, method 800 includes cutting through a housing material and a circuit substrate along a first singulation path to form a first substrate edge of the circuit substrate as part of a first packaging edge and to form a second substrate edge of the circuit substrate as part of a second packaging edge, the housing material being mechanically interlocked with the circuit substrate of a first semiconductor packaging assembly along the first substrate edge, and the housing material being mechanically interlocked with the circuit substrate of the second semiconductor packaging assembly along the second substrate edge.

[0119] In a second aspect (alone or in combination with the first aspect), a first substrate edge of a first semiconductor package assembly includes a first remaining portion of each hole in the series of holes, and the first remaining portion of each hole in the series of holes has a first shape defined by a first circular segment, and a second substrate edge of a second semiconductor package assembly includes a second remaining portion of each hole in the series of holes, and the second remaining portion of each hole in the series of holes has a second shape defined by a second circular segment.

[0120] In a third aspect (alone or in combination with one or more of the first and second aspects), the series of holes is a first series of holes, wherein a first device area is further defined by a second series of holes arranged along a second singulation path, wherein each hole in the second series of holes extends at least partially from the first substrate surface toward the second substrate surface, wherein a second device area is further defined by a third series of holes arranged along a third singulation path, wherein each hole in the third series of holes extends at least partially from the first substrate surface toward the second substrate surface, wherein depositing a shell material on the first substrate surface further includes depositing the shell material over the second singulation path and the third singulation path to encapsulate the second singulation path. The method 800 further comprises cutting through the housing material and the circuit substrate along the second singulation path to form a third packaging edge of the first semiconductor package assembly, wherein the housing material deposited in the second series of holes forms a portion of the third packaging edge, and cutting through the housing material and the circuit substrate along the third singulation path to form a fourth packaging edge of the second semiconductor package assembly, wherein the housing material deposited in the third series of holes forms a portion of the fourth packaging edge.

[0121] In a fourth aspect (alone or in combination with one or more of the first to third aspects), the first singulation path, the second singulation path, and the third singulation path extend parallel to each other.

[0122] although Figure 8 Example blocks of method 800 are shown, but in some embodiments, compared to Figure 8, method 800 may include additional boxes, fewer boxes, different boxes, or differently arranged boxes. In some implementations, method 800 may include forming structures of circuit substrate assembly strips and / or structures of semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500), integrated assemblies including semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500), and electronic system assemblies including semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500), any portions of circuit substrate assembly strips and / or structures of semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500) described herein, and / or any portions of integrated assemblies including semiconductor device assemblies (e.g., semiconductor device assemblies 400 or 500) described herein. For example, method 800 may include forming one or more of portions of circuit substrate assembly strip 300, semiconductor device assembly 400, or semiconductor device assembly 500, including but not limited to portions 308, 425, 450, 455, 460, 465, 475, 480, 485, 490, 550, 555, 560, 565, 575, 580, 585, and 590.

[0123] The following provides an overview of some aspects of the disclosure:

[0124] Aspect 1: A semiconductor device assembly, comprising: a circuit substrate, comprising: a first substrate surface; a second substrate surface, arranged opposite to the first substrate surface; a first substrate edge, extending from the first substrate surface to the second substrate surface; and a second substrate edge, extending from the first substrate surface to the second substrate surface and arranged opposite to the first substrate edge; a series of holes arranged along the first substrate edge of the circuit substrate, wherein each hole in the series of holes extends at least partially from the first substrate surface toward the second substrate surface; at least one die, arranged on the first substrate surface; and a packaging shell disposed above the first substrate surface, wherein the packaging shell encapsulates the at least one die and the first substrate surface, and wherein the packaging shell fills each hole in the series of holes.

[0125] Aspect 2: The semiconductor device assembly of aspect 1, wherein the encapsulating housing is mechanically interlocked with the first substrate edge.

[0126] Aspect 3: The semiconductor device assembly of any of aspects 1-2, wherein the first substrate edge is a perforated edge formed by the series of holes.

[0127] Aspect 4: The semiconductor device assembly of any of aspects 1-3, wherein each hole in the series of holes defines a respective concave segment of the first substrate edge.

[0128] Aspect 5: The semiconductor device assembly of any of aspects 1-4, wherein each hole in the series of holes has a perimeter having a generally semicircular shape.

[0129] Aspect 6: The semiconductor device assembly of any of aspects 1 to 5, wherein each hole in the series of holes extends partially from the first substrate surface to the second substrate surface.

[0130] Aspect 7: The semiconductor device assembly of aspect 6, wherein: a bottom of each hole in the series of holes is defined by the circuit substrate, and the encapsulating housing is in direct contact with the circuit substrate at the bottom of each hole in the series of holes.

[0131] Aspect 8: The semiconductor device assembly of any of aspects 1 to 7, wherein each hole in the series of holes extends completely from the first substrate surface to the second substrate surface.

[0132] Aspect 9: A semiconductor device assembly according to any one of Aspects 1 to 8, wherein: the circuit substrate includes a solder mask formed on the first substrate surface to cover the first substrate surface, wherein the first substrate surface is exposed at an edge of the first substrate, wherein the solder mask is absent from the first substrate edge, and the packaging shell is in direct contact with the first substrate surface at the first substrate edge.

[0133] Aspect 10: The semiconductor device assembly of aspect 9, wherein the first substrate surface is a prepreg layer or a core layer.

[0134] Aspect 11: The semiconductor device assembly of any of Aspects 1 to 10, wherein: the series of holes is a first series of holes, and the semiconductor device assembly further comprises: a second series of holes arranged along the second substrate edge of the circuit substrate, wherein each hole in the second series of holes at least partially extends from the first substrate surface toward the second substrate surface, wherein the encapsulation shell fills the second series of holes. A second series of holes arranged along the second substrate edge of the circuit substrate, wherein each hole in the second series of holes at least partially extends from the first substrate surface toward the second substrate surface, wherein the encapsulation shell fills the second series of holes.

[0135] Aspect 12: The semiconductor device assembly of aspect 11, wherein the encapsulating housing is mechanically interlocked with the first substrate edge and the second substrate edge.

[0136] Aspect 13: The semiconductor device assembly of aspect 11, wherein the first substrate edge is a first perforated edge formed with the first series of holes, and the second substrate edge is a second perforated edge formed with the second series of holes.

[0137] Aspect 14: The semiconductor device assembly of aspect 11, wherein each hole in the first series of holes and each hole in the second series of holes has a perimeter bounded by an arc and a chord of a circle.

[0138] Aspect 15: The semiconductor device assembly of aspect 11, wherein the first substrate edge corresponds to a first sawing path and the second substrate edge corresponds to a second sawing path.

[0139] Aspect 16: The semiconductor device assembly of any of aspects 1 to 15, wherein the at least one die comprises a plurality of dies arranged in a stacked configuration, wherein the at least one die comprises a die edge laterally arranged 100 microns or less from an edge of the first substrate.

[0140] Aspect 17: The semiconductor device assembly of aspect 16, wherein the plurality of dies are flash memory dies.

[0141] Aspect 18: A memory device, comprising: a circuit substrate, comprising: a first substrate surface; a second substrate surface, arranged opposite to the first substrate surface; a first substrate edge, extending from the first substrate surface to the second substrate surface; and a second substrate edge, extending from the first substrate surface to the second substrate surface and arranged opposite to the first substrate edge, wherein a first series of holes are arranged along the first substrate edge of the circuit substrate to form a first perforated edge, wherein each hole in the first series of holes at least partially extends from the first substrate surface toward the second substrate surface, wherein a second series of holes are arranged along the second substrate edge of the circuit substrate to form a second perforated edge, wherein each hole in the second series of holes at least partially extends from the first substrate surface toward the second substrate surface; at least one memory die, arranged on the first substrate surface; and a packaging molding, disposed on the first substrate surface, wherein the packaging molding encapsulates the at least one memory die and the first substrate surface, and wherein the packaging molding fills the first series of holes and the second series of holes.

[0142] Aspect 19: The memory device of aspect 18, wherein the at least one memory die includes a first die edge laterally arranged 100 microns or less from the first substrate edge and a second die edge arranged opposite the first die edge and laterally arranged 100 microns or less from the second substrate edge.

[0143] Aspect 20: The memory device of any of aspects 18-19, wherein each hole in the first series of holes and each hole in the second series of holes is a half hole.

[0144] Aspect 21: The memory device of any of aspects 18-20, wherein each hole in the first series of holes and each hole in the second series of holes partially extends from the first substrate surface to the second substrate surface.

[0145] Aspect 22: The memory device of any of aspects 18-21, wherein each hole in the first series of holes and each hole in the second series of holes extend completely from the first substrate surface to the second substrate surface.

[0146] Aspect 23: A semiconductor package, comprising: a circuit substrate, comprising: a first substrate surface; a second substrate surface, arranged opposite to the first substrate surface; a first substrate edge, extending from the first substrate surface to the second substrate surface; a second substrate edge, extending from the first substrate surface to the second substrate surface and arranged opposite to the first substrate edge; a third substrate edge, extending from the first substrate surface to the second substrate surface; and a fourth substrate edge, extending from the first substrate surface to the second substrate surface and arranged opposite to the third substrate edge; wherein a first series of holes are arranged along the first substrate edge of the circuit substrate to form a first through-hole edge, wherein each hole in the first series of holes extends at least partially from the first substrate surface toward the second substrate surface, wherein a second series of holes are arranged along the second substrate edge of the circuit substrate to form a second through-hole an edge, wherein each hole in the second series of holes extends at least partially from the first substrate surface toward the second substrate surface, wherein a third series of holes is arranged along the third substrate edge of the circuit substrate to form a third through-hole edge, wherein each hole in the third series of holes extends at least partially from the first substrate surface toward the second substrate surface, wherein a fourth series of holes is arranged along the fourth substrate edge of the circuit substrate to form a fourth through-hole edge, wherein each hole in the fourth series of holes extends at least partially from the first substrate surface toward the second substrate surface; at least one die arranged on the first substrate surface; and a packaging housing disposed above the first substrate surface, wherein the packaging housing encapsulates the at least one die and the first substrate surface, and wherein the packaging housing fills each hole in the first series of holes, the second series of holes, the third series of holes, and the fourth series of holes.

[0147] Aspect 24: The semiconductor package of aspect 23, wherein each hole of the first series of holes, the second series of holes, the third series of holes, and the fourth series of holes has a perimeter defined by a circular segment.

[0148] Aspect 25: A method comprising: attaching at least one die to a circuit substrate, the circuit substrate comprising: a first substrate surface on which the at least one die is arranged; a second substrate surface arranged opposite to the first substrate surface; and a series of holes arranged along a first sawing path, wherein each hole in the series of holes extends at least partially from the first substrate surface toward the second substrate surface; depositing a casing material on the first substrate surface (including on the first sawing path) to encapsulate the at least one die, wherein depositing the casing material includes filling the series of holes with the casing material; and sawing through the casing material and the circuit substrate along the first sawing path to form a packaging edge of a semiconductor packaging assembly, wherein the casing material deposited in the series of holes forms a portion of the packaging edge.

[0149] Aspect 26: The method according to Aspect 25, wherein: sawing through the housing material and the circuit substrate along the first sawing path forms a substrate edge of the circuit substrate as part of the package edge, and the housing material is mechanically interlocked with the circuit substrate along the substrate edge.

[0150] Aspect 27: The method of aspect 26, wherein the substrate edge of the semiconductor packaging assembly includes a remaining portion of each hole in the series of holes, and the remaining portion of each hole in the series of holes has a perimeter defined by a circular segment.

[0151] Aspect 28: The method of any one of aspects 25 to 27, wherein each hole in the series of holes extends partially from the first substrate surface to the second substrate surface.

[0152] Aspect 29: The method of aspect 28, wherein: a bottom of each hole in the series of holes is defined by the circuit substrate, and the housing material is in direct contact with the circuit substrate along the bottom of each hole in the series of holes.

[0153] Clause 30: The method of any one of clauses 25 to 29, wherein each hole in the series of holes extends completely from the first substrate surface to the second substrate surface.

[0154] Aspect 31: A method comprising: attaching at least one first die to a first device region of a circuit substrate; attaching at least one second die to a second device region of the circuit substrate, wherein the circuit substrate comprises a first substrate surface on which the at least one first die and the at least one second die are arranged, and a second substrate surface arranged opposite to the first substrate surface, wherein the first device region and the second device region are defined by a series of holes arranged along a first singulation path, wherein each hole in the series of holes at least partially extends from the first substrate surface toward the second substrate surface; depositing a shell material on the first substrate surface, including between the at least one first die, the The casing material is deposited over at least one second die and the first singulation path to encapsulate the at least one first die, the at least one second die and the first singulation path, wherein depositing the casing material includes filling the series of holes with the casing material; and cutting through the casing material and the circuit substrate along the first singulation path to separate the first device area and the second device area to form a first packaging edge of a first semiconductor package assembly corresponding to the first device area and to form a second packaging edge of a second semiconductor package assembly corresponding to the second device area, wherein the casing material deposited in the series of holes forms a portion of the first packaging edge and the second packaging edge.

[0155] Aspect 32: A method according to Aspect 31, wherein: the shell material and the circuit substrate are cut through along the first singulation path to form a first substrate edge of the circuit substrate as part of the first packaging edge and a second substrate edge of the circuit substrate as part of the second packaging edge, the shell material is mechanically interlocked with the circuit substrate of the first semiconductor packaging assembly along the first substrate edge, and the shell material is mechanically interlocked with the circuit substrate of the second semiconductor packaging assembly along the second substrate edge.

[0156] Aspect 33: A method according to Aspect 32, wherein: the first substrate edge of the first semiconductor package assembly includes a first remaining portion of each hole in the series of holes, and the first remaining portion of each hole in the series of holes has a first shape defined by a first circular segment, and the second substrate edge of the second semiconductor package assembly includes a second remaining portion of each hole in the series of holes, and the second remaining portion of each hole in the series of holes has a second shape defined by a second circular segment.

[0157] Aspect 34: A method according to any one of Aspects 31 to 33, wherein: the series of holes is a first series of holes, wherein the first device area is further defined by a second series of holes arranged along a second singulation path, wherein each hole in the second series of holes extends at least partially from the first substrate surface toward the second substrate surface, wherein the second device area is further defined by a third series of holes arranged along a third singulation path, wherein each hole in the third series of holes extends at least partially from the first substrate surface toward the second substrate surface, wherein depositing the shell material on the first substrate surface further includes depositing the shell material over the second singulation path and the third singulation path to encapsulate the The second singulation path and the third singulation path, wherein depositing the housing material on the first substrate surface further includes filling the second series of holes and the third series of holes with the housing material, wherein the method further includes: cutting through the housing material and the circuit substrate along the second singulation path to form a third packaging edge of the first semiconductor package assembly, wherein the housing material deposited in the second series of holes forms a portion of the third packaging edge; and cutting through the housing material and the circuit substrate along the third singulation path to form a fourth packaging edge of the second semiconductor package assembly, wherein the housing material deposited in the third series of holes forms a portion of the fourth packaging edge. Cutting through the housing material and the circuit substrate along the second singulation path to form a third packaging edge of the first semiconductor package assembly, wherein the housing material deposited in the second series of holes forms a portion of the third packaging edge; and cutting through the housing material and the circuit substrate along the third singulation path to form a fourth packaging edge of the second semiconductor package assembly, wherein the housing material deposited in the third series of holes forms a portion of the fourth packaging edge.

[0158] Aspect 35: The method of Aspect 34, wherein the first singulation path, the second singulation path, and the third singulation path extend parallel to each other.

[0159] Aspect 36: A system configured to perform one or more operations recited in one or more of aspects 1-35.

[0160] Aspect 37: An apparatus comprising means for performing one or more operations recited in one or more of Aspects 1-35.

[0161] Aspect 38: A non-transitory computer-readable medium storing an instruction set, the instruction set comprising one or more instructions that, when executed by a device, cause the device to perform one or more operations recited in one or more of aspects 1 to 35.

[0162] Aspect 39: A computer program product comprising instructions or codes for performing one or more operations recited in one or more of Aspects 1-35.

[0163] The foregoing disclosure provides illustration and description but is not intended to be exhaustive or to limit the embodiments to the precise form disclosed.Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the embodiments described herein.

[0164] Each of the illustrated x-, y-, and z-axes is generally perpendicular to the other two axes. In other words, the x-axis is generally perpendicular to the y- and z-axes, the y-axis is generally perpendicular to the x- and z-axes, and the z-axis is generally perpendicular to the x- and y-axes. In some cases, a single reference numeral is shown to refer to a surface, or less than all instances of a part may be labeled with all surfaces of the part. All instances of a part may include associated surfaces of the part, even though not every surface is labeled.

[0165] The orientation of various elements in the figure is shown as an example, and the illustrated example can be rotated relative to the depicted orientation. The description provided herein and the attached claims relate to any structure with the described relationship between various features, regardless of whether the structure is a specific orientation of the diagram or rotated relative to this orientation. Similarly, for ease of description, spatial relative terms such as "below ... ", "below ... ", "lower", "above ... ", "upper", "middle", "left" and "right" are used in this article to describe the relationship between an element and one or more other elements, as illustrated in the figure. In addition to the orientation depicted in the figure, spatial relative terms also wish to cover different orientations of elements, structures and / or assemblies in use or operation. Structures and / or assemblies can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article can be explained because of this. In addition, the cross-sectional views in the figure only show the features in the plane of the cross section, and the materials behind the plane of the cross section are not shown (unless otherwise indicated) to simplify the diagram.

[0166] As used herein, the terms “substantially” and “approximately” mean “within reasonable manufacturing and measurement tolerances.” Unless expressly indicated otherwise, all ranges described herein include the numbers at the ends of the ranges.

[0167] In addition, it should be understood that the disclosure of multiple actions or functions disclosed in this specification or in the claims may not be interpreted as being in a specific order. Therefore, the disclosure of multiple actions or functions will not limit these to a specific order unless such actions or functions are not interchangeable for technical reasons. In addition, in some embodiments, a single action may include or may be decomposed into multiple sub-actions. Unless explicitly excluded, such sub-actions may be included as part of the disclosure of this single action.

[0168] Even if the specific combination of features is described in the claims and / or disclosed in this specification, these combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features can be combined in a manner that is not clearly described in the claims and / or not clearly disclosed in this specification. For example, the disclosure includes each of the attached technical solutions in the technical solution group in combination with each other individual technical solution in the technical solution group and each combination of multiple technical solutions in the technical solution group. As used herein, the phrase "at least one" in a project list refers to any combination of the project, including a single member. As an example, "at least one of the following: a, b or c" is intended to cover a, b, c, a+b, a+c, b+c and a+b+c, and any combination with multiples of the same element (for example, a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c and c+c+c, or any other sorting of a, b and c).

[0169] The elements, actions or instructions used herein should not be interpreted as critical or necessary unless clearly described as such. In addition, as used herein, the articles "one" and "an" are intended to include one or more items and can be used interchangeably with "one or more". In addition, as used herein, the article "said" is intended to include one or more items referenced in conjunction with the article "said" and can be used interchangeably with "said one or more". In the case of only one project, the phrases "only one", "single" or similar language are used. In addition, as used herein, the term "has / have / having" or the like is intended to be an open term (for example, an element "having" A may also have B) that does not limit the elements modified. In addition, unless otherwise explicitly stated, the phrase "based on" is intended to mean "based at least in part". As used herein, the term "multiple (multiple)" can be replaced with "a plurality (a plurality of)", and vice versa. Furthermore, as used herein, the term "or" when used in a series is intended to be inclusive and used interchangeably with "and / or" unless expressly stated otherwise (eg, if used in combination with "either" or "only one of...").

Claims

1. A semiconductor device assembly comprising: A circuit substrate comprising: a first substrate surface; a second substrate surface arranged opposite to the first substrate surface; a first substrate edge extending from the first substrate surface to the second substrate surface; and a second substrate edge extending from the first substrate surface to the second substrate surface and arranged opposite to the first substrate edge; a series of holes arranged along the first substrate edge of the circuit substrate, wherein each hole in the series of holes extends at least partially from the first substrate surface toward the second substrate surface; at least one die disposed on the first substrate surface; and A packaging enclosure is disposed over the first substrate surface, wherein the packaging enclosure encapsulates the at least one die and the first substrate surface, and wherein the packaging enclosure fills each hole in the series of holes.

2. The semiconductor device assembly of claim 1, wherein the package housing is mechanically interlocked with the first substrate edge.

3. The semiconductor device assembly of claim 1, wherein the first substrate edge is a perforated edge formed using the series of holes.

4. The semiconductor device assembly of claim 1, wherein each hole in the series of holes defines a respective concave segment of the first substrate edge.

5. The semiconductor device assembly of claim 1, wherein each hole in the series of holes has a perimeter having a generally semicircular shape.

6. The semiconductor device assembly of claim 1, wherein each hole in the series of holes extends partially from the first substrate surface to the second substrate surface.

7. The semiconductor device assembly according to claim 6, wherein: A bottom of each hole in the series of holes is defined by the circuit substrate, and The package housing is in direct contact with the circuit substrate at the bottom of each hole in the series of holes.

8. The semiconductor device assembly of claim 1, wherein each hole in the series of holes extends completely from the first substrate surface to the second substrate surface.

9. The semiconductor device assembly according to claim 1, wherein: The circuit substrate includes a solder mask formed on the first substrate surface to cover the first substrate surface, wherein the first substrate surface is exposed at an edge of the first substrate, wherein the first substrate edge lacks the solder mask, and the package shell is in direct contact with the first substrate surface at the first substrate edge.

10. The semiconductor device assembly of claim 9, wherein the first substrate surface is a prepreg layer or a core layer.

11. The semiconductor device assembly according to claim 1, wherein: The series of holes is a first series of holes, and The semiconductor device assembly further comprises: a second series of holes arranged along the second substrate edge of the circuit substrate, wherein each hole in the second series of holes extends at least partially from the first substrate surface toward the second substrate surface, wherein the encapsulating housing fills the second series of holes.

12. The semiconductor device assembly of claim 11, wherein the encapsulating housing is mechanically interlocked with the first substrate edge and the second substrate edge.

13. The semiconductor device assembly of claim 11, wherein the first substrate edge is a first through-hole edge formed using the first series of holes, and the second substrate edge is a second through-hole edge formed using the second series of holes.

14. The semiconductor device assembly of claim 11, wherein each hole in the first series of holes and each hole in the second series of holes has a perimeter bounded by an arc and a chord of a circle.

15. The semiconductor device assembly of claim 1, wherein the at least one die comprises a plurality of dies arranged in a stacked configuration, wherein the at least one die comprises a die edge laterally arranged 100 microns or less from an edge of the first substrate.

16. A memory device comprising: A circuit substrate comprising: a first substrate surface; a second substrate surface arranged opposite to the first substrate surface; a first substrate edge extending from the first substrate surface to the second substrate surface; and a second substrate edge extending from the first substrate surface to the second substrate surface and arranged opposite to the first substrate edge. wherein a first series of holes are arranged along the first substrate edge of the circuit substrate to form a first perforated edge, wherein each hole in the first series of holes extends at least partially from the first substrate surface toward the second substrate surface, wherein a second series of holes are arranged along the second substrate edge of the circuit substrate to form a second perforated edge, wherein each hole in the second series of holes extends at least partially from the first substrate surface toward the second substrate surface; at least one memory die disposed on the first substrate surface; and A packaging molding is disposed on the first substrate surface, wherein the packaging molding encapsulates the at least one memory die and the first substrate surface, and wherein the packaging molding fills the first series of holes and the second series of holes.

17. The memory device of claim 16, wherein the at least one memory die includes a first die edge laterally arranged 100 microns or less from the first substrate edge and a second die edge arranged opposite the first die edge and laterally arranged 100 microns or less from the second substrate edge.

18. A method comprising: attaching at least one die to a circuit substrate comprising a first substrate surface on which the at least one die is arranged, a second substrate surface arranged opposite the first substrate surface, and a series of holes arranged along a first sawing path, wherein each hole in the series of holes extends at least partially from the first substrate surface toward the second substrate surface; depositing a casing material on the first substrate surface, including on the first sawing path, to encapsulate the at least one die, wherein depositing the casing material includes filling the series of holes with the casing material; and sawing through the casing material and the circuit substrate along the first sawing path to form a package edge of a semiconductor package assembly, The casing material deposited in the series of holes forms part of the package edge.

19. The method of claim 18, wherein: Sawing through the housing material and the circuit substrate along the first sawing path forms a substrate edge of the circuit substrate as part of the package edge, and The casing material is mechanically interlocked with the circuit substrate along the substrate edge.

20. The method of claim 19, wherein the substrate edge of the semiconductor packaging assembly includes a remaining portion of each hole in the series of holes, and the remaining portion of each hole in the series of holes has a perimeter defined by a circular segment.

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