Digital-to-analog converter, circuit device, discriminator, and photon counting system

Abstract

A digital-to-analog converter (100, 1001,... 100n) DAC comprises a coarse resistor string digital-to-analog conversion unit (121) for selectively outputting a 2N-level analog voltage in response to high N-bit digital data, where N is a natural number greater than or equal to 2, a fine resistor string digital-to-analog conversion unit (122) for selectively outputting a 2N-level analog voltage in response to high N-bit digital data, and a combining unit (109) for combining the coarse resistor string digital-to-analog conversion unit (121) with the fine resistor string digital-to-analog conversion unit (122). The thin resistor string digital-to-analog conversion unit (122) is configured to selectively output a 2N-level analog voltage in response to low N-bit digital data, and the combining unit (109) is configured to combine an output of the thick resistor string digital-to-analog conversion unit (121) and an output of the thin resistor string digital-to-analog conversion unit (122). The combination unit (109) comprises a capacitor (111). An output of the thick resistor string digital-to-analog conversion unit (121) and an output of the thin resistor string digital-to-analog conversion unit (122) can be connected to a first terminal (137) of the capacitor (111).

Description

Technical Field

[0001] The present disclosure relates to a digital-to-analog voltage converter. The present disclosure also relates to a circuit arrangement, a discriminator, a photon counting system, and a device for medical diagnosis. Background Art

[0002] Digital-to-analog converters (DACs) are used to represent digital values ​​in the analog domain. One type of DAC is represented by resistive DACs, which generate multiple equally spaced intermediate voltages by means of matched resistor strings connected between two reference voltages, and select the intermediate voltages through analog multiplexers or switches to supply the DAC outputs. As the number of DAC stages increases, the complexity of the analog multiplexers also increases, and this type of DAC tends to become area intensive when the resolution exceeds 8 bits.

[0003] It is an object of the present invention to provide an improved digital-to-analogue converter, an improved circuit arrangement, an improved discriminator, an improved photon counting system and an improved device for medical diagnosis. Summary of the invention

[0004] According to an embodiment, the above objects are achieved by the subject matter claimed according to the independent claim. Advantageous further developments are defined in the dependent claims.

[0005] A digital-to-analog converter DAC includes a coarse resistor string digital-to-analog conversion unit and a fine resistor string digital-to-analog conversion unit, wherein the coarse resistor string digital-to-analog conversion unit is used to selectively output a high-N-bit digital data. N The analog voltage level, wherein N is a natural number greater than or equal to 2, the thin resistor string digital analog conversion unit is used to selectively output 2 in response to the lower N-bit digital data N The DAC further includes a combining unit for combining the output of the thick resistor string digital analog conversion unit and the output of the thin resistor string digital analog conversion unit. The combining unit includes a capacitor. The output of the thick resistor string digital analog conversion unit and the output of the thin resistor string digital analog conversion unit can be connected to a first terminal of the capacitor.

[0006] According to an embodiment, the thick resistor string digital analog conversion unit includes a thick resistor string and a thick multiplexer, and the thick multiplexer is configured to be connected to a selected tap between resistors in the thick resistor string. In addition, the thin resistor string digital analog conversion unit may include a thin resistor string and a thin multiplexer, and the thin multiplexer is configured to be selectively connected to a selected tap between resistors in the thin resistor string. The thick resistor string and the thin resistor string can be connected in series.

[0007] The DAC may further include a first buffer that receives a reference voltage and controls a voltage supplied to the coarse resistor string.

[0008] According to an embodiment, the first buffer includes a first buffer capacitor for storing an offset voltage. The first buffer may further include a second buffer capacitor for storing a reference voltage.

[0009] For example, the first buffer may include a first buffer circuit and a second buffer circuit, each of the first buffer circuit and the second buffer circuit respectively including a first buffer capacitor. The first buffer circuit and the second buffer circuit may be configured to operate alternately.

[0010] According to an embodiment, the thick resistor string digital-to-analog conversion unit further includes a high-ohmic thick resistor string connected in parallel with the thick resistor string, the resistance of the high-ohmic thick resistor string being greater than the resistance of the thick resistor string. The high-ohmic thick resistor string is configured to be connected to the thick multiplexer when the thick multiplexer is connected to the first terminal of the capacitor.

[0011] In addition, the thin resistor string digital analog conversion unit may also include a low-ohmic thin resistor string, the low-ohmic thin resistor string is connected in parallel with the thin resistor string, and the resistance of the low-ohmic thin resistor string is less than the resistance of the thin resistor string. The low-ohmic thin resistor string is configured to be connected to the thin multiplexer when the thin multiplexer is connected to the first terminal of the capacitor.

[0012] According to an embodiment, the DAC may further include an additional switchable resistor string located between the thick resistor string and the thin resistor string.

[0013] According to a further embodiment, a circuit device includes a digital-to-analog converter DAC and a comparator. The DAC includes a coarse resistor string digital-to-analog conversion unit, a fine resistor string digital-to-analog conversion unit, and a combining unit, wherein the coarse resistor string digital-to-analog conversion unit is configured to selectively output 2 in response to high N-bit digital data. N The analog voltage level, wherein N is a natural number greater than or equal to 2, the thin resistor string digital analog conversion unit is used to selectively output 2 in response to the lower N-bit digital data N The analog voltage is a level, and the combining unit is used to combine the output of the thick resistor string digital analog conversion unit and the output of the fine resistor string digital analog conversion unit. The combining unit includes a capacitor. The output of the fine resistor string digital analog conversion unit can be connected to a first terminal of the capacitor, and the second terminal of the capacitor can be connected to a first input of the comparator.

[0014] For example, the output of the coarse resistor string digital-to-analog conversion unit can be connected to the second input of the comparator.

[0015] According to an embodiment, the output of the coarse resistor string digital analog conversion unit can be connected to a front-end circuit. The front-end circuit is configured to receive an input signal and supply a processed signal to a second input of the comparator. The processed signal is generated based on the input signal and the output of the coarse resistor string digital analog conversion unit.

[0016] For example, the output of the coarse resistor string digital-to-analog conversion unit may be V / I converted before being supplied to the front-end circuit.

[0017] According to an embodiment, the output of the thick resistor string digital analog conversion unit can be connected to the first terminal of the capacitor. The circuit arrangement may also include a front-end circuit configured to receive an input signal and supply the processed signal to a second input of the comparator. The front-end circuit may be permanently connected to the second input of the comparator. The processed signal may be based on the input signal and the output of the thick resistor string digital analog conversion unit.

[0018] According to a further embodiment, a discriminator includes a plurality of discriminator stages. Each discriminator stage includes a comparator, a coarse multiplexer, and a fine multiplexer. The coarse multiplexer is connectable to selected taps of resistors connected to the coarse resistor string to selectively output 2 in response to high N-bit digital data. N The fine multiplexer can be connected to a selected tap of a resistor connected to the fine resistor string to selectively output 2 in response to the lower N bits of digital data. N The discriminator stage further comprises a combining unit for combining the output of the coarse multiplexer and the output of the fine multiplexer. The combining unit comprises a capacitor. The output of the fine multiplexer can be connected to a first terminal of the capacitor, and a second terminal of the capacitor can be connected to a first input of the comparator.

[0019] For example, the output of the coarse multiplexer can be connected to the second input of the comparator.

[0020] Furthermore, the output of the coarse multiplexer may be further connected to a front end circuit configured to receive the input signal and supply a processed signal to a second input of the comparator, the processed signal being based on the input signal and the output of the coarse multiplexer.

[0021] According to an embodiment, a photon counting system comprises the discriminator defined above.A device for medical diagnosis may comprise a photon counting system. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of embodiments of the present invention and are included in this specification and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present invention and are used to explain the principles together with the description. Other embodiments of the present invention and many expected advantages will be easily appreciated because they can be better understood by referring to the following detailed description. The elements in the drawings are not necessarily drawn to scale relative to each other, and the same reference numerals represent corresponding identical parts.

[0023] Figure 1 A schematic diagram of the photon counting system is shown.

[0024] Figure 2A and Figure 2B Embodiments of a DAC forming part of a discriminator stage are respectively shown.

[0025] FIG. 3A to FIG. 3E An example of a circuit arrangement forming part of a discriminator stage is shown in each case.

[0026] FIG. 4A to FIG. 4C Further examples of DACs forming part of the discriminator stage are shown respectively.

[0027] Figure 5A and Figure 5B An example of a DAC forming part of a discriminator stage is shown separately.

[0028] Figure 6 Another example of a photon counting system is shown.

[0029] Figure 7 Devices used in medical diagnostics were demonstrated. DETAILED DESCRIPTION

[0030] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document and in which specific embodiments in which the invention may be practiced are shown by way of example. In this regard, directional terms such as "top", "bottom", "front", "rear", "above", "on", "higher than", "leading", "following", etc. are used with reference to the directions of the illustrated diagrams being described. Since the components of the embodiments of the present invention can be placed in several different directions, these directional terms are used only for illustrative purposes and are not limiting in any way. It should be understood that other embodiments may be adopted and structural or logical changes may be made without departing from the scope defined by the claims.

[0031] The description of the embodiments is not restrictive. In particular, elements of the embodiments described herein may be combined with elements of different embodiments.

[0032] As used in this specification, the terms "coupled" and / or "electrically coupled" are not meant to indicate that elements must be directly coupled together - intermediate elements may be provided between the "coupled" or "electrically coupled" elements. The term "electrically connected" is intended to describe a low-ohmic electrical connection between elements that are electrically connected together. According to further embodiments and where appropriate, the term "electrically connected" may mean that the respective elements are "directly connected" or "directly and permanently connected."

[0033] The term "component A is permanently connected to component B" is intended to mean that there is a direct connection between component A and component B without a switch in between. This characteristic is still satisfied when a connection (e.g., corresponding wiring) is connected to component A and component B when either component A or B is disconnected from power or input signals.

[0034] As used herein, the terms "having", "comprising", "including", "containing", etc. are open terms, indicating the presence of stated elements or features, but not excluding additional elements or features. The articles "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0035] Figure 1 1 shows a schematic diagram of a photon counting system 20, which may include a digital-to-analog converter 100, which will be explained below. Figure 1 In the illustrated photon counting system 20, individual photon events 21 are detected and counted to obtain intensity information for spectral analysis. While in conventional image or X-ray sensors only the total input intensity is measured, in Figure 1 In the photon counting system shown, photons 21 are detected individually. Accordingly, the photon energy can be extracted. Figure 1 The illustrated photon counting system includes a photon detector 201, which may include special sensing materials that convert photons into current pulses. A front-end circuit 202 (e.g., a CMOS front-end circuit) converts these current pulses into voltage pulses. A signal is generated in which the height of the output voltage peak is related to the photon energy and thus contains spectral information. This can be accomplished by using a plurality of comparators 1051, 1052, ... 105 n The discriminator 200 digitizes the spectral information (i.e., the height of the output pulse). Different threshold voltages V are provided for different comparators. th1 、V th2 ……V thn By counting the outputs of the individual discriminators, the spectral distribution of the photon events can be determined.

[0036] For high-performance photon counting, the comparator threshold in the discriminator 200 needs to be defined with high resolution. Typically, hundreds of channels are integrated on a single die, and each channel contains a DAC array. Accordingly, each DAC needs to be implemented in the smallest possible area.

[0037] Different threshold voltages are generated by different DACs 1001, 1002, ... 100 n Supply. For example, a DAC can provide unequally spaced threshold voltages for a comparator. Since there is a relatively long time between different photon events, the threshold voltage needs to be refreshed. Therefore, the digital-to-analog conversion must be performed continuously.

[0038] like Figure 1 As shown, the discriminator 200 includes multiple DACs. Typically, a DAC cluster is implemented based on a shared architecture. In more detail, concepts are being developed based on which part of the circuit can be shared between different DACs. Specifically, the discriminator 200 may include multiple discriminator stages 210. i Each discriminator stage 210 i The comparator 105 and the discriminator stage 210 are included. i Associated DAC 100 i DAC additional elements in a single discriminator stage 210 i Shared between.

[0039] Figure 2A An example of a DAC 100 according to an embodiment is shown. The DAC 100 is a discriminator stage 210 forming a component of the discriminator 200. i components.

[0040] The DAC 100 includes a coarse resistor string digital-to-analog conversion unit 121 for selectively outputting 2 in response to high N-bit digital data. N The DAC 100 further includes a thin resistor string digital-to-analog conversion unit 122 for selectively outputting 2 in response to the lower N-bit digital data. N The DAC 10 further includes a combining unit 109 for combining the output of the coarse resistor string digital analog conversion unit 121 and the output of the fine resistor string digital analog conversion unit 122. The combining unit 109 includes a capacitor 111.

[0041] according to Figure 2AIn the illustrated embodiment, the output of the thick resistor string digital analog conversion unit 121 and the output of the thin resistor string digital analog conversion unit 122 can be connected to the first terminal 137 of the capacitor 111. As will be explained below, due to the presence of the capacitor 111 that combines the output of the thick resistor string digital analog conversion unit 121 and the output of the thin resistor string digital analog conversion unit 122, the second buffer stage can be omitted. Therefore, the area can be reduced.

[0042] The coarse resistor string digital-analog conversion unit 121 may include the coarse resistor string 101 and the coarse multiplexer 107. The fine resistor string digital-analog conversion unit 122 may include the fine resistor string and the fine multiplexer 108.

[0043] like Figure 2A The DAC shown includes a first buffer 112 that receives a first reference voltage (Vrefp) as an input. The first reference voltage (Vrefp) can be a positive voltage. The buffer 112 is connected to a thick resistor string 101. The term "resistor string" is used herein to refer to one or more resistors connected in series. The thick resistor string 101 includes a plurality of resistors and operates as a thick resistor string. The terms "coarse" and "fine" mentioned herein in relation to the resistor string refer to the voltage step or resolution on each resistor of the resistor string, rather than their resistance values. The plurality of resistors in the thick resistor string 101 can have equal resistance values, so that the potential difference is divided into the resistors of the thick resistor string 101 in equal steps. Similarly, the resistors in the thin resistor string 102 can have equal resistance values, so that the potential difference is divided into the thin resistor string 102 in equal steps. According to further embodiments, any transistor can have different resistance values, so that the potential difference is divided into nonlinear steps. The fine resistor string 102 covers only one coarse level. Accordingly, the fine voltage step size is used to interpolate the successive levels of the coarse resistor string 101.

[0044] The second buffer 113 receives a second reference voltage (Vrefn) lower than the first reference voltage (Vrefp). The thin resistor string 102 is connected to the second buffer 113A.

[0045] The coarse multiplexer 107 may be implemented as a coarse switch tree. For example, the coarse resistor string may include a plurality of voltage taps (contact points that the coarse multiplexer 107 can reach), and the coarse multiplexer 107 includes a plurality of switches. Each of the plurality of switches of the coarse multiplexer 107 is controllable to connect to one of the voltage taps of the coarse resistor string 101. The fine resistor string and the fine multiplexer 108 may be implemented in a corresponding manner.

[0046] When the bit string 103 is input to the DAC 100 (e.g., input to the coarse multiplexer 107), the switch of the coarse multiplexer 107 is activated according to the upper bit (e.g., the upper N-bit digital data). In addition, the switch of the fine multiplexer 108 is activated according to the lower N-bit digital data. Accordingly, the coarse resistor string digital-to-analog conversion unit 121 selectively outputs 2 N The analog voltage is outputted from the thin resistor string digital analog conversion unit 122 selectively according to the low N-bit digital data. N level analog voltage.

[0047] like Figure 2A As further shown, the thin resistor string 102 and the thick resistor string 101 are connected to each other at multiple discriminator stages 210. i Shared between.

[0048] Discriminator stage 210 i A comparator 105 is also included. The comparator 105 includes a pre-amplifier 106. The output of the comparator 105 is used for each discriminator stage 210. i The comparator voltage V C,I . Comparator voltage V C,I It depends on the comparison result between the voltage input of the front-end circuit 202 and the analog threshold voltage Vth.

[0049] The front-end circuit 202 (eg, a CMOS front-end circuit) receives the current signal from the detector 201. The front-end circuit 202 may include a charge-sensitive amplifier. For example, the inverting input of the charge-sensitive amplifier may receive the current signal I in The feedback resistor may be connected between the inverting input of the charge sensitive amplifier and the output of the charge sensitive amplifier. The front end circuit 202 may include a shaping amplifier stage (not shown) configured to receive the output of the charge sensitive amplifier and output a voltage signal including a bell-shaped pulse.

[0050] like Figure 2A As further shown, the first input of the comparator 105 or the preamplifier 106 is in phase During the period, it is connected to the reference voltage Vref. During this period, the first input of the comparator 105 or the preamplifier 106 is connected to the front-end circuit 202. During this period, the output of the preamplifier 106 is fed back to the second input of the preamplifier 106. The discriminator stage 210 iOr the DAC 100 includes a capacitor 111. For example, the first input may be a non-inverting input of a comparator and the second input may be an inverting input of the comparator. As will be explained below, due to this configuration, the preamplifier 106 may perform offset compensation in an auto-zero loop, wherein the offset is stored on the capacitor 111. In general, depending on the polarity of the signal output by the shaping amplifier stage, the first input may be a non-inverting input or an inverting input.

[0051] Figure 2A The inset shows the operation of the discriminator stage 210. i Different stages of and In the first stage During this time, the coarse voltage is sampled. The coarse voltage is selected by the coarse multiplexer 107. The selected coarse voltage is sampled to the capacitor 111 with respect to the reference voltage. As a result, the difference between the comparator offset voltage and the coarse DAC voltage is stored on the capacitor 111. Therefore, the complexity and capacitor area are reduced.

[0052] In the embodiment including a plurality of discriminator stages 210 i In the photon counting system of FIG. 1 , several different coarse voltages can be sampled in parallel by connecting several independent coarse multiplexers 107 to the coarse resistor string 101. This allows the generation of the DAC cluster required for the discriminator 200 without increasing the static power consumption. Therefore, this topology is highly scalable. The fine voltage is in the second stage The fine voltage of each DAC 100 in the cluster is selected by an independent multiplexer 108 and connected in series with a respective capacitor 111 that holds the coarse voltage and the comparator offset voltage. Accordingly, in phase The output voltage Vth,comp output by the preamplifier 106 is given by:

[0053] Vth,comp=Vref–Vcoarse+Vfine

[0054] The reference voltages applied to the coarse resistor string 101 and the fine resistor string 102 do not need to be the same. In most practical cases, they can be the same. In this case, the DAC range can be adjusted by introducing a voltage drop via the resistor 114 above the coarse resistor string 101 to move the coarse voltage relative to Vref.

[0055] Due to the above configuration, in particular, since the combination unit 109 includes the capacitor 111, the area of ​​the DAC can be reduced. In addition, due to the presence of the capacitor 111, the offset voltage can be compensated.

[0056] Figure 2BDemonstrates the formation of discriminator stage 210 i Another example of a portion of DAC 100 . Figure 2B The embodiments shown in Figure 2A Same components as in Figure 2A The difference from the embodiment shown in FIG. 1 is that the second buffer 113 is replaced by a low-ohmic ground connection. Accordingly, the thin resistor string 102 is grounded. As a result, the area and power can be further reduced.

[0057] As explained above, according to Figure 2A and Figure 2B In the embodiment shown in FIG. 1 , the combination of the coarse voltage and the fine voltage is in the stage achieved during the period.

[0058] Figure 3A The circuit arrangement 115 and further the corresponding discriminator stage 210 using different switching schemes are shown. i Specifically, as shown in the figure, in the stage During the period, the coarse voltage is applied to the non-inverting input of the preamplifier 106 instead of connecting the reference voltage to the non-inverting input of the preamplifier 106. In addition, during the phase During this period, a thin voltage is applied to the first terminal 137 of the capacitor 111. In the phase During the photon counting phase, the output of the preamplifier 106 is input to the inverting input of the preamplifier 106. During the counting phase, the fine multiplexer 108 is no longer connected to the capacitor 111. Instead, the first terminal 137 of the capacitor 111 is pulled to ground or the reference voltage. During this time, the DAC is no longer needed and can be turned off. As a result, power can be saved.

[0059] This switching scheme results in an effective comparator threshold voltage of

[0060] Vth,comp=Vcoarse–Vfine

[0061] Accordingly, Figure 3A The circuit device 115 including the digital-to-analog converter DAC 100 and the comparator 105 is shown. The DAC includes a coarse resistor string digital-to-analog conversion unit 121 and a fine resistor string digital-to-analog conversion unit 122. The coarse resistor string digital-to-analog conversion unit 121 is used to selectively output 2 in response to the upper N-bit digital data. N The analog voltage level, wherein N is a natural number greater than or equal to 2, the thin resistor string digital analog conversion unit 122 is used to selectively output 2 in response to the lower N-bit digital data. NThe DAC further includes a combining unit for combining the output of the coarse resistor string digital analog conversion unit 121 with the output of the fine resistor string digital analog conversion unit 122. The combining unit 109 includes a capacitor 111. The output of the fine resistor string digital analog conversion unit can be connected to a first terminal of the capacitor 111. The first terminal 137 of the capacitor 111 can be connected to a first input of the comparator 105.

[0062] As explained above, according to Figure 2A , Figure 2B and Figure 3A In the embodiment shown in During this period, the front-end circuit 202 is connected to the discriminator stage 210 via the switch 104. i The switch 104 forms an RC filter in combination with the comparator parasitic input capacitance. This can lead to considerable distortion and speed limitations when the MOS transistor switch 104 is operated at low supply voltages with low overdrive. To this end, according to a further embodiment, the front-end circuit 202 can be directly and permanently connected to the respective discriminator stage 210. i All comparators 105 in.

[0063] Also refer to Figure 3B and Figure 3C This is explained. When using this device, in the stage During this period, it may not be possible to i The comparators in the circuit 105 are applied with separate rough voltages. Thus, the comparators 105 can be offset compensated one by one. Alternatively, Figure 2A or Figure 2B The scheme shown in the figure, where the rough voltage is in the phase applied to capacitor 111 during the counting phase, while the fine voltage Added during.

[0064] according to Figure 3B In the embodiment shown, the front end circuit 202 can be directly and permanently connected to each comparator 105. In addition, in the stage During this period, the coarse voltage is applied to the baseline control circuit for controlling the baseline of the signal output via the front-end circuit 202. During this period, the reference voltage V b is applied to the baseline control circuit. This reference voltage or baseline voltage corresponds to the target voltage for the baseline. The signal input is used as a reference for the baseline control circuit. Thus, in this case, the front end circuit 202 or the shaping circuit can act as a buffer, driving the comparator with a voltage proportional to the applied coarse voltage or baseline reference voltage. During this period, the signal input to the front-end circuit 202 may be disconnected to ensure that the output of the front-end circuit 202 is not disturbed.

[0065] like Figure 3B As further shown, according to this embodiment, the coarse multiplexer 107 is shared between the different stages. Accordingly, the different comparators of the discriminator 210 are not calibrated in parallel, but only one at a time (per frame).

[0066] according to Figure 3B In the illustrated embodiment, since the fine multiplexer 108 is connected to the first terminal 137 of the capacitor 111 and the coarse multiplexer 107 is not connected to the capacitor, the fine voltage can be subtracted again.

[0067] Figure 3C shows the output of the coarse multiplexer 107 in phase During the configuration, the first terminal 137 of the capacitor 111 is connected to the output of the fine multiplexer 108 in phase The period is connected to the first terminal 137 of the capacitor.

[0068] according to Figure 3D In the illustrated embodiment, the circuit device 115 further includes a voltage-to-current converter 116 disposed between the coarse multiplexer 107 and the front-end circuit 202. The output of the coarse multiplexer 107 is converted into a current by the voltage-to-current converter 116 and fed to the front-end circuit 202 via a switch. Accordingly, the coarse voltage signal is injected into the front-end circuit 202 as a current signal. The front-end circuit 202 multiplies this coarse current with its transimpedance ZFB and provides a voltage output proportional to Vcoarse.

[0069] Figure 3E A further embodiment of the circuit arrangement 115 is shown, in which the front-end circuit 202 has a control input, the output of which is set to a high impedance state by the control circuit 118 (HZ block). Meanwhile, the voltage can be overwritten with the reference voltage directly at the input of the preamplifier 106. The input of the control circuit 118 is a digital control signal (logic 1).

[0070] According to a further concept, the first buffer 112 may be offset compensated to eliminate the effect of buffer offset.

[0071] Figure 4A shows that the discriminator stage 210 can be formed i1. The DAC 100 may be implemented in any of the ways discussed above. In addition, the first buffer 112 may be modified to provide offset compensation. More specifically, the buffer 112 may be implemented as a circuit including an amplifier 131 and a first buffer capacitor 119. Vref is applied to the inverting input of the amplifier 131. Vref is applied to the inverting input of the amplifier 131 via the phase During the closed switch 123, the output of the amplifier 131 is applied to the non-inverting input of the amplifier 131. The first buffer capacitor 119 is arranged between the auxiliary input and the ground terminal of the amplifier 131. The output of the amplifier 131 is connected to the ground terminal of the amplifier 131 via the phase The switch 126 which is closed during this time is fed back to the auxiliary input of the amplifier 131 .

[0072] In stage During this period, switches 123 and 126 are closed. Vref is applied to the inverting input and the non-inverting input of the amplifier 131. Therefore, the first buffer capacitor 119 is charged with a charge corresponding to the offset voltage of the amplifier 131. Figure 2A The description corresponds to the stage Stage During this time, switches 123 and 126 are open. At this stage, the output of amplifier 131 is offset compensated due to the charge stored in first buffer capacitor 119. The output of amplifier 131 is connected to the gate of transistor 134, which may be a P-MOSFET. The voltage supplied to coarse resistor string 101 and fine resistor string 102 is forced to Vref. The voltage output of coarse multiplexer 107 is stored on capacitor 111.

[0073] In stage During the photon counting phase, the Figure 2A The same process as described is performed. Figure 4A In the diagram, the output of the front-end circuit 202 is represented as V in The description of the front end circuit 202 is omitted in this figure.

[0074] Figure 4B A further example of DAC 100 is shown, in which the circuit implementing the first buffer 112 further includes a second buffer capacitor 120. The second buffer capacitor 120 is connected to a node between the amplifier 131 and the gate of the transistor 134. The circuit implementing the first buffer 112 is further modified. Due to the presence of the second buffer capacitor 120, the DAC 100 can be operated in two phases instead of three phases. Accordingly, in order to reduce the number of phases, the offset compensation of the first buffer 112 can be performed in the DAC operation phase. To keep the coarse tree operational, the buffer output voltage is stored on the second buffer capacitor 120 to During the period, transistor 134 is properly biased to source current. Depending on the phase The leakage may cause the thick tree current to droop significantly due to the length of the second buffer capacitor 120. In addition, the large second buffer capacitor 120 connected to the buffer output may complicate the frequency compensation.

[0075] Figure 4C A further embodiment of the first buffer 112 is shown, in which droop due to capacitor leakage can be avoided. Figure 4C In the illustrated configuration, the second buffer capacitor 120 is replaced by a second buffer circuit 125. Accordingly, Figure 4C As shown, the DAC includes a first buffer circuit 124 and a second buffer circuit 125. Each of the first buffer circuit 124 and the second buffer circuit 125 includes an amplifier and a first buffer capacitor 119. The corresponding switches are configured to be driven in complementary phases. Accordingly, only one buffer is connected to the thick tree at a time, while the other buffer is offset compensated. Accordingly, the combination of the first buffer circuit and the second buffer circuit implements a ping-pong buffer. Periodically swapping the buffers causes the buffers to be refreshed from a zero state. Accordingly, Figure 4C The demonstrated DAC 100 can operate faster.

[0076] Figure 5A A further embodiment of the DAC 100 is shown, in which the thick resistor string 101 and the thin resistor string 102 can be implemented in alternative ways. Additional components of the DAC can be connected with, for example, Figure 2A In addition, the DAC may also include components such as those already described in Figure 4C A first buffer circuit 124 and a second buffer circuit 125 are illustrated. It should be clearly understood that the voltage supply of the thick resistor string 101 and the thin resistor strings 101, 102 may be achieved in any manner.

[0077] With reference Figure 4C The disclosed embodiment is different, for example, a variable resistor string is introduced for the thick resistor string 101 and the thin resistor string 102. Thus, the average current consumption can be further reduced.

[0078] Typically, for matching purposes, the thick resistor string 101 is implemented with a greater number of taps than the thin string. At the same time, the thin resistor string 102 covers a small range, typically equal to or greater than the resolution of the thick string. Therefore, the resistance of the thin string is smaller than that of the thick string, making it more difficult to match the thin string at the stage. The dynamic settling during the period is better than that during the stage The dynamic stability during the period is faster. During this period, the capacitor 111 is charged, and in the phase This effect is enhanced during the period when only the parasitic capacitance is charged. During this period, stability is mainly limited by the parasitic capacitance and the speed of the reference buffer. Consider Figure 4C With the DAC shown, for example, the string current is determined primarily by the stability requirements of the RC circuit (including the coarse resistor string 101 , coarse multiplexer 107 , capacitor 111 , and the speed of the preamplifier 106 ), and significantly less by the dynamics of the thin resistor string 102 .

[0079] like Figure 5A As shown, a low ohmic thin resistor string 129 can be added in parallel to the high ohmic thin resistor string 102. The high ohmic thin resistor string 102 has a higher resistance than the above referenced example. Figure 4C The thin resistor string 102 is depicted as having a greater resistance.

[0080] In addition, a high ohmic thick resistor string 127 may be added in parallel to the low ohmic thick resistor string 101. The low ohmic thick resistor string 101 has a larger value than the above referenced example. Figure 4C The thick resistor string 101 is depicted as having a smaller resistance.

[0081] In stage During this period, when the fine multiplexer 108 is not connected to the capacitor 111, stability is important. During this period, a low ohmic resistor string is required. Accordingly, a parallel low ohmic thin resistor string 129 is added or replaced. During the period, because the stage occupies most of the frame time, power consumption is a consideration. During this time, the high ohmic thin resistor string 102 is used and the thick string is replaced with the high ohmic resistor 127. Typically, a thin resistor unit can be made of several thick resistor units in parallel to provide a good matching.

[0082] Through the stage Using a portion of the current and a higher ohmic string in the resistor string 102 saves current and area because a smaller number of parallel cells are used in the thin resistor string 102.

[0083] When one of the two coarse resistor strings 127 and 128 is not selected and no current flows therethrough, the resistor elements constituting the two paths are charged to Vref. When switching to the next stage, the selected coarse path settles at its final operating point through a current loop involving the resistor, its parasitic capacitance, and the local ground, making the transient process relatively fast and independent of the reference buffer.

[0084] according to Figure 5A In the embodiment shown in , the fine resistor string digital-to-analog conversion unit 122 also includes a low-ohmic fine resistor string 129, which is connected in parallel with the fine resistor string 102, and the resistance of the low-ohmic fine resistor string 129 is less than the resistance of the fine resistor string 102, and the low-ohmic fine resistor string 129 is configured to be connected to the fine multiplexer 108 when the fine multiplexer 108 is connected to the first terminal 137 of the capacitor 111.

[0085] In addition, the coarse resistor string digital-analog conversion unit 121 further includes a high-ohmic coarse resistor string 127 connected in parallel with the coarse resistor string 101. The resistance of the high-ohmic coarse resistor string 127 is greater than the resistance of the coarse resistor string 101, and the coarse resistor string 127 is configured to be connected to the coarse multiplexer 107 when the coarse multiplexer 107 is connected to the first terminal 137 of the capacitor 111.

[0086] The reference buffer can still be operable to regulate fast output current steps. The size and compensation of the output stage can be adjusted depending on the stage current.

[0087] according to Figure 5A In the illustrated embodiment, this can be achieved by disabling certain PMOS transistors on the source side using PMOS switches, thereby maintaining the bias of all PMOS elements and allowing fast recovery due to the low ohmic on-resistance of the switches.

[0088] Figure 5B A further embodiment is shown, according to which capacitor droop can be mitigated. As shown, the DAC 100 also includes an additional resistor string 135, which includes a switch that can be selectively turned on or off. Due to this additional resistor string 135, capacitor droop can be compensated. A fine voltage extension range can be achieved. Sub-LSB resolution can be achieved. For example, this additional resistor string 135 can be controlled by a digital word that is dynamically adjusted to compensate for the droop in the sampling capacitor. Possible operations are as follows: In stage During this period, switches 135 are all closed; in the stage During this time, a digital word is programmed to compensate for capacitor droop. In this case, positive droop can be compensated.

[0089] Another possible operation is as follows: During this period, a portion of the switches in the additional resistor string 135 are closed. During this time, the digital word is programmed to compensate for the capacitor droop. In this case, by closing a greater or lesser number of switches in the additional resistor string 135, both positive and negative droops can be compensated.

[0090] According to a further embodiment, an additional resistor string 135 may be arranged above the thick resistor string 101. During this time, the same operating principles as above are valid.

[0091] According to a further embodiment, the additional resistor string 135 may be arranged below the thin resistor string 102. In such an embodiment, the additional resistor string 135 may achieve a total resistance equal to one resistor unit of the thin resistor string 102, thereby Dynamic capacitor droop compensation and sub-LSB resolution of fine DAC voltages are achieved during this process.

[0092] Figure 6 An example of a photon counting system 20 is shown, which includes, for example, the photon counting system 20 described above with reference to Figure 4C The DAC 100 is described. Figure 6 Photon counting system with Figure 1 The photon counting systems presented are similar, so a detailed description of the components will be omitted. Figure 1 Unlike the illustrated embodiment, a single discriminator stage 210 i and other components of DAC 100 as described in reference to e.g. Figure 4C More specifically, refer to Figure 1 The discriminator 200 depicted comprises a plurality of discriminator stages 210 i , these discriminator stages 210 i You can follow Figure 6 It can be clearly understood that the discriminator stage 210 i The other components of DAC 100 may also be implemented in any other manner described above. Figure 6 The left side shows the different stages for operating the discriminator. As shown, in stage During this period, the first frame 136 is detected, and the phase Corresponding to the second frame 136 .

[0093] The photon counting system 20 may be, for example, a photon counting CT detector. In such applications, X-ray photons are generated externally and are attenuated while passing through the tissue or object being analyzed. The photon detector 201 converts each incident photon 21 into a charge packet that is processed by a CMOS front-end circuit 202. The amplitude of the voltage pulse generated at the output of the front-end circuit 202 is discretized by an array of comparators 105, each of which is a corresponding discriminator stage 201. i The array of comparators 105 is supplied with an array of threshold voltages covering a discretized range of voltage pulse amplitudes.

[0094] The discriminator 200 comprises a cluster of n voltage DACs 100, where a coarse resistor string 101 and a fine resistor string 102 are shared between all DACs 100. The coarse voltage is stored on capacitors 111 of respective comparators 105. As shown in the figure, the counting front end is connected to the comparator array through switches or directly, while in phase During this period, the front-end circuit 102 is placed in a high-ohmic state.

[0095] In CT applications, it is critical to maintain a low dead time (i.e., the time during which incident X-rays cannot be used for imaging) to minimize radiation dose to the patient. Comparator offset compensation must be completed during this short dead time window, leaving no time for a separate buffer compensation stage. Therefore, if Figure 6 As shown, a ping-pong buffer topology including a first buffer circuit 124 and a second buffer circuit 125 can be advantageously employed. Due to this concept, an idle buffer circuit 124, 125 can be offset compensated within a full frame time while still providing an operating path by another buffer.

[0096] As already explained, due to this morphology, photon counting systems can be used for medical applications.

[0097] Figure 7 A device 30 for medical diagnosis is shown, comprising the photon counting system 20 described above.

[0098] Although the embodiments of the present invention are described above, it is clear that further embodiments may be implemented. For example, further embodiments may include any sub-combination of the features described in the claims, or any sub-combination of the elements described in the above examples. Accordingly, the subject matter and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0099] Reference numerals list

[0100] 20 Photon counting system

[0101] 21 Photon

[0102] 30 Equipment for medical diagnosis

[0103] 100, 1001, 1002, ... 100 n Digital to Analog Converter

[0104] 101 Thick resistor string

[0105] 102 Thin resistor string

[0106] 103 bit string

[0107] 104 Switch

[0108] 105,1051,1052,……105 n Comparator

[0109] 106 Preamplifier

[0110] 107 Coarse Multiplexer

[0111] 108 Thin Multiplexer

[0112] 109 Combination Units

[0113] 110,1101,1102,...110 n counter

[0114] 111 Capacitor

[0115] 112 First Buffer

[0116] 113 Second buffer

[0117] 114 Resistors

[0118] 115 Circuit Devices

[0119] 116 Voltage-to-current converter

[0120] 117 Baseline Control Circuit

[0121] 118 Control Circuit

[0122] 119 First buffer capacitor

[0123] 120 Second buffer capacitor

[0124] 121 thick resistor string digital analog conversion unit

[0125] 122 thin resistor string digital analog conversion unit

[0126] 123 Switch

[0127] 124 First buffer circuit

[0128] 125 Second buffer circuit

[0129] 126 Switch

[0130] 127 High Ohm Thick Resistor String

[0131] 129 Low ohm thin resistor string

[0132] 131 Amplifier

[0133] 134 Transistors

[0134] 135 Additional resistor string

[0135] 136 frames

[0136] 137 First terminal of capacitor

[0137] 200 Discriminator

[0138] 201 Photon Detector

[0139] 202 front-end circuit

[0140] 210,2101,2102,……210 n Discriminator level

Claims

1. A circuit device (115), comprising a digital-to-analog converter (100, 1001, ... 100 n )DAC and comparator (105,1051,1052,...105 n ), The DAC (100, 1001, ... 100 n )include: A thick resistor string digital analog conversion unit (121) is used to selectively output 2 in response to high N-bit digital data N level analog voltage, where N is a natural number greater than or equal to 2; A thin resistor string digital analog conversion unit (122) for selectively outputting 2 in response to low N-bit digital data N level analog voltage, and A combining unit (109) is used to combine the output of the thick resistor string digital analog conversion unit (121) and the output of the thin resistor string digital analog conversion unit (122), wherein the combining unit (109) comprises a capacitor (111), The output of the thin resistor string digital-to-analog conversion unit (122) can be connected to a first terminal (137) of the capacitor (111), and a second terminal of the capacitor (111) can be connected to the comparator (105, 1051, 1052, ... 105 n )’s first input.

2. The circuit device (115) according to claim 1, wherein the output of the coarse resistor string digital-to-analog conversion unit (121) is connectable to the comparator (105, 1051, 1052, ... 105 n )’s second input.

3. The circuit arrangement (115) according to claim 1, wherein the output of the coarse resistor string digital-to-analog conversion unit (121) is connectable to a front-end circuit (202), wherein the front-end circuit (202) is configured to receive an input signal and supply a processed signal to the comparator (105, 1051, 1052, ... 105 n ), the processed signal being generated based on the input signal and the output of the coarse resistor string digital-to-analog conversion unit (121).

4. The circuit arrangement (115) according to claim 3, further comprising a voltage-to-current converter (116) arranged between the coarse multiplexer (107) and the front-end circuit (202).

5. The circuit arrangement (115) according to claim 1, wherein the output of the coarse resistor string digital-to-analog conversion unit (121) is connectable to the first terminal (137) of the capacitor (111), further comprising a circuit configured to receive an input signal and supply a processed signal to the comparator (105, 1051, 1052, ... 105 n ) of the front-end circuit (202) of the second input, the front-end circuit being permanently connected to the comparator (105, 1051, 1052, ... 105 n )'s second input, the processed signal being generated based on the input signal and the output of the coarse resistor string digital-to-analog conversion unit.

6. A discriminator (200) comprising a plurality of discriminator stages (210, 2101, 2102, ... 210 n ), each of the discriminator stages (210, 2101, 2102, ... 210 n )include Comparator (105, 1051, 1052, ... 105 n ), A coarse multiplexer capable of being connected to selected taps between resistors of the coarse resistor string to selectively output 2 in response to the upper N-bit digital data N Level analog voltage, Where N is a natural number greater than or equal to 2; A thin multiplexer capable of being connected to selected taps between resistors of the thin resistor string to selectively output 2 in response to low N-bit digital data N level analog voltage, and a combining unit for combining the output of the coarse multiplexer and the output of the fine multiplexer, the combining unit comprising a capacitor, The output of the thin multiplexer can be connected to a first terminal of the capacitor, and a second terminal of the capacitor can be connected to the comparator (105, 1051, 1052, ... 105 n )’s first input.

7. The discriminator (200) according to claim 6, wherein the output of the coarse multiplexer (107) is connectable to the comparators (105, 1051, 1052, ... 105 n )’s second input.

8. The discriminator (200) according to claim 6, wherein the output of the coarse multiplexer (107) is connectable to a front-end circuit (202), the front-end circuit (202) being configured to receive an input signal and supply a processed signal to the comparators (105, 1051, 1052, ... 105 n ), the processed signal being based on the input signal and the output of the coarse multiplexer (107).

9. A photon counting system (20) comprising the discriminator (200) according to any one of claims 6 to 8.

10. A device (30) for medical diagnosis comprising a photon counting system (20) according to claim 9.

11. A digital-to-analog converter (100, 1001, ... 100 n )DAC, including: A thick resistor string digital analog conversion unit (121) is used to selectively output 2 in response to high N-bit digital data N level analog voltage, where N is a natural number greater than or equal to 2; A thin resistor string digital analog conversion unit (122) for selectively outputting 2 in response to low N-bit digital data N level analog voltage, and a combining unit (109) for combining the output of the coarse resistor string digital-to-analog conversion unit (121) with the output of the fine resistor string digital-to-analog conversion unit (122), the combining unit (109) comprising a capacitor (111), the output of the coarse resistor string digital-to-analog conversion unit (121) and the output of the fine resistor string digital-to-analog conversion unit (122) being connectable to a first terminal of the capacitor (111), wherein the coarse resistor string digital-to-analog conversion unit (121) comprises a coarse resistor string (101) and a coarse multiplexer (107), the coarse multiplexer (107) being configured to be connected to selected taps between resistors of the coarse resistor string (101), and The thin resistor string digital-to-analog conversion unit (122) includes a thin resistor string (102) and a thin multiplexer (108), wherein the thin multiplexer (108) is configured to be connected to selected taps between resistors of the thin resistor string (102), and the coarse resistor string (101) and the thin resistor string (102) are connected in series.

12. The DAC (100, 1001, . . . 1002) according to claim 11 n ), further comprising a first buffer (112) receiving a reference voltage and controlling a voltage supplied to the coarse resistor string (101).

13. The DAC (100, 1001, . . . 1002) according to claim 12 n ), wherein the first buffer (112) includes a first buffer capacitor (119) for storing an offset voltage.

14. The DAC (100, 1001, . . . 1002) according to claim 13 n ), wherein the first buffer (112) further comprises a second buffer capacitor (120) for storing a reference voltage.

15. The DAC (100, 1001, . . . 1002) according to claim 13 n ), wherein the first buffer (112) includes a first buffer circuit (124) and a second buffer circuit (125), wherein each of the first buffer circuit and the second buffer circuit (124, 125) includes a first buffer capacitor (119), respectively, and the first buffer circuit (124) and the second buffer circuit (125) are configured to operate alternately.

16. The DAC (100, 1001, . . . 1002) according to any one of claims 11 to 15. n ), wherein the coarse resistor string digital-to-analog conversion unit (121) further comprises a high-ohmic coarse resistor string (127), the high-ohmic coarse resistor string (127) being connected in parallel with the coarse resistor string (121), the resistance of the high-ohmic coarse resistor string (127) being greater than the resistance of the coarse resistor string (121), and the high-ohmic coarse resistor string (127) being configured to be connected to the coarse multiplexer (107) when the coarse multiplexer (107) is connected to the first terminal (137) of the capacitor (111).

17. The DAC (100, 1001, ... 1002) according to any one of claims 11 to 16. n ), wherein the thin resistor string digital-to-analog conversion unit (122) further includes a low-ohmic thin resistor string (129), the low-ohmic thin resistor string (129) is connected in parallel with the thin resistor string (102), the resistance of the low-ohmic thin resistor string (129) is smaller than the resistance of the thin resistor string (102), and the low-ohmic thin resistor string (102) is configured to be connected to the thin multiplexer (108) when the thin multiplexer (108) is connected to the first terminal (137) of the capacitor (111).

18. The DAC (100, 1001, ... 1002) according to any one of claims 11 to 17. n ), further comprising an additional switchable resistor string (135) located between the thick resistor string (101) and the thin resistor string (102).

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