Reducing eye pattern asymmetry caused by voltage variation in clock and data recovery circuits or delay locked loops

Abstract

A data communication interface has a delay locked loop configured to generate a receive clock signal based on timing information provided by a signal received over a clock channel of a data communication link; a phase interpolator configured to provide a phase shifted clock signal by phase shifting one or more edges in the received clock signal based on timing of transitions in a data signal received over a data channel of the data communication link; a clock and data recovery circuit configured to capture data from the data signal using the phase shifted clock signal; and a calibration circuit. The calibration circuit is configured to: calibrate the delay locked loop while the clock and data recovery circuit is in an idle state; recalibrating the delay locked loop when the clock and data recovery circuit is activated; and calibrating the clock and data recovery circuit after recalibrating the delay locked loop.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. non-provisional application No. 17 / 963,970, filed on October 11, 2022, which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] The present disclosure relates generally to equalization on high speed interfaces and, more particularly, to calibration circuits provided in receivers. Background Art

[0004] Electronic device technology has exploded over the past few years. For example, better communications, hardware, larger networks, and more reliable protocols have driven the development of cellular and wireless communication technologies. Wireless service providers are now able to offer their customers an ever-expanding array of features and services, and provide users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, mobile electronic devices (e.g., cellular phones, tablet devices, laptop computers, etc.) have become more powerful and complex than ever before. Wireless devices may include high-speed bus interfaces for signal communication between hardware components.

[0005] High-speed serial buses offer advantages over parallel communication links when reduced power consumption and a smaller footprint are required, such as in integrated circuit (IC) devices. In a serial interface, a serializer is used to convert data from parallel words to a serial bit stream, and a deserializer is used to convert the data back to parallel words at the receiver. For example, a high-speed bus interface can be implemented using a peripheral component interconnect express (PCIe) bus, a universal serial bus (USB), or a serial advanced technology attachment (SATA), etc.

[0006] An IC device may include a memory interface having a physical layer circuit configured to read and write a double data rate random access memory device. The demand for higher data rates increases, requiring strict timing between circuits within the memory interface. The performance, accuracy, or reliability of the memory interface may depend on a calibration and training process that can accommodate voltage drift and other changes that may affect the operation of the memory interface. Therefore, there is a continuing need for new technologies that provide reliable training and calibration techniques for components that receive clock signals and data signals over high-speed data links. Summary of the invention

[0007] Certain aspects of the present disclosure relate to systems, devices, methods and techniques that can be used in an equalization circuit in a transmitter coupled to a serial data link. Certain aspects provide flexible configuration of the equalization circuit to achieve different operating modes. The operating mode may include high frequency, high data rate operation and low power mode, which can be configured by controlling a clock signal used to sample data from the serial data link.

[0008] In various aspects of the present disclosure, a data communication interface has a delay locked loop configured to generate a receive clock signal based on timing information provided by a signal received through a clock channel of a data communication link; a phase interpolator configured to provide a phase-shifted clock signal by phase-shifting one or more edges in the receive clock signal based on the timing of transitions in a data signal received through a data channel of the data communication link; a clock and data recovery circuit configured to capture data from the data signal using the phase-shifted clock signal; and a calibration circuit. The calibration circuit is configured to: calibrate the delay locked loop while the clock and data recovery circuit is in an idle state; recalibrate the delay locked loop when the clock and data recovery circuit is activated; and calibrate the clock and data recovery circuit after recalibrating the delay locked loop.

[0009] In various aspects of the present disclosure, an apparatus has a component for generating a receive clock signal, a component for providing a phase-shifted clock signal, a component for capturing data from a data signal, and a component for calibrating one or more circuits of the apparatus. The component for generating the receive clock signal includes a delay-locked loop that responds to timing information provided by a signal received through a clock channel of a data communication link. The component for providing the phase-shifted clock signal includes a phase interpolator that is configured to phase-shift one or more edges in the receive clock signal based on the timing of transitions in a data signal received through the data channel of the data communication link. The component for capturing data from the data signal includes a clock and data recovery circuit that responds to the phase-shifted clock signal. The component for calibrating one or more circuits of the apparatus is configured to: calibrate the delay-locked loop while the clock and data recovery circuit is in an idle state; recalibrate the delay-locked loop when the clock and data recovery circuit is activated; and calibrate the clock and data recovery circuit after recalibrating the delay-locked loop.

[0010] In various aspects of the present disclosure, a method includes: using a delay locked loop to generate a received clock signal, the delay locked loop being responsive to timing information provided by a signal received through a clock channel of a data communication link; using a phase interpolator to provide a phase-shifted clock signal, the phase interpolator being configured to phase shift one or more edges in the received clock signal based on the timing of transitions in a data signal received through a data channel of the data communication link; using a clock and data recovery circuit to capture data from the data signal, the clock and data recovery circuit being responsive to the phase-shifted clock signal; calibrating the delay locked loop while the clock and data recovery circuit is in an idle state; calibrating the delay locked loop when the clock and data recovery circuit is activated; and calibrating the clock and data recovery circuit after recalibrating the delay locked loop.

[0011] In certain aspects, the calibration circuit is further configured to: determine a first delay locked loop calibration code (DLL calibration code) when calibrating the delay locked loop while the clock and data recovery circuit is in the idle state; determine a second DLL calibration code while recalibrating the delay locked loop when the clock and data recovery circuit is activated; determine a phase interpolator code based on a difference between the first DLL calibration code and the second DLL calibration code; and configure the phase interpolator using the phase interpolator code. The calibration circuit may be further configured to: perform at least one additional recalibration of the delay locked loop; and determine that a power supply voltage has changed when the at least one additional recalibration produces a third DLL calibration that is different from the second DLL calibration code. The calibration circuit may be further configured to: determine an updated phase interpolator code based on a difference between a current DLL calibration code and an initial DLL calibration code after determining that the power supply voltage has changed; and configure the phase interpolator using the updated phase interpolator code. The current DLL calibration code and the initial DLL calibration code may be included in a DLL calibration code table that includes the first DLL calibration code and the second DLL calibration code.

[0012] In certain aspects, the calibration circuit is further configured to: determine that the data communication interface has been reconfigured; and reconfigure the delay locked loop using a current DLL calibration code selected based on an expected change in power supply voltage caused by the reconfiguration of the data communication interface. The calibration circuit may be further configured to: determine an updated phase interpolator code based on a difference between the current DLL calibration code and an initial DLL calibration code after determining that the power supply voltage has changed; and configure the phase interpolator using the updated phase interpolator code. Prior to the reconfiguration of the data communication interface, the delay locked loop may be configured with the initial DLL calibration code. The data communication link may include multiple data channels. The DLL calibration code table may map DLL calibration codes to multiple data communication link configurations. The reconfiguration of the data communication interface may cause one or more of the multiple data channels to be deactivated, or cause one or more of the multiple data channels to be activated.

[0013] In certain aspects, the calibration circuit is further configured to independently step-adjust the phase of the phase-shifted clock signal provided by the phase interpolator.The phase shifts added to the received clock signal by multiple phase interpolators may be adjusted independently of each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 An example of a system on a chip (SOC) according to certain aspects of the present disclosure is illustrated.

[0015] Figure 2 An example of a data communication system that may be adapted according to certain aspects of the present disclosure is illustrated.

[0016] Figure 3 An eye diagram generated as a superposition of signaling states for multiple bit transmissions is illustrated.

[0017] Figure 4 An example of a calibration process is illustrated in which certain changes in the supply voltage may affect the eye opening symmetry.

[0018] Figure 5 Included is an illustration of eye diagram asymmetry.

[0019] Figure 6 Calibration techniques that may be performed according to certain aspects of the present disclosure are illustrated.

[0020] Figure 7 A mapping table of DLL calibration codes maintaining various operating states for a data communications interface operating according to certain aspects of the present disclosure is illustrated.

[0021] Figure 8 An example of real-time calibration according to certain aspects of the present disclosure is illustrated.

[0022] Fig. 9 Certain aspects of a phase control circuit that may operate in accordance with certain aspects of the present disclosure are illustrated.

[0023] Fig.10 is a flow chart illustrating an example of a method for calibrating a data communication interface according to certain aspects disclosed herein. DETAILED DESCRIPTION

[0024] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configurations in which the concepts described herein may be practiced. In order to provide a thorough understanding of the various concepts, the specific embodiments include specific details. However, it is apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, in order to avoid obscuring such concepts, well-known structures and components are shown in block diagram form.

[0025] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0026] The terms "computing device" and "mobile device" are used interchangeably herein to refer to any or all of the following: servers, personal computers, smart phones, cellular phones, tablet computers, laptop computers, notebooks, ultrabooks, palmtop computers, personal data assistants (PDAs), wireless email receivers, multimedia Internet-enabled cellular phones, global positioning system (GPS) receivers, wireless game controllers, and similar personal electronic devices that include programmable processors. While various aspects are particularly useful in mobile devices (e.g., smart phones, laptop computers, etc.) with limited resources (e.g., processing power, battery, size, etc.), these aspects are generally useful in any computing device that can benefit from increased processor performance and reduced energy consumption.

[0027] The term "multi-core processor" is used herein to refer to a single integrated circuit (IC) chip or chip package that contains two or more independent processing units or cores (e.g., CPU cores, etc.) configured to read and execute program instructions. The term "multiprocessor" is used herein to refer to a system or device that includes two or more processing units configured to read and execute program instructions.

[0028] The term "system on chip" (SoC) is used herein to refer to a single integrated circuit (IC) chip that includes multiple resources and / or processors integrated on a single substrate. A single SoC may include circuits for digital, analog, mixed signal, and radio frequency functions. A single SoC may also include any number of general and / or special-purpose processors (digital signal processors (DSPs), modem processors, video processors, etc.), storage blocks (e.g., read-only memory (ROM), random access memory (RAM), flash memory, etc.), and resources (e.g., timers, voltage regulators, oscillators, etc.), any or all of which may be included in one or more cores.

[0029] The memory technologies described herein may be suitable for storing instructions, programs, control signals, and / or data for use in or by a computer or other digital electronic device. Any reference to terms and / or technical details related to individual memory types, interfaces, standards, or memory technologies is for illustrative purposes only and is not intended to limit the scope of the claims to a particular memory system or technology unless specifically stated in the claim language. The complexity of mobile computing device architectures has grown and now typically includes multiple processor cores, SoCs, coprocessors, functional modules including dedicated processors (e.g., communication modem chips, GPS receivers, etc.), complex memory systems, intricate electrical interconnects (e.g., buses and / or fabrics), and many other resources to execute complex and power-intensive software applications (e.g., video streaming applications, etc.).

[0030] Process technologies used to manufacture semiconductor devices (including IC devices) are constantly improving. Process technologies include manufacturing methods used to manufacture IC devices and define transistor size, operating voltage, and switching speed. Features that are components of circuits in IC devices may be referred to as technology nodes and / or process nodes. The terms "technology node," "process node," and "process technology" may be used to characterize a particular semiconductor manufacturing process and corresponding design rules. Faster and more efficient technology nodes are constantly being developed by using smaller feature sizes to produce smaller transistors that enable the manufacture of higher density ICs.

[0031] Certain aspects of the present disclosure are applicable to IC devices that provide an interface between core circuits and memory devices. In one example, many mobile devices employ synchronous dynamic random access memory (SDRAM), including low-power double data rate (DDR) SDRAM, which may be referred to as low-power DDR SDRAM (LPDDR SDRAM), or in some instances, LPDDRx, where x describes a technology generation of the LPDDR SDRAM. Later generations of LPDDR SDRAM are designed to operate at higher operating frequencies.

[0032] Figure 1 Example components and interconnects in a system on chip (SoC) 100 (including a memory interface / bus 126) that may be suitable for implementing certain aspects of the present disclosure are illustrated. The SoC 100 may include multiple heterogeneous processors, such as a central processing unit (CPU) 102, a modem processor 104, a graphics processor 106, and an application processor 108. Each processor 102, 104, 106, 108 may include one or more cores, and each processor / core may perform operations independently of the other processors / cores. The processors 102, 104, 106, 108 may be organized in close proximity to each other (e.g., on a single substrate, die, integrated chip, etc.), so that the processors can operate at a much higher frequency / clock rate than would be possible if the signals were propagated off-chip. The proximity of the cores may also allow for sharing of on-chip memory and resources (e.g., voltage rails), as well as allowing for more coordinated collaboration between the cores.

[0033] SoC 100 may include system components and resources 110 for managing sensor data, analog-to-digital conversion, and / or wireless data transmission, as well as for performing other specialized operations (e.g., decoding high-definition video, video processing, etc.). System components and resources 110 may also include components such as voltage regulators, oscillators, phase-locked loops (PLLs), peripheral bridges, data controllers, system controllers, access ports, timers, and / or other similar components for supporting processors and software clients running on the computing device. System components and resources 110 may also include circuits for interfacing with peripheral devices such as cameras, electronic displays, wireless communication devices, external memory chips, etc.

[0034] SoC 100 may also include a universal serial bus (USB) or other serial bus controller 112, one or more memory controllers 114, and a centralized resource manager (CRM) 116. SoC 100 may also include an input / output module (not illustrated) for communicating with resources external to the SoC, each of which may be shared by two or more of the internal SoC components.

[0035] Processors 102, 104, 106, 108 may be interconnected to USB controller 112, memory controller 114, system components and resources 110, CRM 116, and / or other system components via interconnect / bus module 122, which may include a reconfigurable logic gate array and / or implement a bus architecture. Communications may also be provided by advanced interconnects such as a high-performance network-on-chip (NoC).

[0036] The interconnect / bus module 122 may include or provide a bus master system that is configured to grant the SoC component (e.g., processor, peripheral device, etc.) exclusive control of the bus (e.g., transfer data in burst mode, block transfer mode, etc.) to achieve a set duration, number of operations, number of bytes, etc. In some cases, the interconnect / bus module 122 may implement an arbitration scheme to prevent multiple master components from attempting to drive the bus at the same time. The memory controller 114 may be a dedicated hardware module configured to manage the flow of data to and from the memory 124 via the memory interface / bus 126.

[0037] The memory controller 114 may include one or more processors configured to perform read and write operations on the memory 124. Examples of processors include microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic components, discrete hardware circuits, and other suitable hardware configured to perform various functionalities described throughout the present disclosure. In some aspects, the memory 124 may be part of the SoC 100.

[0038] Figure 2 An example of a data communication system 200 that may be adapted according to certain aspects of the present disclosure is illustrated. The data communication system 200 includes a transmitter 202, a data communication channel 210, and a receiver 222. The transmitter 202 may be disposed in a first device configured to transmit a data signal to a second device. The data communication channel 210 provides a transmission medium through which the transmitted data signal propagates from the first device to the second device. The receiver 222 is disposed in the second device and may be configured to receive and process the received data signal 234.

[0039] In one example, the transmitter 202 includes a serializer 204 configured to provide a data stream for transmission via a data communication channel 210. The transmitter 202 also includes a transmit driver 206 configured to generate a transmit data signal based on the serial data for transmission to the receiver 222 via the data communication channel 210.

[0040] The data communication channel 210 may be implemented using any type of transmission medium through which a data signal may propagate from the transmitter 202 to the receiver 222. Examples of the data communication channel 210 include one or more metallized traces on a printed circuit board (PCB) (the one or more metallized traces may include one or more vias), stripline, microstrip, coaxial cable, twisted pair, etc.

[0041] The receiver 222 includes a variable gain amplifier (VGA) (VGA / CTLE 224) with a continuous time linear equalizer (CTLE) (which can be implemented in a single stage or multiple stages), a clock data recovery circuit (CDR circuit 232), and a deserializer 226. CTLE may refer to a technique for boosting higher frequency components of a signal at a receiver so that all frequency components of the signal have similar amplitudes, thereby improving jitter and eye diagram performance. As disclosed herein, the VGA / CTLE 224 is configured to perform equalization and amplification of a received data signal. The CDR circuit 232 is configured to recover clock information associated with the data signal 234 and generate a data recovery clock signal 242, which can be used to sample or otherwise recover serial data from the data signal. The deserializer 226 is configured to convert the serial data stream back into parallel data 244.

[0042] The received data signal 234 or the received clock signal may be distorted when it reaches the receiver 222 through the data communication channel 210. Distortion may occur due to various reasons, including impedance mismatch, interference, and reflected energy in the data communication channel 210. Signal distortion may make it difficult to recover clock information and data through the CDR circuit 232, and may limit the stability window during which data can be reliably sampled. In some examples, distortion caused by high-frequency attenuation in the received data signal 234 can be addressed by the VGA / CTLE 224, which can be configured to perform equalization and amplification of the high-frequency components of the data signal 234 to increase the data rate at which the data can be transmitted through the data communication channel 210 and reliably recovered at the receiver 222. In some examples, amplification can be performed using high-speed amplifiers that are implemented using a current mode logic (CML) structure. The CML structure may also be referred to as a source coupled logic (SCL) structure.

[0043] The CDR circuit 232 may be configured to generate a data recovery clock signal 242 having an edge (transition) positioned in time within a stability window during which data can be reliably sampled. The data recovery clock signal 242 may be provided in two or more phase versions that may be used directly by a data recovery circuit (including the illustrated deserializer 226). In the illustrated example, a clock input 236 is provided to a delay locked loop (DLL 228) that provides a receiver clock signal 238. In some examples, the receiver clock signal 238 is provided as a multi-phase single-ended signal, although the receiver clock signal may alternatively be provided as a multi-phase differential signal. The receiver clock signal 238 may be used to derive the data recovery clock signal 242. In one example, the clock input 236 is a version of a clock signal received from the transmitter 202. The DLL 228 may be configured to generate a receiver clock signal 238 having a frequency different from the frequency associated with the clock input 236. For example, the DLL 228 can be configured to double or quadruple the frequency associated with the clock input 236 while maintaining correspondence between edges in the clock input 236 and edges in the receiver clock signal 238. In some implementations, a phase interpolator (PI 230) can be used to generate one or more phase-shifted receiver clock signals 240 used by the CDR circuit 232. The PI 230 can be configured to move or reposition edges in the data recovery clock signal 242 within a stability window to accommodate changes in operating conditions that may be sensitive to the effects of process, voltage, and temperature (PVT) variations.

[0044] The stability window during which data can be reliably sampled can be visualized in the eye diagram. Figure 3An eye diagram 300 generated as a superposition of signaling states for multiple bit transmissions is illustrated. Bit transmission may occur in a bit transmission interval 302, which may span a full cycle or a half cycle of a transmitter clock signal. A signal transition region 304 represents an uncertain period of time at the boundary between two symbols where variable signal rise times prevent reliable decoding. State information may be reliably determined in a region defined by an eye opening 306, which encompasses a stability window and represents a period during which signaling states are stable and bit values ​​may be reliably sampled and captured. The eye opening 306 may define an area in which midpoint crossings do not occur, and a receiver or decoder may depict a stability window within the eye opening 306. The stability window defines an area within the eye opening 306 in which signaling states can be reliably distinguished, and the stability window may be based on a minimum voltage threshold and a maximum voltage threshold. Information may be reliably sampled, demodulated, or decoded from a data signal within the stability window. The eye opening 306 may narrow along the time axis as the data rate increases, and may be compressed on the voltage axis as a function of ISI and other types of interference and distortion. When the rise time or fall time of the data signal is different, the eye opening 306 may narrow along the time axis.

[0045] The concept of periodic sampling and superimposed display of signals is useful during the design, adaptation, and configuration of systems that use clock and data recovery (CDR) circuits that use the frequent transitions that occur in the received data to recreate the received data timing signal. A communication system based on serializer / deserializer (SERDES) technology is an example of a system in which the eye opening 306 in the eye diagram 300 can be used as a basis for judging the ability to reliably recover data. An eye opening monitor (EOM) can be implemented using one or more comparators that can indicate when the voltage in a channel is sufficiently above or below a midpoint voltage to enable reliable sampling of the signal carried by the channel.

[0046] Continue to refer Figure 2 and Figure 3, the receiver 222 may be used in high-speed input / output (I / O) applications to recover timing information from an incoming clock input 236 and generate a data recovery clock signal 242 that has been phase aligned or retimed to receive and / or capture data from a received data signal 234. The data recovery clock signal 242 may be generated by phase aligning a reference clock signal generated by the DLL 228 with transitions in the incoming data. The data may be sampled at times defined by edges in the data recovery clock signal 242. In the illustrated example, the nominal ideal sampling point occurs at a time corresponding to a midpoint 312 of the eye opening 306. The eye opening 306 begins after an uncertainty period represented by the signal transition region 304. The time (t elapsed from the start of the bit transmission interval 310 may be used offset 308) and the midpoint 312 of the eye opening 306 to define the nominal ideal sampling point. The nominal ideal sampling point can also be defined as the phase offset provided in the data recovery clock signal 242.

[0047] In some instances, the transition in the data recovery clock signal 242 may occur at a time or phase offset that would result in sampling outside the eye opening 306, and errors may occur in data capture. In an ideal symmetrical eye diagram 300, the distance from the nominal ideal sampling point (which may be referred to as the CDR lock point) to the two edges of the eye opening 306 should be the same. In some instances, differences in signal rise time and signal fall time may cause eye diagram asymmetry, which may reduce the tolerance of the receiver 222 to timing jitter and may cause failures. PVT changes may affect the timing of the edges in the data recovery clock signal 242, and in some systems, voltage changes may be the main cause of CDR eye diagram asymmetry. In one example, when certain circuits transition between an idle state and an active state, the voltage of the power supply may change. When the data communication channel 210 is in use, circuits such as the CDR circuit 232 may be placed in an idle state or a sleep state to save power. For example, other circuits including the DLL 228 may also be placed in an idle state or a sleep state. Occasionally used circuits, such as calibration circuits, may be idle or dormant during most of the time that receiver 222 is enabled. As another example, the number of activities of a data communication channel and corresponding transceiver and data capture circuits may vary as channels are idle or activated.

[0048] The symmetry of the eye opening 306 may be affected by power supply voltage fluctuations that reflect changes in the number or combination of active circuits and / or communication channels. If the effects of power supply voltage fluctuations on the clock signal path and the data signal path are uneven, the symmetry of the eye opening 306 may be affected. For example, the clock signal path is typically longer than the data signal path, and when the voltage changes, the length difference may cause the phase changes of the clock signal and the data signal to be completely different.

[0049] Figure 4 An example of a calibration process 400 is illustrated in which certain changes in the power supply voltage may affect the symmetry of the eye opening associated with the communication interface in subsequent receive operations. The calibration process may be related to Figure 2 222. The illustrated supply voltage variations are attributable to the power consumed by different circuits during different stages of calibration of the clock generation circuitry in the receiver 222. Calibration may be implemented at different stages to save energy by enabling certain circuits to be idle during calibration of other circuits. For example, the CDR circuit 232 may be idle during calibration of the DLL 228, and circuits used during calibration of the DLL 228 may be idle or disabled during calibration of the CDR circuit 232.

[0050] Conventionally, the DLL 228 is the first component to be calibrated. The communication interface is in an idle state, where the power supply has a first voltage level 410. During the DLL calibration period 402, the power consumption increases causing the power supply voltage to drop to a second voltage level 412. The difference between the first voltage level 410 and the second voltage level 412 is expected to be within the specified tolerance of the power supply, and may be up to a difference of one or two percent. For example, during the calibration of the DLL 228, the voltage of the nominal 0.8 volt power supply may drop to 0.79 volts. The delay calibration loop may be used to iteratively adjust one or more delays in the DLL 228 until a target frequency is achieved. The calibration of the DLL 228 may generate a binary number (DLL code) that configures the DLL 228 to generate an output clock signal with a desired phase shift. In one example, the DLL code may configure one or more delay elements in the DLL 228. The power consumption may return to a pre-calibrated level, and the power supply voltage may return to the first voltage level 410.

[0051] After the delay or idle period, the CDR calibration period 404 begins. Power consumption increases, causing the power supply voltage to drop to a third voltage level 414. The difference between the first voltage level 410 and the third voltage level 414 is expected to be within the specified tolerance of the power supply. The third voltage level 414 may be significantly lower than the second voltage level 412 because the CDR circuit 232 typically consumes considerable power. In some implementations, the difference between the first voltage level 410 and the third voltage level 414 may be 3% or greater. For example, during calibration of the CDR circuit 232, the voltage of the nominal 0.8 volt power supply may drop to 0.75 volts. The calibration of the CDR circuit 232 may involve determining a binary number (CDR code) that causes the CDR circuit 232 to configure the timing of the edges in the data recovery clock signal 242. In one example, the CDR code may configure one or more delays or phase shifts in the PI 230 or the CDR circuit 232. In other examples, the PI configuration may be determined or used by the DLL 228 to configure the initial delay or phase shift in the PI 230. In some examples, PI 230 may be independently calibrated, at least initially.

[0052] exist Figure 4 In the example illustrated in , the CDR circuit 232 is calibrated at the third voltage level 414 using the DLL 228 that has been calibrated at the second voltage level 412. This difference between the voltages may cause the CDR eye diagram to be asymmetric.

[0053] Figure 5 An eye diagram 500 illustrating eye asymmetry is included. In the illustrated example, a bit transmission interval is shown as having an asymmetric eye opening 502 caused by a rising edge 512 that transitions more slowly than a falling edge, as can be seen from the time difference 506 between their respective crossings of a mid-voltage level 504. The timing difference of the rising and falling edges results in an eye opening 502 that is not centered around the mid-voltage level 504, nor around a midpoint 508 between the edges.

[0054] Figure 5 Also included are timing diagrams 520, 540, which illustrate examples of asymmetries that may be introduced by changes in the power supply voltage. The first timing diagram 520 illustrates a first point in time using the current voltage (V t1) calibrates the CDR, DLL, and PLL when calibrating the timing of data capture of the clock signal 524. By way of example, edges 528a-528d in the clock signal 524 are ideally positioned to capture corresponding data bits from the data signal 522. For example, edge 528b occurs at the center of the bit interval 526 and can reliably capture data in the presence of jitter affecting the leading transition 530a in the data signal 522 or the lagging transition 530b in the data signal 522.

[0055] The second timing diagram 540 illustrates that after the power supply voltage has changed to a new voltage level (V t2 ) after the data is captured. Here, when the DLL and PLL are not adjusted to the new supply voltage level (V t2 ) is calibrated for the initial voltage of the power supply (V t1 ) maintains calibration, a clock signal 544 is generated by the CDR. The data signal 542 is less affected than the clock signal 544. In the illustrated example, the data signal 542 is delayed by a duration 532 that is less than the duration 534 by which the edges 548a-548c in the clock signal 544 are delayed. The edges 548a-548c in the clock signal 524 are misaligned relative to the bit positions in the data signal 542. This misalignment of the edges 548a-548c in the clock signal 524 makes the data capture circuit more sensitive to jitter affecting the early transition 530a in the data signal 522 than to jitter affecting the late transition 530b in the data signal 522. The misalignment of the edges 548a-548c in the clock signal 524 can be viewed or observed as an asymmetric eye opening.

[0056] Certain aspects of the present disclosure relate to calibration and operation of a phase interpolator that can account for power supply voltage variations and can reduce asymmetry in the opening of a CDR eye diagram. In one aspect, a DLL delay calibration loop can be performed after an initial calibration of the DLL 228 has been completed to indicate a loss of calibration. In some examples, the loss of calibration can be attributed to a change in the power supply voltage. When the DLL delay calibration loop indicates a loss of calibration, the DLL 228 can be recalibrated by completing the delay calibration loop.

[0057] Figure 6 An example of a calibration technique 600 that may be performed in accordance with certain aspects of the present disclosure is illustrated. Figure 6 The calibration process illustrated in Figure 2222. The power supply voltage variation may be attributed to the power consumed by different circuits during different stages of calibration of the clock generation circuit in the receiver 222. By idling certain circuits during different calibration stages, energy may be saved during calibration. For example, the CDR circuit 232 may be idled during calibration of the DLL 228, and some circuits used during calibration of the DLL 228 may be idled or disabled during calibration of the CDR circuit 232.

[0058] An initial calibration of the DLL 228 is performed during the DLL calibration period 602. In the illustrated example, the CDR circuit 232 is idle or in a dormant state, and the communication interface is in an idle state, where no data is sent or received. Current from the power supply is supplied at a first voltage level 610 before the DLL calibration period 602, and drops to a second voltage level 612 when power consumption increases due to the operation of certain calibration circuits. The difference between the first voltage level 610 and the second voltage level 612 is expected to be within the specified tolerance of the power supply, and may be up to a difference of one or two percent. For example, during the calibration of the DLL 228, the voltage of a nominal 0.8 volt power supply may drop to 0.79 volts. The calibration of the DLL 228 may involve executing a DLL delay calibration loop to determine a binary number, which may be referred to herein as a DLL code, and which causes the DLL 228 to generate an output clock signal with a desired phase shift. In one example, the DLL code may configure one or more delays in the DLL 228. The power consumption may return to the pre-calibrated level and the supply voltage may return to the first voltage level 610 .

[0059] After the idle period, the CDR calibration period 604 begins. Power consumption increases, causing the power supply voltage to drop to a third voltage level 614. The difference between the first voltage level 610 and the third voltage level 614 is expected to be within the specified tolerance of the power supply. The third voltage level 614 can be significantly lower than the second voltage level 612 because the CDR circuit 232 typically consumes considerable power. In some implementations, the difference between the first voltage level 610 and the third voltage level 614 can be 3% or greater. For example, during calibration of the CDR circuit 232, the voltage of a nominal 0.8 volt power supply can drop to 0.75 volts. Calibration of the CDR circuit 232 can involve determining a binary number (CDR code) that causes the CDR circuit 232 to configure the timing of the edges in the data recovery clock signal 242. In one example, the CDR code can configure one or more delays or phase shifts in the PI 230 or the CDR circuit 232.

[0060] According to certain aspects of the present disclosure, while CDR circuit 232 is active, DLL 228 is recalibrated during DLL recalibration period 606. Initiating the DLL delay calibration loop during DLL recalibration period 606 may cause the power supply voltage to drop from third voltage level 614 to fourth voltage level 616. In some examples, the power supply voltage offset (vdiff) attributable to the DLL delay calibration loop may be DLL ) can be calculated as:

[0061] vdiff DLL =v3-v4=v1-v2, Equation 1

[0062] Wherein v1 represents a first voltage level 610 , v2 represents a second voltage level 612 , v3 represents a third voltage level 614 , and v4 represents a fourth voltage level 616 .

[0063] Recalibrating the DLL 228 at the fourth voltage level 616 may produce an indication of the magnitude of the offset required to compensate for asymmetry due to changes in the supply voltage that may occur when the CDR circuit 232 is activated. The recalibration may produce an updated DLL code. The original DLL code, the updated DLL code, and / or the difference between the DLL codes may be stored by a controller or calibration circuit provided in the communication interface.

[0064] In some implementations, a DLL delay calibration loop may be implemented to detect power changes and cause the DLL code to be updated. The update to the DLL code may enable tracking of the nominal data sampling point and may maintain a symmetrical CDR eye diagram using the DLL code stored or accessible by the controller after the power change.

[0065] According to certain aspects of the present disclosure, PI 230 may be configured to compensate for timing changes that may result in an asymmetric eye diagram. In one example, the controller may reconfigure the data communication interface in a manner that causes a change in the power supply voltage. The controller may determine a change in the phase interpolator configuration based on the value of the DLL code associated with the new data communication interface configuration and the previous data communication interface configuration.

[0066] The data communication interface may include a phase interpolator that selects the phase of an output signal by mixing two phase versions of an input signal. The phase of the output signal is selected by weighting the contribution of the two phase versions of the input signal in the output signal. For example, the phase versions of the input signal may be quadrature (I and Q) signals that are 90° phase shifted apart, and the output signal may be generated using a phase shift that may be varied at step intervals. When the I input signal is weighted at 0% and the Q input signal is weighted at 100%, the output signal may have approximately the same phase as the Q signal. The phase of the output signal may be modified by gradually adding and / or removing weights to the input.

[0067] In one aspect of the present disclosure, eye diagram symmetry may be restored by adjusting a phase interpolator using a compensating offset to change the phase of the output, wherein:

[0068] Compensation offset = α × [DLL v4 -DLL v2 Equation 2

[0069] The compensation offset may correspond to the number of steps used to adjust the phase change of the phase interpolator. In some examples, each step of phase change increases or decreases the phase by a fixed phase angle. Here, it is assumed that vdiff DLL (See Equation 1) which represents the increase in supply voltage during DLL calibration, which is negligible. That is, v 4 ≈v 3 In some examples, the term α can be characterized through simulation, empirically, and / or during system initialization.

[0070] Figure 7 An example of a mapping table 700 of DLL calibration codes 708 for various operating states of a data communication interface operating according to certain aspects of the present disclosure is illustrated. The DLL calibration code 708 codes may be maintained in a lookup table and indexed using a reference that relates each DLL calibration code 708 to a corresponding operating state. In the illustrated example, each operating state may correspond to the number of data channels in an active (on) state, the number of data channels in an inactive (off) state, a combination of active / inactive channels, or a CDR circuit in an active state. Different CDR circuits may affect the supply voltage by different amounts, and each state may be defined based on which CDR circuits are in an active state. In some implementations, the measured supply voltage may be associated with an operating state or an operating code. In some implementations, states are defined for different operating frequencies of the data communication interface or for different frequency bands in which the data communication interface may operate.

[0071] At least two fields can be used to index the illustrated mapping table 700. The state code 704 in the mapping table 700 is a refinement of the interface operation state 702 and characterizes a combination of active / inactive channels and active / inactive CDR circuits. The columns included in the interface operation state 702 are repeated with the state code 704 and may not be included in the lookup table when implemented in a physical circuit. The voltage state 706 may refer to an integer value that is assigned to a measurable voltage level and corresponds to one of the DLL calibration codes 708. In some specific implementations, the measured supply voltage or voltage range may be included as an index that can be used to select the DLL calibration code 708 or identify the voltage state 706.

[0072] The illustrated mapping table 700 relates to an example in which the operation of two channels in a data communication interface is characterized. The controller circuit can be configured to use the DLL codes listed in the mapping table 700 to determine the phase offset in real time. The illustrated mapping table 700 stores 10 DLL codes (DLL v1 ,…DLL v10 ). The compensation offset may be determined in real time according to Equation 2 and using the DLL code stored in the mapping table 700.

[0073] Figure 8 800 is a timing diagram illustrating an example of real-time calibration according to certain aspects of the present disclosure. In a first time interval 802, the physical interface of the communication link may be initialized and calibrated. The purpose of the initial calibration is to achieve CDR lock, whereby the CDR, DLL, phase interpolator, and associated circuits are configured to maximize the reliability of capturing data from each data channel of the communication link. A second time interval 804 may begin after the physical interface of the communication link has achieved CDR lock and can operate in a stable manner. When an initial CDR-PI code 812 has been determined, CDR lock may be established. The CDR-PI code 812 defines a phase shift introduced by the phase interpolator into a data recovery clock signal that is used to capture data from a data signal sent through the communication link. In one example, CDR lock is established when an edge in the data recovery clock signal appears at the center of the data eye opening, so that the communication link can operate stably and reliably.

[0074] In the illustrated timing diagram 800, the change in power supply voltage occurs at time point 808. In one example, the CDR circuit 232 is turned off and the change in power supply voltage is detected during the recalibration of the DLL 228. In another example, the change in power supply voltage is detected by a voltage measurement circuit. In other examples, the change in power supply voltage may be detected by circuits or features of the communication link physical interface, including error detection circuits or other circuits that monitor sampling clock signals and data signals. In another example, when the operating state of the communication link is reconfigured in a manner that expects a change in the power supply voltage, the controller may indicate a change in the power supply voltage. In the latter example, the reconfiguration of the operating state of the activation or deactivation of the data channel or the associated CDR circuit may result in a change in the power supply voltage.

[0075] The controller may cause the phase interpolator to be reconfigured to conform to the compensation offset or new CDR-PI code 814 determined using Equation 2. In some instances, the compensation offset or new CDR-PI code 814 may be obtained using a lookup table. In the illustrated example, the CDR-PI code is incrementally increased in a plurality of phase steps (β 810) performed within a time period 816. At the end of the adjustment, the value of the new CDR-PI code 814 is expected to be equal to the sum of the values ​​of the initial CDR-PI code 812 and β 810.

[0076] Fig. 9 Certain aspects of a phase control circuit 900 that may operate in accordance with certain aspects of the present disclosure are illustrated. The phase control circuit 900 is configured to operate after an initial calibration of the CDR, DDR, and PI 906. The phase control circuit 900 may change the configuration of a phase interpolator (PI 906) to accommodate changes in the communication link physical interface configuration or other detected asymmetries in the CDR eye opening. In one example, the PI 906 may be reconfigured to modify the phase shift applied to a signal received at its input to produce a phase-shifted output signal that may be used to capture data from a data signal sent over a data communication link.

[0077] In one aspect, the phase control circuit 900 can be configured to manage data capture in a multi-channel communication link. The phase control circuit 900 can use a lookup table (such as Figure 7 700) to perform determinations or calculations related to phase offsets. The lookup table can maintain a list of DLL calibration codes 708 for various operating states of the multi-channel communication link. In some examples, the phase control circuit 900 can cause the DLL to be reconfigured with a DLL code corresponding to a new operating state after a transition from a previous operating state has been detected or indicated.

[0078] According to various aspects of the present disclosure, the asymmetry correction circuit 908 may be configured to modify the phase shift applied by the PI 906 to the signal received at its input so as to produce its phase-shifted output signal. In one example, the asymmetry correction circuit 908 receives or accesses an initial CDR-PI code 922 and an offset value 924 (β) that controls the operation of the PI 906, the offset value representing the difference between the initial CDR-PI code 922 and the new CDR-PI code. In some implementations, the asymmetry correction circuit 908 may cause the new CDR-PI code to be written to the PI 906. In some implementations, the phase shift provided by the PI 906 is incrementally updated with a phase angle step. In these latter implementations, the asymmetry correction circuit 908 may monitor the current code value 926 used by the PI 906, while providing an update signal 914 that causes the phase angle to be increased or decreased according to a direction signal 916 that controls whether the phase angle is increased or decreased. The asymmetry correction circuit 908 can continue to modify the phase shift provided by the PI 906 until the current code value 926 is equal to the sum of the initial CDR-PI code 922 and β. In some implementations, the timing of the phase angle steps can be controlled by the clock signal 910.

[0079] According to various aspects of the present disclosure, the phase control circuit 900 may be configured to fine-tune the CDR eye opening. The fine-tuning may be implemented using timing information derived from a transition in one or more data signals received through a multi-channel communication link. The phase control circuit 900 may compare the aggregate timing of rising edges in the data signal with the aggregate timing of edges in the data signal. A comparison of the current bit value of the channel and the previous bit value 920 may indicate the occurrence of transitions and the direction of those transitions. The phase offset detector 902 is used to aggregate the transition information and use it to determine whether the rising edge or the falling edge in the clock signal will be phase shifted. In one example, the ΔΣ modulator (DSM 904) may be configured to process the edge and determine or cause the phase shift increment and the direction (± phase angle) of the phase shift increment. The update signal 914 is used to incrementally apply the phase shift to control the PI 906. The update signal 914 causes the phase angle to be increased or decreased according to the direction signal 916, which controls whether the phase angle is increased or decreased.

[0080] According to various aspects of the present disclosure, multiple phase interpolators can be used to receive data from a multi-channel communication link. In some examples, each channel of the multi-channel communication link is associated with a dedicated phase interpolator. The CDR circuit can provide a receive clock signal to control data capture of multiple deserializers. Each deserializer is coupled to a data channel of the multi-channel communication link, and the corresponding phase interpolator is used to apply a calibrated phase offset to the receive clock signal and / or fine-tune the receive clock signal based on the timing of the transition in the data signal received from the associated data channel. In some specific implementations, the phase control circuit 900 can handle the phase adjustment of multiple data channels of the multi-channel communication link. In some specific implementations, a phase control circuit 900 is provided for each data channel of the multi-channel communication link.

[0081] Fig.10 1 is a flow chart illustrating an example of a method 1000 for calibrating a data communication interface according to certain aspects disclosed herein. The method 1000 may be implemented in a receiver coupled to a data communication link. At block 1002, the receiver generates a receive clock signal using a delay locked loop, the delay locked loop responsive to timing information provided by a signal received through a clock channel of the data communication link. At block 1004, the receiver provides a phase-shifted clock signal using a phase interpolator, the phase interpolator being configured to phase shift one or more edges in the receive clock signal based on the timing of transitions in a data signal received through a data channel of the data communication link. At block 1006, the receiver captures data from the data signal using a clock and data recovery circuit, the clock and data recovery circuit responsive to the phase-shifted clock signal. At block 1008, the receiver calibrates the delay locked loop while the clock and data recovery circuit is in an idle state. At block 1010, the receiver calibrates the delay locked loop when the clock and data recovery circuit is activated. At block 1012, the receiver calibrates the clock and data recovery circuit after recalibrating the delay locked loop.

[0082] In certain implementations, when calibrating the delay locked loop while the clock and data recovery circuit is in the idle state, the receiver determines a first delay locked loop calibration code (DLL calibration code); when the clock and data recovery circuit is activated, while recalibrating the delay locked loop, the receiver determines a second DLL calibration code; the receiver determines a phase interpolator code based on a difference between the first DLL calibration code and the second DLL calibration code; and the receiver uses the phase interpolator code to configure the phase interpolator. The receiver may perform at least one additional recalibration of the delay locked loop; and when the at least one additional recalibration produces a third DLL calibration that is different from the second DLL calibration code, determine that the power supply voltage has changed. The receiver may determine an updated phase interpolator code based on a difference between a current DLL calibration code and an initial DLL calibration code after determining that the power supply voltage has changed; and configure the phase interpolator using the updated phase interpolator code. In some implementations, the current DLL calibration code and the initial DLL calibration code are included in a DLL calibration code table that includes the first DLL calibration code and the second DLL calibration code.

[0083] In some specific implementations, the receiver determines that the data communication interface has been reconfigured; and reconfigures the delay locked loop using a current DLL calibration code selected based on an expected change in power supply voltage caused by the reconfiguration of the data communication interface. The receiver may determine an updated phase interpolator code based on a difference between the current DLL calibration code and an initial DLL calibration code after determining that the power supply voltage has changed; and configure the phase interpolator using the updated phase interpolator code. Prior to the reconfiguration of the data communication interface, the delay locked loop was configured with the initial DLL calibration code. In some examples, the data communication link includes multiple data channels. The DLL calibration code table may map DLL calibration codes to multiple data communication link configurations. In some instances, the reconfiguration of the data communication interface causes one or more of the multiple data channels to be deactivated, or causes one or more of the multiple data channels to be activated.

[0084] In some implementations, the receiver is configured to independently step-adjust the phase of the phase-shifted clock signal provided by the phase interpolator.The phase shifts added to the received clock signal by multiple phase interpolators can be adjusted independently of each other.

[0085] The operation steps described in any exemplary aspects herein are described to provide examples. The described operations may be performed in many different orders other than the illustrated order. In addition, the operations described in a single operation step may actually be performed in a plurality of different steps. Additionally, one or more operation steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operation steps illustrated in the flow chart. Those skilled in the art will also understand that any one of a variety of different technologies and techniques may be used to represent information and signals. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned in the above entire description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0086] The various operations of the above method can be performed by any suitable component capable of performing the corresponding function. The component may include various hardware and / or software components and / or modules, including but not limited to circuits, application specific integrated circuits (ASICs) or processors. Generally, in the case of operations illustrated in the accompanying drawings, those operations may have corresponding corresponding components plus functional components with similar numbers. In some aspects, a device includes a component for generating a received clock signal, the component including a delay locked loop, the delay locked loop responding to the timing information provided by the signal received by the clock channel of the data communication link; a component for providing a phase-shifted clock signal, the component including a phase interpolator, the phase interpolator being configured to phase shift one or more edges in the received clock signal based on the timing of the transition in the data signal received by the data channel of the data communication link; a component for capturing data from the data signal, the component including a clock and data recovery circuit, the clock and data recovery circuit responding to the phase-shifted clock signal; and a component for calibrating one or more circuits of the device. The component for calibration can be configured to: calibrate the delay locked loop while the clock and data recovery circuit is in an idle state; recalibrate the delay locked loop when the clock and data recovery circuit is activated; and calibrate the clock and data recovery circuit after recalibrating the delay locked loop.

[0087] In some examples, the component for calibration is further configured to: determine a first DLL calibration code when calibrating the delay locked loop while the clock and data recovery circuit is in the idle state; determine a second DLL calibration code while recalibrating the delay locked loop when the clock and data recovery circuit is activated; determine a phase interpolator code based on a difference between the first DLL calibration code and the second DLL calibration code; and configure the phase interpolator using the phase interpolator code. The component for calibration may be further configured to: perform at least one additional recalibration of the delay locked loop; and determine that the power supply voltage has changed when the at least one additional recalibration produces a third DLL calibration that is different from the second DLL calibration code. The component for calibration may be further configured to: determine an updated phase interpolator code based on a difference between a current DLL calibration code and an initial DLL calibration code after determining that the power supply voltage has changed; and configure the phase interpolator using the updated phase interpolator code. The current DLL calibration code and the initial DLL calibration code may be included in a DLL calibration code table including the first DLL calibration code and the second DLL calibration code.

[0088] In some examples, the component for calibration is further configured to: determine that the data communication interface has been reconfigured; and reconfigure the delay locked loop using a current DLL calibration code selected based on an expected change in power supply voltage caused by the reconfiguration of the data communication interface. The component for calibration may be further configured to: determine an updated phase interpolator code based on a difference between the current DLL calibration code and an initial DLL calibration code after determining that the power supply voltage has changed; and configure the phase interpolator using the updated phase interpolator code. Prior to the reconfiguration of the data communication interface, the delay locked loop may be configured with the initial DLL calibration code. The data communication link may include multiple data channels. The DLL calibration code table may map DLL calibration codes to multiple data communication link configurations. The reconfiguration of the data communication interface may cause one or more of the multiple data channels to be deactivated, or may cause one or more of the multiple data channels to be activated.

[0089] In some examples, the means for calibrating is further configured to independently step-adjust the phase of the phase-shifted clock signal provided by the phase interpolator.The phase shifts added to the received clock signal by multiple phase interpolators may be adjusted independently of each other.

[0090] Some specific implementation examples are described in the following numbered clauses:

[0091] 1. A data communication interface, comprising: a delay locked loop, the delay locked loop being configured to generate a received clock signal based on timing information provided by a signal received through a clock channel of a data communication link; a phase interpolator, the phase interpolator being configured to provide a phase-shifted clock signal by phase-shifting one or more edges in the received clock signal based on the timing of transitions in a data signal received through a data channel of the data communication link; a clock and data recovery circuit, the clock and data recovery circuit being configured to capture data from the data signal using the phase-shifted clock signal; and a calibration circuit, the calibration circuit being configured to: calibrate the delay locked loop while the clock and data recovery circuit is in an idle state; recalibrate the delay locked loop when the clock and data recovery circuit is activated; and calibrate the clock and data recovery circuit after recalibrating the delay locked loop.

[0092] 2. A data communication interface according to claim 1, wherein the calibration circuit is further configured to: determine a first delay locked loop calibration code (DLL calibration code) when the delay locked loop is calibrated while the clock and data recovery circuit is in the idle state; determine a second DLL calibration code while recalibrating the delay locked loop when the clock and data recovery circuit is activated; determine a phase interpolator code based on the difference between the first DLL calibration code and the second DLL calibration code; and use the phase interpolator code to configure the phase interpolator.

[0093] 3. A data communication interface according to claim 2, wherein the calibration circuit is further configured to: perform at least one additional recalibration on the delay locked loop; and determine that the power supply voltage has changed when the at least one additional recalibration produces a third DLL calibration that is different from the second DLL calibration code.

[0094] 4. A data communication interface according to claim 3, wherein the calibration circuit is further configured to: determine an updated phase interpolator code based on a difference between a current DLL calibration code and an initial DLL calibration code after determining that the power supply voltage has changed; and configure the phase interpolator using the updated phase interpolator code.

[0095] 5. The data communication interface of clause 4, wherein the current DLL calibration code and the initial DLL calibration code are included in a DLL calibration code table that includes the first DLL calibration code and the second DLL calibration code.

[0096] 6. A data communication interface according to any one of clauses 1 to 5, wherein the calibration circuit is further configured to: determine that the data communication interface has been reconfigured; and reconfigure the delay locked loop using a current DLL calibration code selected based on an expected change in power supply voltage caused by the reconfiguration of the data communication interface.

[0097] 7. A data communication interface according to clause 6, wherein the calibration circuit is further configured to: determine an updated phase interpolator code based on a difference between the current DLL calibration code and the initial DLL calibration code after determining that the power supply voltage has changed; and configure the phase interpolator using the updated phase interpolator code, wherein the delay locked loop is configured with the initial DLL calibration code prior to the reconfiguration of the data communication interface.

[0098] 8. A data communication interface according to clause 6 or clause 7, wherein the data communication link includes multiple data channels, and the DLL calibration code table including the current DLL calibration code and the initial DLL calibration code maps the DLL calibration code to multiple data communication link configurations.

[0099] 9. A data communication interface according to clause 8, wherein reconfiguration of the data communication interface causes one or more of the plurality of data channels to be deactivated, or causes one or more of the plurality of data channels to be activated.

[0100] 10. A data communication interface according to any one of clauses 1 to 9, wherein the calibration circuit is further configured to: independently step-adjust the phase of the phase-shifted clock signal provided by the phase interpolator, wherein the phase shifts added to the received clock signal by multiple phase interpolators are adjusted independently of each other.

[0101] 11. An apparatus comprising: a component for generating a received clock signal, the component comprising a delay locked loop, the delay locked loop responsive to timing information provided by a signal received through a clock channel of a data communication link; a component for providing a phase-shifted clock signal, the component comprising a phase interpolator, the phase interpolator being configured to phase shift one or more edges in the received clock signal based on the timing of transitions in a data signal received through a data channel of the data communication link; a component for capturing data from the data signal, the component comprising a clock and data recovery circuit, the clock and data recovery circuit being responsive to the phase-shifted clock signal; and a component for calibrating one or more circuits of the apparatus, the component being configured to: calibrate the delay locked loop while the clock and data recovery circuit is in an idle state; recalibrate the delay locked loop when the clock and data recovery circuit is activated; and calibrate the clock and data recovery circuit after recalibrating the delay locked loop.

[0102] 12. An apparatus according to clause 11, wherein the component for calibration is further configured to: determine a first delay locked loop calibration code (DLL calibration code) when calibrating the delay locked loop while the clock and data recovery circuit is in the idle state; determine a second DLL calibration code while recalibrating the delay locked loop when the clock and data recovery circuit is activated; determine a phase interpolator code based on the difference between the first DLL calibration code and the second DLL calibration code; and use the phase interpolator code to configure the phase interpolator.

[0103] 13. An apparatus according to clause 12, wherein the component for calibrating is further configured to: perform at least one additional recalibration of the delay locked loop; and determine that the power supply voltage has changed when the at least one additional recalibration produces a third DLL calibration different from the second DLL calibration code.

[0104] 14. An apparatus according to clause 13, wherein the component for calibration is further configured to: determine an updated phase interpolator code based on a difference between a current DLL calibration code and an initial DLL calibration code after determining that the power supply voltage has changed; and configure the phase interpolator using the updated phase interpolator code.

[0105] 15. The apparatus of clause 14, wherein the current DLL calibration code and the initial DLL calibration code are included in a DLL calibration code table that includes the first DLL calibration code and the second DLL calibration code.

[0106] 16. An apparatus according to any one of clauses 11 to 15, wherein the component for calibration is further configured to: determine that the data communication interface has been reconfigured; and reconfigure the delay locked loop using a current DLL calibration code selected based on an expected change in power supply voltage caused by the reconfiguration of the data communication interface.

[0107] 17. An apparatus according to clause 16, wherein the component for calibration is further configured to: determine an updated phase interpolator code based on a difference between the current DLL calibration code and an initial DLL calibration code after determining that the power supply voltage has changed; and configure the phase interpolator using the updated phase interpolator code, wherein the delay locked loop is configured with the initial DLL calibration code prior to the reconfiguration of the data communication interface.

[0108] 18. An apparatus as recited in clause 16 or clause 17, wherein the data communications link comprises a plurality of data channels, and a DLL calibration code table including the current DLL calibration code and the initial DLL calibration code maps DLL calibration codes to a plurality of data communications link configurations.

[0109] 19. An apparatus according to clause 18, wherein reconfiguration of the data communication interface causes one or more of the plurality of data channels to be deactivated, or causes one or more of the plurality of data channels to be activated.

[0110] 20. An apparatus according to any one of clauses 11 to 19, wherein the component for calibration is further configured to: independently step-adjust the phase of the phase-shifted clock signal provided by the phase interpolator, wherein the phase shifts added to the received clock signal by multiple phase interpolators are adjusted independently of each other.

[0111] 21. A method for calibrating a data communication interface, the method comprising: using a delay-locked loop to generate a received clock signal, the delay-locked loop responding to timing information provided by a signal received through a clock channel of a data communication link; using a phase interpolator to provide a phase-shifted clock signal, the phase interpolator being configured to phase-shift one or more edges in the received clock signal based on the timing of transitions in a data signal received through a data channel of the data communication link; using a clock and data recovery circuit to capture data from the data signal, the clock and data recovery circuit responding to the phase-shifted clock signal; calibrating the delay-locked loop while the clock and data recovery circuit is in an idle state; calibrating the delay-locked loop when the clock and data recovery circuit is activated; and calibrating the clock and data recovery circuit after recalibrating the delay-locked loop.

[0112] 22. The method according to clause 21 further comprises: determining a first delay locked loop calibration code (DLL calibration code) when calibrating the delay locked loop while the clock and data recovery circuit is in the idle state; determining a second DLL calibration code while recalibrating the delay locked loop when the clock and data recovery circuit is activated; determining a phase interpolator code based on the difference between the first DLL calibration code and the second DLL calibration code; and configuring the phase interpolator using the phase interpolator code.

[0113] 23. The method of clause 22, further comprising: performing at least one additional recalibration of the delay locked loop; and determining that a power supply voltage has changed when the at least one additional recalibration produces a third DLL calibration that is different from the second DLL calibration code.

[0114] 24. The method of clause 23, further comprising: after determining that the power supply voltage has changed, determining an updated phase interpolator code based on a difference between a current DLL calibration code and an initial DLL calibration code; and configuring the phase interpolator using the updated phase interpolator code.

[0115] 25. The method of clause 24, wherein the current DLL calibration code and the initial DLL calibration code are included in a DLL calibration code table that includes the first DLL calibration code and the second DLL calibration code.

[0116] 26. A method according to any one of clauses 21 to 25, the method further comprising: determining that the data communication interface has been reconfigured; and reconfiguring the delay locked loop using a current DLL calibration code selected based on an expected change in power supply voltage caused by the reconfiguration of the data communication interface.

[0117] 27. The method according to clause 26 further includes: after determining that the power supply voltage has changed, determining an updated phase interpolator code based on the difference between the current DLL calibration code and the initial DLL calibration code; and configuring the phase interpolator using the updated phase interpolator code, wherein the delay locked loop is configured with the initial DLL calibration code prior to the reconfiguration of the data communication interface.

[0118] 28. The method of clause 26 or clause 27, wherein the data communication link comprises a plurality of data channels, and the DLL calibration code table including the current DLL calibration code and the initial DLL calibration code maps DLL calibration codes to a plurality of data communication link configurations.

[0119] 29. The method of clause 28, wherein reconfiguration of the data communications interface causes one or more of the plurality of data channels to be deactivated, or causes one or more of the plurality of data channels to be activated.

[0120] 30. A method according to any one of clauses 21 to 29, further comprising independently stepping the phase of the phase-shifted clock signal provided by the phase interpolator, wherein the phase shifts added to the received clock signal by multiple phase interpolators are adjusted independently of each other.

[0121] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items (including single members). For example, "at least one of a, b, or c" is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c).

[0122] The present disclosure is provided to enable any person skilled in the art to make or use the various aspects of the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples and designs described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data communication interface, comprising: a delay locked loop configured to generate a receive clock signal based on timing information provided by a signal received through a clock channel of the data communications link; a phase interpolator configured to provide a phase-shifted clock signal by phase-shifting one or more edges in the received clock signal based on the timing of transitions in a data signal received over a data channel of the data communications link; a clock and data recovery circuit configured to capture data from the data signal using the phase-shifted clock signal; and A calibration circuit, the calibration circuit being configured to: calibrating the delay locked loop while the clock and data recovery circuit is in an idle state; recalibrating the delay locked loop when the clock and data recovery circuit is activated; as well as After recalibrating the delay locked loop, the clock and data recovery circuit is calibrated.

2. The data communication interface of claim 1 , wherein the calibration circuit is further configured to: determining a first delay locked loop calibration code (DLL calibration code) when calibrating the delay locked loop while the clock and data recovery circuit is in the idle state; determining a second DLL calibration code while recalibrating the delay locked loop when the clock and data recovery circuit is activated; determining a phase interpolator code based on a difference between the first DLL calibration code and the second DLL calibration code; as well as The phase interpolator is configured using the phase interpolator code.

3. The data communication interface of claim 2, wherein the calibration circuit is further configured to: performing at least one additional recalibration of the delay locked loop; and When the at least one additional recalibration produces a third DLL calibration that is different than the second DLL calibration code, it is determined that the supply voltage has changed.

4. The data communication interface of claim 3, wherein the calibration circuit is further configured to: After determining that the power supply voltage has changed, determining an updated phase interpolator code based on a difference between a current DLL calibration code and an initial DLL calibration code; and The phase interpolator is configured using the updated phase interpolator code. 5 . The data communication interface of claim 4 , wherein the current DLL calibration code and the initial DLL calibration code are included in a DLL calibration code table including the first DLL calibration code and the second DLL calibration code.

6. The data communication interface of claim 1 , wherein the calibration circuit is further configured to: determining that the data communications interface has been reconfigured; and The delay locked loop is reconfigured using a current DLL calibration code selected based on an expected change in supply voltage caused by the reconfiguration of the data communications interface.

7. The data communication interface of claim 6, wherein the calibration circuit is further configured to: After determining that the power supply voltage has changed, determining an updated phase interpolator code based on a difference between the current DLL calibration code and an initial DLL calibration code; and configuring the phase interpolator using the updated phase interpolator code, Wherein prior to said reconfiguration of said data communication interface, said delay locked loop is configured with said initial DLL calibration code.

8. The data communication interface of claim 7, wherein the data communication link comprises a plurality of data channels, and the DLL calibration code table including the current DLL calibration code and the initial DLL calibration code maps DLL calibration codes to a plurality of data communication link configurations.

9. The data communication interface of claim 8, wherein reconfiguration of the data communication interface causes one or more of the plurality of data channels to be deactivated, or causes one or more of the plurality of data channels to be activated.

10. The data communication interface of claim 1, wherein the calibration circuit is further configured to: The phases of the phase-shifted clock signals provided by the phase interpolators are independently step-adjusted, wherein the phase shifts added to the received clock signal by a plurality of phase interpolators are adjusted independently of one another.

11. A device, comprising: means for generating a receive clock signal, the means comprising a delay locked loop responsive to timing information provided by a signal received via a clock channel of a data communications link; means for providing a phase-shifted clock signal, the means comprising a phase interpolator configured to phase shift one or more edges in the received clock signal based on the timing of transitions in a data signal received over a data channel of the data communications link; means for capturing data from said data signal, said means comprising a clock and data recovery circuit responsive to said phase-shifted clock signal; and Means for calibrating one or more circuits of the apparatus, the means being configured to: calibrating the delay locked loop while the clock and data recovery circuit is in an idle state; recalibrating the delay locked loop when the clock and data recovery circuit is activated; as well as After recalibrating the delay locked loop, the clock and data recovery circuit is calibrated.

12. The apparatus of claim 11, wherein the means for calibrating is further configured to: determining a first delay locked loop calibration code (DLL calibration code) when calibrating the delay locked loop while the clock and data recovery circuit is in the idle state; determining a second DLL calibration code while recalibrating the delay locked loop when the clock and data recovery circuit is activated; determining a phase interpolator code based on a difference between the first DLL calibration code and the second DLL calibration code; as well as The phase interpolator is configured using the phase interpolator code.

13. The apparatus of claim 12, wherein the means for calibrating is further configured to: performing at least one additional recalibration of the delay locked loop; and When the at least one additional recalibration produces a third DLL calibration that is different than the second DLL calibration code, it is determined that the supply voltage has changed.

14. The apparatus of claim 13, wherein the means for calibrating is further configured to: After determining that the power supply voltage has changed, determining an updated phase interpolator code based on a difference between a current DLL calibration code and an initial DLL calibration code; and The phase interpolator is configured using the updated phase interpolator code. 15 . The apparatus of claim 14 , wherein the current DLL calibration code and the initial DLL calibration code are included in a DLL calibration code table including the first DLL calibration code and the second DLL calibration code.

16. The apparatus of claim 11, wherein the means for calibrating is further configured to: determining that the device has been reconfigured; and The delay locked loop is reconfigured using a current DLL calibration code selected based on an expected change in supply voltage caused by the reconfiguration of the device.

17. The apparatus of claim 16, wherein the means for calibrating is further configured to: After determining that the power supply voltage has changed, determining an updated phase interpolator code based on a difference between the current DLL calibration code and an initial DLL calibration code; and configuring the phase interpolator using the updated phase interpolator code, Wherein prior to said reconfiguration of said apparatus, said delay locked loop is configured with said initial DLL calibration code.

18. The apparatus of claim 17, wherein the data communication link comprises a plurality of data channels, and wherein the DLL calibration code table including the current DLL calibration code and the initial DLL calibration code maps DLL calibration codes to a plurality of data communication link configurations.

19. The apparatus according to claim 18, wherein the reconfiguration of the apparatus causes one or more data channels of the plurality of data channels to be deactivated, or causes one or more data channels of the plurality of data channels to be activated.

20. The apparatus of claim 11, wherein the means for calibrating is further configured to: The phases of the phase-shifted clock signals provided by the phase interpolators are independently step-adjusted, wherein the phase shifts added to the received clock signal by a plurality of phase interpolators are adjusted independently of one another.

21. A method for calibrating a data communication interface, the method comprising: generating a receive clock signal using a delay locked loop responsive to timing information provided by a signal received over a clock channel of the data communications link; providing a phase-shifted clock signal using a phase interpolator configured to phase shift one or more edges in the received clock signal based on the timing of transitions in a data signal received over a data channel of the data communications link; capturing data from the data signal using a clock and data recovery circuit, the clock and data recovery circuit being responsive to the phase-shifted clock signal; calibrating the delay locked loop while the clock and data recovery circuit is in an idle state; calibrating the delay locked loop when the clock and data recovery circuit is activated; as well as After recalibrating the delay locked loop, the clock and data recovery circuit is calibrated.

22. The method according to claim 21, further comprising: determining a first delay locked loop calibration code (DLL calibration code) when calibrating the delay locked loop while the clock and data recovery circuit is in the idle state; determining a second DLL calibration code while recalibrating the delay locked loop when the clock and data recovery circuit is activated; determining a phase interpolator code based on a difference between the first DLL calibration code and the second DLL calibration code; as well as The phase interpolator is configured using the phase interpolator code.

23. The method according to claim 22, further comprising: performing at least one additional recalibration of the delay locked loop; as well as When the at least one additional recalibration produces a third DLL calibration that is different than the second DLL calibration code, it is determined that the supply voltage has changed.

24. The method according to claim 23, further comprising: determining an updated phase interpolator code based on a difference between a current DLL calibration code and an initial DLL calibration code after determining that the power supply voltage has changed; as well as The phase interpolator is configured using the updated phase interpolator code. 25 . The method of claim 24 , wherein the current DLL calibration code and the initial DLL calibration code are included in a DLL calibration code table including the first DLL calibration code and the second DLL calibration code.

26. The method according to claim 21, further comprising: determining that the data communication interface has been reconfigured; as well as The delay locked loop is reconfigured using a current DLL calibration code selected based on an expected change in supply voltage caused by the reconfiguration of the data communications interface.

27. The method according to claim 26, further comprising: determining an updated phase interpolator code based on a difference between the current DLL calibration code and an initial DLL calibration code after determining that the power supply voltage has changed; as well as configuring the phase interpolator using the updated phase interpolator code, Wherein prior to said reconfiguration of said data communication interface, said delay locked loop is configured with said initial DLL calibration code.

28. The method of claim 27, wherein the data communication link comprises a plurality of data channels, and wherein a DLL calibration code table including the current DLL calibration code and the initial DLL calibration code maps DLL calibration codes to a plurality of data communication link configurations.

29. The method of claim 28, wherein the reconfiguration of the data communication interface causes one or more of the plurality of data channels to be deactivated, or causes one or more of the plurality of data channels to be activated.

30. The method of claim 21, further comprising: The phases of the phase-shifted clock signals provided by the phase interpolators are independently step-adjusted, wherein the phase shifts added to the received clock signal by a plurality of phase interpolators are adjusted independently of one another.

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