Arker chip wake-up circuit, method, device, medium, product and chip

Abstract

The invention discloses an EArker chip awakening circuit, method and device, a medium, a product and a chip, and relates to the technical field of integrated circuits, the circuit comprises a BMC receiving circuit, a BMC edge detection circuit, an Emaker dormancy control circuit and an EArker chip, the input end of the BMC receiving circuit is connected with a CC channel, the output end of the BMC receiving circuit is connected with the input end of the BMC edge detection circuit, and the BMC edge detection circuit is connected with the Emaker dormancy control circuit. The output end of the BMC edge detection circuit is connected with the input end of the Emaker dormancy control circuit; the BMC receiving circuit is used for converting an analog BMC signal input by a CC channel into a digital signal; the BMC edge detection circuit is used for analyzing the digital signal to judge whether PD communication exists in the CC channel or not so as to obtain a judgment result; the Emaker dormancy control circuit is used for starting a clock signal of the EMarker chip when the judgment result shows that PD communication exists in the CC channel, so that the EMarker chip responds to a PD message transmitted through the CC channel, extra power consumption of the EMarker chip can be reduced, and therefore the use experience of a user is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an EMarker chip wake-up circuit, method, device, medium, product and chip. Background Art

[0002] With the rapid development of modern electronic technology, the USB Type-C interface has become the mainstream interface standard for many electronic devices due to its advantages such as reversible pluggability, support for high-power charging and high-speed data transmission. Under this technical framework, the EMaker chip, as the core component of the Type-C cable, plays a vital role. The EMaker chip can not only store key information of the cable, such as manufacturer ID, maximum current supported and communication rate, but also interact with the connected device through the USB PD (Power Delivery) protocol to achieve intelligent identification and configuration optimization.

[0003] Especially in some high-end or special application scenarios, the design of Type-C cables is more complex, and multiple EMaker chips may be configured to meet different functional requirements. For example, configuring EMaker chips at both ends of the cable can monitor the temperature of the devices at both ends in real time, and actively cut off the connection when the temperature is abnormal, thereby effectively ensuring the safe operation of the equipment. Although this design improves the intelligence level of the cable, it also puts higher requirements on the power consumption management of the EMaker chip.

[0004] However, it is worth noting that the Type-C cable itself does not have the power supply capability, and the working energy of the EMaker chip inside it needs to be provided by the Type-C devices connected at both ends of the cable. When connecting power banks, mobile phones and other devices that are sensitive to power consumption, the extra power consumption of the EMaker chip will directly lead to a reduction in the battery life of the device, thus affecting the user experience. Summary of the invention

[0005] The purpose of this application is to provide an EMarker chip wake-up circuit, method, device, medium, product and chip, which can reduce the additional power consumption of the EMaker chip and thus improve the user experience.

[0006] To achieve the above objectives, this application provides the following solutions:

[0007] In the first aspect, the present application provides an EMarker chip wake-up circuit, which includes a BMC receiving circuit, a BMC edge detection circuit, an Emaker sleep control circuit and an EMarker chip, wherein the input end of the BMC receiving circuit is connected to the CC channel of the Type-C cable, the output end of the BMC receiving circuit is connected to the input end of the BMC edge detection circuit, the output end of the BMC edge detection circuit is connected to the input end of the Emaker sleep control circuit, and the output end of the Emaker sleep control circuit is connected to the EMarker chip, wherein:

[0008] The BMC receiving circuit is used to convert the analog BMC signal input by the CC channel into a digital signal;

[0009] The BMC edge detection circuit is used to determine whether there is PD communication in the CC channel by analyzing the digital signal to obtain a determination result;

[0010] The Emaker sleep control circuit is used to turn on the clock signal of the EMarker chip when the judgment result indicates that the PD communication exists in the CC channel, so that the EMarker chip responds to the PD message transmitted through the CC channel.

[0011] Optionally, the BMC receiving circuit includes a comparator, a Schmitt trigger and a first inverter, wherein:

[0012] The comparator is used to compare the voltage of the analog BMC signal input by the CC channel with the reference voltage to obtain a comparison result, and output a first level matching the comparison result;

[0013] The Schmitt trigger is used to input the first level to the first inverter;

[0014] The first inverter is used to invert the first level to obtain a second level, and output the second level as a digital signal.

[0015] Optionally, the BMC receiving circuit includes a second inverter, a third inverter, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, wherein:

[0016] The input end of the second inverter is connected to the CC channel of the Type-C cable, and the output end of the second inverter is connected to the input end of the third inverter and the gate of the second NMOS tube;

[0017] The output end of the third inverter is connected to the gate of the first NMOS tube;

[0018] The source of the first NMOS tube is connected to a source power supply voltage, and the drain of the first NMOS tube is connected to the source of the first PMOS tube and the gate of the second PMOS tube;

[0019] The source of the second NMOS tube is connected to the source power supply voltage, and the drain of the second NMOS tube is connected to the source of the second PMOS tube and the gate of the first PMOS tube;

[0020] The drain of the first PMOS tube and the drain of the second PMOS tube are connected to a power source.

[0021] Optionally, the digital signal is an asynchronous digital signal, and the BMC edge detection circuit determines whether there is PD communication in the CC channel by parsing the digital signal, and the determination result is obtained in the following manner:

[0022] Synchronizing the asynchronous digital signal to obtain a synchronous digital signal;

[0023] Delaying the synchronous digital signal to obtain a delayed digital signal;

[0024] Performing edge recognition on the synchronous digital signal and the delayed digital signal to obtain an edge recognition result; wherein the edge recognition result indicates that an edge event occurs on the synchronous digital signal;

[0025] Obtaining the total number of occurrences of the edge event within a preset time period;

[0026] If the total number of times reaches the preset number of times, it is determined that there is PD communication in the CC channel.

[0027] Optionally, the Emaker sleep control circuit includes a second 4-bit counter, a third 4-bit counter, a fourth 4-bit counter, a fifth 4-bit counter, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, a ninth AND gate, a tenth AND gate, a fourth inverter, a fourth trigger, a first crystal oscillator and a first clock gating unit, wherein:

[0028] The second 4-bit counter, the third 4-bit counter, the fourth 4-bit counter, the fifth 4-bit counter, the sixth AND gate, the seventh AND gate, the eighth AND gate, the ninth AND gate, the tenth AND gate and the fourth trigger are used to send an enable signal to the first clock gating unit when the judgment result indicates that the PD communication exists in the CC channel;

[0029] The first crystal oscillator is used to send a crystal oscillator signal to the first clock gating unit;

[0030] The first clock gating unit is used to connect the crystal oscillator signal with the clock signal output by the first clock gating unit when receiving the start signal; wherein the clock signal is used to provide a clock for the operation of the EMarker chip;

[0031] The fourth inverter, the second 4-bit counter, the third 4-bit counter, the fourth 4-bit counter, the fifth 4-bit counter, the third AND gate, the fourth AND gate and the fifth AND gate are used to control the connection duration between the crystal oscillator signal and the clock signal; the connection duration is a preset connection duration.

[0032] Optionally, the Emaker sleep control circuit includes a fifth trigger, a sixth trigger, a multiplexer, a second crystal oscillator, a second clock gating unit, a fifth inverter and a NAND gate, wherein:

[0033] The output end of the multiplexer is connected to the input end D of the fifth trigger, the input end 0 of the multiplexer is connected to the BMC edge detection circuit, the input end 1 of the multiplexer is connected to the output end of the NAND gate, and the selection end S0 of the multiplexer is connected to the output end Q of the fifth trigger;

[0034] The output terminal Q of the fifth trigger is also connected to the enable terminal of the second clock gating unit;

[0035] The input end of the second clock gating unit is connected to the output end of the second crystal oscillator, and the output end of the second clock gating unit is connected to the input end of the EMaker chip;

[0036] The input terminal D of the sixth trigger is connected to the output terminal of the EMaker chip, and the output terminal Q of the sixth trigger is connected to an input terminal of the NAND gate;

[0037] The input end of the fifth inverter is connected to the output end of the EMaker chip, and the output end of the fifth inverter is connected to another input end of the NAND gate.

[0038] In a second aspect, the present application provides an EMarker chip wake-up method, which is applied to the EMarker chip wake-up circuit in the first aspect, and the EMarker chip wake-up method includes:

[0039] Convert the analog BMC signal input by CC channel into digital signal;

[0040] Synchronizing the digital signal to obtain a synchronized digital signal;

[0041] Delaying the synchronous digital signal to obtain a delayed digital signal;

[0042] Based on the synchronous digital signal and the delayed digital signal, obtaining the total number of edge events occurring within a preset time period;

[0043] If the total number of times reaches the preset number of times, it is determined that there is PD communication in the CC channel, and the clock signal of the EMarker chip is turned on to enable the EMarker chip to respond to the PD message transmitted through the CC channel.

[0044] In a third aspect, the present application provides a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the EMarker chip wake-up method described above.

[0045] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-mentioned EMarker chip wake-up method.

[0046] In a fifth aspect, the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the above-mentioned EMarker chip wake-up method.

[0047] In a sixth aspect, the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction. When the processor executes the program or instruction, the steps of the EMarker chip wake-up method described above are implemented.

[0048] According to the specific embodiments provided in this application, this application discloses the following technical effects:

[0049] The present application provides an EMarker chip wake-up circuit, method, device, medium, product and chip. The analog BMC signal is converted into a digital signal through a BMC receiving circuit, and the digital signal is analyzed through a BMC edge detection circuit to analyze whether there is PD communication in the CC channel. If it is determined that there is PD communication in the CC channel, the dormant EMaker chip can be awakened by the Emaker sleep control circuit at this time, so that the EMarker chip responds to the PD message transmitted through the CC channel, so that the EMarker chip can be in a dormant state in the absence of PD communication. When PD communication is detected, the EMarker chip is awakened. It can be seen that this method can reduce the extra power consumption of the EMaker chip, thereby improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 This is a structural diagram of an EMarker chip wake-up circuit in an embodiment of the present application;

[0052] Figure 2 A schematic diagram of the structure of a BMC receiving circuit provided in one embodiment of the present application;

[0053] Figure 3 A schematic diagram of the structure of another BMC receiving circuit provided in an embodiment of the present application;

[0054] Figure 4 A schematic diagram of the structure of a BMC edge detection circuit provided in one embodiment of the present application;

[0055] Figure 5 A schematic diagram of the structure of an Emaker sleep control circuit provided in one embodiment of the present application;

[0056] Figure 6 A schematic diagram of the structure of another Emaker sleep control circuit provided in an embodiment of the present application;

[0057] Figure 7 A flowchart of an EMarker chip wake-up method provided in one embodiment of the present application.

[0058] Figure 8 A schematic diagram of the structure of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0059] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0060] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0061] In an exemplary embodiment, Figure 1As shown, an EMarker chip wake-up circuit is provided, and the EMarker chip wake-up circuit includes a BMC (Biphase Mark Coding) receiving circuit, a BMC edge detection circuit, an Emaker sleep control circuit and an EMarker chip. The input end of the BMC receiving circuit is connected to the CC channel of the Type-C cable, the output end of the BMC receiving circuit is connected to the input end of the BMC edge detection circuit, the output end of the BMC edge detection circuit is connected to the input end of the Emaker sleep control circuit, and the output end of the Emaker sleep control circuit is connected to the EMarker chip.

[0062] In the embodiment of the present application, the BMC receiving circuit may convert the analog BMC signal transmitted on the CC channel into a digital signal that can be processed by the digital circuit;

[0063] The BMC edge detection circuit can analyze the digital signal output by the BMC receiving circuit, and then determine whether there is PD communication in the CC channel.

[0064] In the embodiment of the present application, the method for determining whether there is PD communication in the CC channel may be:

[0065] The number of edges of the BMC waveform simulating the BMC signal within a period of time is counted. If the number of edges of the BMC waveform within a period of time is greater than the specified number, it is considered that PD communication exists in the CC channel.

[0066] For the BMC edge detection circuit, when the number of edges within a period of time is greater than the specified number, the confirmation signal (bmc_edge_max_flag) will be set to 1 to notify the EMaker sleep control circuit that PD communication may exist.

[0067] After detecting that the confirmation signal is 1, the EMaker sleep control circuit will turn on the clock signal of the EMaker chip, so that the EMaker chip can respond normally to the PD message that may come.

[0068] When no PD message is detected for a period of time (the confirmation signal always remains at a low level), the EMaker sleep control circuit will turn off the clock signal of the EMaker chip, causing the EMaker chip to enter a sleep state. Since the clock source of the EMaker chip is turned off, the dynamic power consumption of the EMaker chip will be significantly reduced compared to when the clock is turned on.

[0069] In the embodiment of the present application, the PD communication protocol uses the BMC encoding method to encode the data to be transmitted.

[0070] Please also read Figure 2 , Figure 2 Schematic diagram of a BMC receiving circuit; the BMC receiving circuit includes a comparator CMP1, a Schmitt trigger U1 and a first inverter INV1, wherein:

[0071] The comparator CMP1 is used to compare the voltage of the analog BMC signal input by the CC channel with the reference voltage to obtain a comparison result, and output a first level matching the comparison result;

[0072] The Schmitt trigger U1 is used to input the first level to the first inverter INV1;

[0073] The first inverter INV1 is used for inverting the first level to obtain a second level, and outputting the second level as a digital signal.

[0074] The positive input terminal of the comparator CMP1 is connected to the reference voltage Vref, the negative input terminal of the comparator CMP1 is connected to the CC channel of the Type-C cable, and the output terminal of the comparator CMP1 is connected to the input terminal of the Schmitt trigger U1;

[0075] The input end of the first inverter INV1 is connected to the output end of the Schmitt trigger U1 , and the output end of the first inverter INV1 is connected to the input end of the BMC edge detection circuit.

[0076] In the embodiment of the present application, the data signal outputted from the output end of the first inverter INV1 may be a digital signal (rxdata).

[0077] In the embodiment of the present application, by referring to the Type-C protocol and PD protocol specifications, it can be known that the EMaker chip and other devices use the PD protocol for communication, and the encoding method used for the transmission of the PD protocol on the CC channel is BMC encoding.

[0078] When there is no PD communication, the voltage level on the CC channel is approximately 1.68V or 0.92V (determined by the Type-C devices at both ends of the cable).

[0079] When PD communication starts on the CC channel, the high level of the BMC waveform is approximately 1.125V and the low level is approximately 0V.

[0080] In order to wake up the EMaker chip in time to respond when an external device accesses the EMaker chip, it is necessary to identify and analyze the BMC waveform.

[0081] When the operating voltage of the digital circuit is 5V, if the BMC high level on the CC channel is directly sent to the digital circuit without conversion, it will be regarded as the low level of the digital circuit. Figure 2 The circuit shown converts the analog BMC signal present on the CC channel into a digital signal so as to be further processed by the subsequent digital circuit.

[0082] from Figure 2 It can be seen that in this embodiment, the comparator CMP1 and the reference voltage Vref (the reference voltage value here can be 1.125V / 2=0.56V) are used to convert the CC level.

[0083] When the digital signal (i.e., the second level) output by the first inverter INV1 is a high level of the digital circuit, the first level output by the Schmitt trigger U1 is a low level, and the first level output by the comparator CMP1 is a low level. This means that the voltage on the negative input terminal of the comparator (CC channel of the Type-C cable) is greater than the voltage on the positive input terminal (0.56V reference voltage), and at this time, it is considered that the CC channel has BMC data high level (BMC high level 1.125V) or no data transmission (CC channel level is 1.68V or 0.92V when there is no PD communication).

[0084] When the digital signal output by the first inverter INV1 is a low level of the digital circuit, the first level output by the Schmitt trigger U1 is a high level, and the first level output by the comparator CMP1 is a high level. This means that the voltage on the negative input terminal of the comparator (CC channel of the Type-C cable) is less than the voltage on the positive input terminal (0.56V reference voltage), and at this time, it is considered that the CC channel has a low level of BMC data.

[0085] From the above analysis, it can be seen that the BMC receiving circuit in this embodiment converts the voltage on the CC channel that is greater than the reference voltage Vref into a high level of the digital circuit, and converts the voltage on the CC channel that is less than the reference voltage Vref into a low level of the digital circuit, and finally sends the converted result to the BMC edge detection circuit for further analysis.

[0086] Please also read Figure 3 , Figure 3 : is a structural diagram of another BMC receiving circuit; the BMC receiving circuit includes a second inverter INV2, a third inverter INV3, a first PMOS tube Q1, a second PMOS tube Q2, a first NMOS tube Q3 and a second NMOS tube Q4, wherein:

[0087] The input end of the second inverter INV2 is connected to the CC channel of the Type-C cable, and the output end of the second inverter INV2 is connected to the input end of the third inverter INV3 and the gate of the second NMOS tube Q4;

[0088] The output end of the third inverter INV3 is connected to the gate of the first NMOS transistor Q3;

[0089] The source of the first NMOS transistor Q3 is connected to the source power supply voltage Vss, and the drain of the first NMOS transistor Q3 is connected to the source of the first PMOS transistor Q1 and the gate of the second PMOS transistor Q2;

[0090] The source of the second NMOS transistor Q4 is connected to the source power supply voltage Vss, and the drain of the second NMOS transistor Q4 is connected to the source of the second PMOS transistor Q2 and the gate of the first PMOS transistor Q1;

[0091] The drain of the first PMOS transistor Q1 and the drain of the second PMOS transistor Q2 are connected to a power source Vdd.

[0092] In the embodiment of the present application, the operating voltage of the second inverter INV2 and the third inverter INV3 may be 1.8V, and the voltage of the power supply Vdd may be 5V.

[0093] Figure 3 In the embodiment, when CC level is low, the second inverter INV2 outputs high level, and the third inverter INV3 outputs low level, so the second NMOS tube Q4 is turned on, the first NMOS tube Q3 is turned off, the first PMOS tube Q1 is turned on, and the second PMOS tube Q2 is turned off. Thus, the digital signal is connected to Vss, that is, the digital signal outputs the low level of the digital circuit at this time.

[0094] When CC is high, the second inverter INV2 outputs a low level, and the third inverter INV3 outputs a high level, so the second NMOS transistor Q4 is turned off, the first NMOS transistor Q3 is turned on, the second PMOS transistor Q2 is turned on, and the first PMOS transistor Q1 is turned off. At this time, the digital signal is connected to Vdd, that is, the digital signal outputs a high level of the digital circuit.

[0095] Through the above analysis, we can know that Figure 3 and Figure 2 Although the BMC receiving circuits shown have different circuit structures, the final effects achieved are basically the same, that is, they all convert the analog BMC waveform on the CC channel into a digital signal that can be processed by the digital circuit.

[0096] The BMC edge detection circuit is used to determine whether there is PD communication in the CC channel by analyzing the digital signal to obtain a determination result.

[0097] In the embodiment of the present application, the digital signal is an asynchronous digital signal. The BMC edge detection circuit analyzes the digital signal to determine whether there is PD communication in the CC channel. The determination result is obtained in the following manner:

[0098] Synchronizing the asynchronous digital signal to obtain a synchronous digital signal;

[0099] Delaying the synchronous digital signal to obtain a delayed digital signal;

[0100] Performing edge recognition on the synchronous digital signal and the delayed digital signal to obtain an edge recognition result; wherein the edge recognition result indicates that an edge event occurs on the synchronous digital signal;

[0101] Obtaining the total number of occurrences of the edge event within a preset time period;

[0102] If the total number of times reaches the preset number of times, it is determined that there is PD communication in the CC channel.

[0103] Please also read Figure 4 , Figure 4 Schematic diagram of a BMC edge detection circuit; the BMC edge detection circuit includes a first trigger DFF1, a second trigger DFF2, a third trigger DFF3, an XOR gate XOR1, a first 4-bit counter U2, a 2-bit counter U3, a first AND gate AND1 and a second AND gate AND2, wherein:

[0104] A first flip-flop DFF1 and a second flip-flop DFF2 are used to synchronize the asynchronous digital signal to obtain a synchronous digital signal;

[0105] A third trigger DFF3 is used to delay the synchronous digital signal to obtain a delayed digital signal;

[0106] XOR gate XOR1, used for edge recognition of the synchronous digital signal and the delayed digital signal to obtain an edge recognition result; wherein the edge recognition result indicates that an edge event occurs on the synchronous digital signal;

[0107] 2-bit counter U3, used to count edge events occurring within a preset time period;

[0108] The second AND gate AND2 is used to determine that there is PD communication in the CC channel as a judgment result when the bit[0] terminal and the bit[1] terminal of the 2-bit counter U3 are both 1, and then output a confirmation signal indicating that there is PD communication in the CC channel;

[0109] The first 4-bit counter U2 and the first AND gate AND1 are used to set a preset time period.

[0110] The D input terminal of the first flip-flop DFF1 is connected to the BMC receiving circuit, and the Q output terminal of the first flip-flop DFF1 is connected to the D input terminal of the second flip-flop DFF2;

[0111] The Q output terminal of the second flip-flop DFF2 is connected to the D input terminal of the third flip-flop DFF3 and one input terminal of the XOR gate XOR1;

[0112] The Q output terminal of the third flip-flop DFF3 is connected to the other input terminal of the XOR gate XOR1;

[0113] The enable terminal ena of the first 4-bit counter U2 is connected to the power supply, the reset terminal rst of the first 4-bit counter U2 is connected to the output terminal of the first AND gate AND1, and the bit[3] terminal and the bit[2] terminal of the first 4-bit counter U2 are connected to the two input terminals of the first AND gate AND1 respectively;

[0114] The enable terminal ena of the 2-bit counter U3 is connected to the output terminal of the XOR gate XOR1, the reset terminal rst of the 2-bit counter U3 is connected to the output terminal of the first AND gate AND1, and the bit[0] terminal and the bit[1] terminal of the 2-bit counter U3 are respectively connected to the two input terminals of the second AND gate AND2.

[0115] In the embodiment of the present application, the output digital signal of the BMC receiving circuit is the comparison result of the CC channel voltage and a fixed reference voltage. From its output digital signal, it can be known whether the BMC high level or low level is transmitted on the CC channel at the current moment. However, due to the connection and removal of Type-C devices, or interference from the external environment, the level on the CC channel will change. Therefore, after using the BMC receiving circuit to convert the BMC data on the CC channel, it is necessary to further analyze the BMC data to confirm whether there is PD communication.

[0116] The function of the BMC edge detection circuit is to determine whether there is PD communication on the CC channel based on the received BMC data, and then send the judgment result to the EMaker sleep control circuit.

[0117] The input of the BMC edge detection circuit is the BMC digital signal converted by the analog BMC signal receiving circuit, and the output is a flag confirmation signal indicating the presence of PD communication on the CC.

[0118] like Figure 4 As shown, the first flip-flop DFF1 and the second flip-flop DFF2 function to synchronize the digital signal, so that the digital signal is changed from an asynchronous signal to a synchronous signal.

[0119] The function of the third trigger DFF3 is to delay the digital signal by one clock cycle. By performing XOR on the current and previous values ​​of the digital signal, it is possible to obtain whether a rising edge or a falling edge appears on the digital signal at the output end of the XOR gate XOR1.

[0120] Figure 4 The output of the XOR gate XOR1 is connected to the enable terminal ena of the 2-bit counter U3, so whenever an edge event occurs on the digital signal, the output terminal of the XOR gate XOR1 becomes a high level, causing the value of the counter U3 to increase.

[0121] When bit[0] and bit[1] of counter U3 are both 1, that is, the number of edges counted by the counter is 3, the second AND gate AND2 will output a high level, indicating that the number of BMC edges has reached the maximum number that the counter can reach.

[0122] The enable terminal ena of the first 4-bit counter U2 is connected to Vdd, so every time the rising edge of the clock arrives, the count value of the counter will increase by 1. When the first 4-bit counter U2 counts to bit[3] and bit[2] are 1, the output of the first AND gate AND1 will become 1, and then the count values ​​of the first 4-bit counter U2 and the 2-bit counter U3 will be cleared.

[0123] Based on the above analysis, it can be seen that the first 4-bit counter U2 and the first AND gate AND1 function to generate a periodic pulse, and the 2-bit counter U3 is used to record the number of pulses on the digital signal. Therefore, the first 4-bit counter U2 actually plays the role of periodically clearing the currently counted pulse value.

[0124] The working principle of this circuit can be summarized as judging whether there is PD communication on the CC channel by counting the number of BMC data edges within a period of time.

[0125] If the clock is 1MHz, the first 4-bit counter U2 counts to 12, which means that every 13 microseconds, the number of pulses counted by the 2-bit counter U3 will be cleared. If the count value of the 2-bit counter U3 reaches the maximum value of 3 before being cleared, it means that there is PD communication on the CC channel.

[0126] The Emaker sleep control circuit is used to turn on the clock signal of the EMarker chip when the judgment result indicates that the PD communication exists in the CC channel, so that the EMarker chip responds to the PD message transmitted through the CC channel.

[0127] In an embodiment of the present application, the EMaker sleep control circuit is used to control the sleep and wake-up of the EMaker chip.

[0128] Please also read Figure 5 , Figure 5 : This is a structural diagram of an Emaker sleep control circuit; the Emaker sleep control circuit includes a second 4-bit counter U4, a third 4-bit counter U5, a fourth 4-bit counter U6, a fifth 4-bit counter U7, a third AND gate AND3, a fourth AND gate AND4, a fifth AND gate AND5, a sixth AND gate AND6, a seventh AND gate AND7, an eighth AND gate AND8, a ninth AND gate AND9, a tenth AND gate AND10, a fourth inverter INV4, a fourth trigger DFF4, a first crystal oscillator OSC1 and a first clock gating unit CLK_GATE1, wherein:

[0129] A second 4-bit counter U4, a third 4-bit counter U5, a fourth 4-bit counter U6, a fifth 4-bit counter U7, a sixth AND gate AND6, a seventh AND gate AND7, an eighth AND gate AND8, a ninth AND gate AND9, a tenth AND gate AND10 and the fourth flip-flop DFF4, configured to send an enable signal to the first clock gating unit CLK_GATE1 when the judgment result indicates that the PD communication exists in the CC channel;

[0130] The first crystal oscillator OSC1 is used to send a crystal oscillator signal to the first clock gating unit CLK_GATE1;

[0131] The first clock gating unit CLK_GATE1 is used to connect the crystal oscillator signal with the clock signal output by the first clock gating unit CLK_GATE1 when receiving the start signal; wherein the clock signal is used to provide a clock for the operation of the EMarker chip;

[0132] The fourth inverter INV4, the second 4-bit counter U4, the third 4-bit counter U5, the fourth 4-bit counter U6, the fifth 4-bit counter U7, the third AND gate AND3, the fourth AND gate AND4 and the fifth AND gate AND5 are used to control the connection duration between the crystal oscillator signal and the clock signal; the connection duration is a preset connection duration.

[0133] The enable terminal ena of the second 4-bit counter U4 is connected to the output terminal of the fourth inverter INV4, the reset terminal rst of the second 4-bit counter U4 is connected to the BMC edge detection circuit, and the output terminal of the second 4-bit counter U4 is connected to the input terminal of the sixth AND gate AND6;

[0134] The enable terminal ena of the third 4-bit counter U5 is connected to the output terminal of the third AND gate AND3, the reset terminal rst of the third 4-bit counter U5 is connected to the BMC edge detection circuit, and the output terminal of the third 4-bit counter U5 is connected to the input terminal of the seventh AND gate AND7;

[0135] The enable terminal ena of the fourth 4-bit counter U6 is connected to the output terminal of the fourth AND gate AND4, the reset terminal rst of the fourth 4-bit counter U6 is connected to the BMC edge detection circuit, and the output terminal of the fourth 4-bit counter U6 is connected to the input terminal of the eighth AND gate AND8;

[0136] The enable terminal ena of the fifth 4-bit counter U7 is connected to the output terminal of the fifth AND gate AND5, the reset terminal rst of the fifth 4-bit counter U7 is connected to the BMC edge detection circuit, and the output terminal of the fifth 4-bit counter U7 is connected to the input terminal of the ninth AND gate AND9;

[0137] One input end of the third AND gate AND3 is connected to the output end of the sixth AND gate AND6, and the other input end of the third AND gate AND3 is connected to the output end of the fourth inverter INV4;

[0138] One input end of the fourth AND gate AND4 is connected to the output end of the seventh AND gate AND7, and the other input end of the fourth AND gate AND4 is connected to the output end of the fourth inverter INV4;

[0139] One input end of the fifth AND gate AND5 is connected to the output end of the eighth AND gate AND8, and the other input end of the fifth AND gate AND5 is connected to the output end of the fourth inverter INV4;

[0140] The input end of the tenth AND gate AND10 is respectively connected to the output end of the sixth AND gate AND6, the output end of the seventh AND gate AND7, the output end of the eighth AND gate AND8 and the output end of the ninth AND gate AND9, and the output end of the tenth AND gate AND10 is connected to the input end of the fourth inverter INV4 and the input end D of the fourth flip-flop DFF4;

[0141] The inverting output terminal of the fourth flip-flop DFF4 connected to the enable terminal ena of the first clock gating unit CLK_GATE1;

[0142] An input end of the first clock gating unit CLK_GATE1 is connected to an output end of the first crystal oscillator OSC1, and an output end of the first clock gating unit CLK_GATE1 is connected to the EMaker chip.

[0143] In the embodiment of the present application, when the BMC edge detection circuit detects enough edge events within a certain period of time, the confirmation signal will become a high level, indicating that there is PD communication on the CC channel at this time, so the values ​​of the second 4-bit counter U4, the third 4-bit counter U5, the fourth 4-bit counter U6 and the fifth 4-bit counter U7 will be cleared, and the outputs of the 4-input AND gates (the sixth AND gate AND6, the seventh AND gate AND7, the eighth AND gate AND8, the ninth AND gate AND9 and the tenth AND gate AND10) will also become 0, so the D end of the fourth flip-flop DFF4 is also 0, which eventually causes the reverse output end of the fourth flip-flop DFF4 to be reset. becomes 1.

[0144] The first clock gating unit CLK_GATE1 is turned on under the action of the fourth trigger DFF4, and the clock signal clk_emaker sent to the EMaker chip is connected to the crystal oscillator signal clk_osc.

[0145] When the clock signal of the EMaker chip is turned on, the EMaker chip exits the sleep state and starts responding to PD communication on the CC channel.

[0146] In addition, when the output of the tenth AND gate AND10 is set to 0, the output of the fourth inverter INV4 will become 1, so the second 4-bit counter U4 will continue to accumulate until the sixth AND gate AND6 outputs a high level, and the two inputs of the third AND gate AND3 both become 1, and the value of the third 4-bit counter U5 will also increase by 1.

[0147] Similarly, the count values ​​of the fourth 4-bit counter U6 and the fifth 4-bit counter U7 will also be continuously accumulated.

[0148] After counting to the maximum value, the sixth AND gate AND6, the seventh AND gate AND7, the eighth AND gate AND8, the ninth AND gate AND9 and the tenth AND gate AND10 output 1. At this time, the outputs of the third AND gate AND3, the fourth AND gate AND4 and the fifth AND gate AND5 are all 0, and the second 4-bit counter U4, the third 4-bit counter U5, the fourth 4-bit counter U6 and the fifth 4-bit counter U7 stop counting.

[0149] The D terminal of the fourth flip-flop DFF4 will remain at 1, so the inverting output terminal of the fourth flip-flop DFF4 When the clock signal is 0, the first clock gating unit CLK_GATE1 is closed, the clock signal is disconnected from the crystal oscillator signal, and the EMaker chip stops working because there is no clock source. At this time, the EMaker chip is said to be in sleep mode.

[0150] From the working principle of the above circuit, it can be seen that the working principle of the EMaker sleep control circuit is: when a certain number of edges are detected on the CC channel within a certain period of time, it is considered that there is PD communication on the CC channel, and the EMaker chip starts working. When a certain number of edges do not appear on the CC channel within a certain period of time, and after a certain period of time, the EMaker chip will enter the sleep mode to save power consumption. In the current embodiment, assuming that the clock frequency of the counter is 1MHz, the EMaker chip will enter the sleep state after 65ms when no BMC data is detected on the CC channel.

[0151] Please also read Figure 6 , Figure 6 Schematic diagram of another Emaker sleep control circuit; the Emaker sleep control circuit includes a fifth trigger DFF5, a sixth trigger DFF6, a multiplexer Mux, a second crystal oscillator OSC2, a second clock gating unit CLK_GATE2, a fifth inverter INV5 and a NAND gate NAND1, wherein:

[0152] The output end of the multiplexer Mux is connected to the input end D of the fifth flip-flop DFF5, the input end 0 of the multiplexer Mux is connected to the BMC edge detection circuit, the input end 1 of the multiplexer Mux is connected to the output end of the NAND gate, and the selection end S0 of the multiplexer Mux is connected to the output end Q of the fifth flip-flop DFF5;

[0153] The output terminal Q of the fifth flip-flop DFF5 is also connected to the enable terminal ena of the second clock gating unit CLK_GATE2;

[0154] The input end of the second clock gating unit CLK_GATE2 is connected to the output end of the second crystal oscillator OSC2, and the output end of the second clock gating unit CLK_GATE2 is connected to the input end of the EMaker chip;

[0155] The input terminal D of the sixth flip-flop DFF6 is connected to the output terminal of the EMaker chip, and the output terminal Q of the sixth flip-flop DFF6 is connected to an input terminal of the NAND gate NAND1;

[0156] The input end of the fifth inverter INV5 is connected to the output end of the EMaker chip, and the output end of the fifth inverter INV5 is connected to the other input end of the NAND gate NAND1.

[0157] In the embodiment of the present application, the busy signal busy_flag outputted by the output end of the EMaker chip is a port controlled by the EMaker chip. When the EMaker chip is in a busy state (such as receiving a PD message or needing to respond to a PD message), the port will be set to a high level. When the EMaker chip has processed what needs to be processed, the busy signal will be cleared.

[0158] Below Figure 6 The working principle of the circuit shown is briefly introduced. Assume that the initial state is that the EMaker chip is in a dormant state (the busy signal is 0, the D and Q ends of the fifth trigger DFF5 are both 0, and the selection end S0 of the multiplexer Mux is 0). When the BMC edge detection circuit does not indicate that there is currently PD communication, that is, when bmc_edge_max_flg is 0, the D and Q ends of the fifth trigger DFF5 remain 0, and the enable signal of the second clock gating unit CLK_GATE2 also remains 0. The clock signal and the crystal oscillator signal are disconnected, and the EMaker chip remains in a dormant state. At this time, the power consumption of the EMaker chip is low.

[0159] At a certain moment, when the BMC edge detection circuit indicates that there is PD communication on the CC channel (the confirmation signal changes from low level to high level), the D end of the fifth trigger DFF5 changes from 0 to 1, so after the next clock cycle arrives, the output end Q of the fifth trigger DFF5 changes to 1, and the enable signal of the second clock gating unit CLK_GATE2 is 1. The clock signal of the EMaker chip is connected to the second crystal oscillator signal, and the EMaker chip exits the sleep state and starts working.

[0160] When the EMaker chip starts working, the selection terminal S0 of the multiplexer Mux also changes from 0 to 1, so the D terminal of the fifth trigger DFF5 is determined by the output of the NAND gate NAND1. At this time, even if the confirmation signal becomes 0 (there is no PD communication on the CC channel), the D terminal of the fifth trigger DFF5 still remains 1, that is, the EMaker chip is still in working state.

[0161] When the EMaker chip starts working, its output port busy signal will be set to a high level, but the output of the NAND gate NAND1 is actually the result of inverting the falling edge of the busy signal, so the output of the NAND gate NAND1 will still remain at 1, so the D end of the fifth trigger DFF5 will also remain at 1.

[0162] When the EMaker chip completes the response to the message, it will clear the busy signal. At the moment when the busy signal is cleared, the output of the fifth inverter INV5 is 1, and the input of the sixth flip-flop DFF6 is 0, but the output Q of the sixth flip-flop DFF6 remains 1, so the output of the NAND gate NAND1 is 0, and the D input of the fifth flip-flop DFF5 changes from 1 to 0.

[0163] This eventually causes the enable terminal ena of the second clock gating unit CLK_GATE2 to be 0, the clock of the EMaker chip is disconnected, and the EMaker chip re-enters the sleep state.

[0164] At the same time, the selection terminal S0 of the multiplexer Mux also changes from 1 to 0, so the D terminal of the fifth flip-flop DFF5 is determined by the confirmation signal again.

[0165] Through the above analysis, we can know Figure 6 and Figure 5 The difference between the EMaker sleep control circuit is that, Figure 5 An open-loop control strategy is adopted for the sleep state of the EMaker chip, that is, no matter what state the EMaker chip is in, as long as the BMC edge detection circuit does not detect PD communication within a certain period of time, the EMaker sleep control circuit will turn off the clock of the EMaker chip and put it into sleep state.

[0166] Figure 6 In the EMaker chip, a closed-loop strategy is adopted. When the EMaker chip is processing data (such as responding to a message), a busy signal will be set. When the EMaker chip completes the response to the message, the busy signal will be cleared, and the clock of the EMaker chip will be turned off, thereby achieving the purpose of saving power.

[0167] The embodiment of the present application can reduce the power consumption of the EMaker chip when it does not need to work. After actual testing, the EMaker chip equipped with the EMarker chip wake-up circuit of the present application can reduce the power consumption by about 50%.

[0168] The present application converts the analog BMC signal into a digital signal through the BMC receiving circuit, and parses the digital signal through the BMC edge detection circuit to analyze whether there is PD communication in the CC channel. If it is determined that there is PD communication in the CC channel, the dormant EMaker chip can be awakened by the Emaker sleep control circuit to enable the EMarker chip to respond to the PD message transmitted through the CC channel, so that the EMarker chip can be in a dormant state in the absence of PD communication. When PD communication is detected, the EMarker chip is awakened. It can be seen that this method can reduce the additional power consumption of the EMaker chip, thereby improving the user experience.

[0169] In an exemplary embodiment, Figure 7 As shown, an EMarker chip wake-up method is provided, which is executed by an EMarker chip wake-up circuit. In the embodiment of the present application, the following steps 701 to 705 are included. Among them:

[0170] Step 701: Convert the analog BMC signal input by the CC channel into a digital signal.

[0171] Step 702: synchronize the digital signal to obtain a synchronized digital signal.

[0172] Step 703, delaying the synchronous digital signal to obtain a delayed digital signal.

[0173] Step 704: Based on the synchronous digital signal and the delayed digital signal, obtain the total number of edge events occurring within a preset time period.

[0174] Step 705: If the total number of times reaches the preset number of times, it is determined that there is PD communication in the CC channel, and the clock signal of the EMarker chip is turned on to enable the EMarker chip to respond to the PD message transmitted through the CC channel.

[0175] Implementing the above steps 701 to 705 can reduce the extra power consumption of the EMaker chip, thereby improving the user experience.

[0176] In an exemplary embodiment, a computer device is provided. The computer device may be a server or a terminal. The internal structure diagram thereof may be as follows: Figure 8As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store EMarker chip wake-up data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, an EMarker chip wake-up method is implemented.

[0177] Those skilled in the art will understand that Figure 8 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0178] In an exemplary embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0179] In an exemplary embodiment, a computer-readable storage medium is provided, storing a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0180] In an exemplary embodiment, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0181] In an exemplary embodiment, a chip is provided, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the steps in the above-mentioned method embodiments and achieve the same technical effects. To avoid repetition, they are not described here.

[0182] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0183] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0184] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM may be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0185] The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. The non-relational database may include a distributed database based on blockchain, etc., but is not limited thereto. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but is not limited thereto.

[0186] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0187] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. At the same time, for those skilled in the art, according to the ideas of this application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting this application.

Claims

1. An EMarker chip wake-up circuit, characterized in that: The EMarker chip wake-up circuit includes a BMC receiving circuit, a BMC edge detection circuit, an Emaker sleep control circuit and an EMarker chip. The input end of the BMC receiving circuit is connected to the CC channel of the Type-C cable, the output end of the BMC receiving circuit is connected to the input end of the BMC edge detection circuit, the output end of the BMC edge detection circuit is connected to the input end of the Emaker sleep control circuit, and the output end of the Emaker sleep control circuit is connected to the EMarker chip, wherein: The BMC receiving circuit is used to convert the analog BMC signal input by the CC channel into a digital signal; The BMC edge detection circuit is used to determine whether there is PD communication in the CC channel by analyzing the digital signal to obtain a determination result; The Emaker sleep control circuit is used to turn on the clock signal of the EMarker chip when the judgment result indicates that the PD communication exists in the CC channel, so that the EMarker chip responds to the PD message transmitted through the CC channel.

2. The EMarker chip wake-up circuit according to claim 1, characterized in that: The BMC receiving circuit includes a comparator, a Schmitt trigger and a first inverter, wherein: The comparator is used to compare the voltage of the analog BMC signal input by the CC channel with the reference voltage to obtain a comparison result, and output a first level matching the comparison result; The Schmitt trigger is used to input the first level to the first inverter; The first inverter is used to invert the first level to obtain a second level, and output the second level as a digital signal.

3. The EMarker chip wake-up circuit according to claim 1, characterized in that: The BMC receiving circuit includes a second inverter, a third inverter, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, wherein: The input end of the second inverter is connected to the CC channel of the Type-C cable, and the output end of the second inverter is connected to the input end of the third inverter and the gate of the second NMOS tube; The output end of the third inverter is connected to the gate of the first NMOS tube; The source of the first NMOS tube is connected to a source power supply voltage, and the drain of the first NMOS tube is connected to the source of the first PMOS tube and the gate of the second PMOS tube; The source of the second NMOS tube is connected to the source power supply voltage, and the drain of the second NMOS tube is connected to the source of the second PMOS tube and the gate of the first PMOS tube; The drain of the first PMOS tube and the drain of the second PMOS tube are connected to a power source.

4. The EMarker chip wake-up circuit according to claim 1, characterized in that: The digital signal is an asynchronous digital signal. The BMC edge detection circuit analyzes the digital signal to determine whether there is PD communication in the CC channel. The determination result is obtained in the following manner: Synchronizing the asynchronous digital signal to obtain a synchronous digital signal; Delaying the synchronous digital signal to obtain a delayed digital signal; Performing edge recognition on the synchronous digital signal and the delayed digital signal to obtain an edge recognition result; wherein the edge recognition result indicates that an edge event occurs on the synchronous digital signal; Obtaining the total number of occurrences of the edge event within a preset time period; If the total number of times reaches the preset number of times, it is determined that there is PD communication in the CC channel.

5. The EMarker chip wake-up circuit according to claim 1, characterized in that: The Emaker sleep control circuit includes a second 4-bit counter, a third 4-bit counter, a fourth 4-bit counter, a fifth 4-bit counter, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, a ninth AND gate, a tenth AND gate, a fourth inverter, a fourth trigger, a first crystal oscillator and a first clock gating unit, wherein: The second 4-bit counter, the third 4-bit counter, the fourth 4-bit counter, the fifth 4-bit counter, the sixth AND gate, the seventh AND gate, the eighth AND gate, the ninth AND gate, the tenth AND gate and the fourth trigger are used to send an enable signal to the first clock gating unit when the judgment result indicates that the PD communication exists in the CC channel; The first crystal oscillator is used to send a crystal oscillator signal to the first clock gating unit; The first clock gating unit is used to connect the crystal oscillator signal with the clock signal output by the first clock gating unit when receiving the start signal; wherein the clock signal is used to provide a clock for the operation of the EMarker chip; The fourth inverter, the second 4-bit counter, the third 4-bit counter, the fourth 4-bit counter, the fifth 4-bit counter, the third AND gate, the fourth AND gate and the fifth AND gate are used to control the connection duration between the crystal oscillator signal and the clock signal; the connection duration is a preset connection duration.

6. The EMarker chip wake-up circuit according to claim 1, characterized in that: The Emaker sleep control circuit includes a fifth trigger, a sixth trigger, a multiplexer, a second crystal oscillator, a second clock gating unit, a fifth inverter and a NAND gate, wherein: The output end of the multiplexer is connected to the input end D of the fifth trigger, the input end 0 of the multiplexer is connected to the BMC edge detection circuit, the input end 1 of the multiplexer is connected to the output end of the NAND gate, and the selection end S0 of the multiplexer is connected to the output end Q of the fifth trigger; The output terminal Q of the fifth trigger is also connected to the enable terminal of the second clock gating unit; The input end of the second clock gating unit is connected to the output end of the second crystal oscillator, and the output end of the second clock gating unit is connected to the input end of the EMaker chip; The input terminal D of the sixth trigger is connected to the output terminal of the EMaker chip, and the output terminal Q of the sixth trigger is connected to an input terminal of the NAND gate; The input end of the fifth inverter is connected to the output end of the EMaker chip, and the output end of the fifth inverter is connected to another input end of the NAND gate.

7. An EMarker chip wake-up method, characterized in that: The method is applied to the EMarker chip wake-up circuit in claim 1, and the EMarker chip wake-up method comprises: Convert the analog BMC signal input by CC channel into digital signal; Synchronizing the digital signal to obtain a synchronized digital signal; Delaying the synchronous digital signal to obtain a delayed digital signal; Based on the synchronous digital signal and the delayed digital signal, obtaining the total number of edge events occurring within a preset time period; If the total number of times reaches the preset number of times, it is determined that there is PD communication in the CC channel, and the clock signal of the EMarker chip is turned on to enable the EMarker chip to respond to the PD message transmitted through the CC channel.

8. A computer device comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the EMarker chip wake-up method described in claim 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the EMarker chip wake-up method described in claim 7 are implemented.

10. A chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, characterized in that: The processor is used to run a program or an instruction, and when the processor executes the program or the instruction, the steps of the EMarker chip wake-up method as claimed in claim 7 are implemented.

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