Data reading method and memory controller

Abstract

The application provides a data reading method and a memory controller thereof, which are suitable for a storage device with a rewritable non-volatile memory module. The method comprises: performing a read operation on a target physical page to obtain target data containing a plurality of bit page data; when the number of error bits of the target bit page data exceeds a preset threshold, obtaining a target voltage level table corresponding to the bit page type, and performing an iterative re-reading according to a current level sequence number in the table; if the number of error bits after re-reading does not exceed the preset threshold, obtaining original data and updating the target voltage level table based on the current level sequence number. The application can effectively reduce the number of re-reading attempts and improve the re-reading efficiency of the flash memory by maintaining the order of the voltage level table and preferentially using the voltage level group with a high re-reading success rate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, and in particular to a data reading method for improving read retry efficiency of rewritable non-volatile memory and a memory controller thereof. BACKGROUND

[0002] NAND flash is a kind of non-volatile memory, which can keep data after power off, has the advantages of data non-volatility, power saving, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] Due to the inherent characteristics of NAND flash, each page of data is usually divided into multiple error correction code (ECC) blocks. When writing, each ECC block performs error detection and correction coding, so that corresponding ECC decoding can be performed when reading to ensure data integrity.

[0004] With the use of NAND flash, the storage unit will gradually wear out, resulting in an increase in the number of error bits. In order to ensure data reliability, user data must be protected by ECC, so that even if some bits are wrong, they can be corrected by ECC. However, the error correction capability of ECC is limited, and when the error exceeds its error correction range, read retry operation is needed. Read retry operation re-reads data by adjusting read voltage and uses ECC for error correction. If the parameter adjustment is unreasonable, it will cause multiple reading and checking, increase the burden of NAND controller, and affect the reading speed and overall performance. SUMMARY

[0005] The purpose of the present application is to provide a method for improving the read retry efficiency of flash memory and a memory controller thereof, which maintains a sorting table about the voltage adjustment table, which is conducive to reducing the number of read retries, thereby improving the read retry efficiency after reading data from NAND flash memory.

[0006] One or more embodiments of the present disclosure provide a data read method suitable for a memory controller of a storage device configured with a rewritable non-volatile memory module. The method comprises: performing a read operation on a target physical page of the rewritable non-volatile memory module to obtain target data comprising a plurality of bit page data corresponding to a plurality of bit page types and a number of error bits corresponding to each bit page data, wherein each memory cell of the target physical page can store a plurality of bits corresponding to the plurality of bit page types respectively; if a target number of error bits of a target bit page data in the plurality of bit page data exceeds a preset error bit threshold: obtaining a target voltage level table corresponding to a target bit page type of the target bit page data; selecting a level sequence number as a current level sequence number according to an order of a plurality of level sequence numbers of the target voltage level table, to perform an iterative re-read operation on the target physical page through the current level sequence number, thereby obtaining re-read target data comprising a plurality of re-read bit page data corresponding to the plurality of bit page types and a number of re-read error bits corresponding to each re-read bit page data; and if the number of re-read error bits of each re-read bit page data does not exceed the preset error bit threshold, determining that the original data stored in the target physical page is successfully obtained, ending the iterative re-read operation, and updating the target voltage level table based on the current level sequence number.

[0007] In one or more embodiments of the present disclosure, after obtaining the re-read target data and the error correction status corresponding to each re-read bit page data, the method further comprises: if the error correction status corresponding to each re-read bit page data is characterized as unsuccessful error correction, then sequentially selecting a next level sequence number as a new current level sequence number to perform the iterative re-read operation, and repeating this cycle until a level sequence number appears that characterizes the error correction status of each re-read bit page data as successful error correction.

[0008] In one or more embodiments of the present disclosure, the iterative re-read operation comprises: determining a target voltage adjustment level corresponding to the target physical page in the target voltage level table according to the current level sequence number; adjusting a target read reference voltage corresponding to the target bit page type in a reference voltage group based on the target voltage adjustment level; and re-reading the target physical page using the adjusted reference voltage group to obtain re-read target data comprising a plurality of re-read bit page data corresponding to the plurality of bit page types and an error correction status corresponding to each re-read bit page data.

[0009] In one or more embodiments of the present application, the method further comprises: establishing a ranking table according to the target voltage gear table, the ranking table prioritizing each of the gear numbers according to the ranking information of each of the gear numbers; the step of sequentially selecting a gear number as the current gear number according to the order of the gear numbers of the target voltage gear table comprises: obtaining the ranking table and sequentially selecting a gear number as the current gear number according to the priority of each of the gear numbers in the ranking table. The step of updating the ranking information corresponding to the current gear number comprises: updating the ranking information of the current gear number and adjusting the priority of the current gear number in the ranking table according to the updated ranking information.

[0010] In one or more embodiments of the present application, the method further comprises: if the original data is successfully obtained after performing the iterative read operation on the target physical page by the current gear number, accumulating the successful read number of the corresponding current gear number; and the step of updating the ranking information corresponding to the current gear number comprises: after updating the successful read number of the current gear number, performing descending order ranking on the plurality of gear numbers according to the size of the successful read number of each of the plurality of gear numbers to obtain the updated target voltage gear table, wherein the gear number with the largest successful read number is selected first to perform the iterative read operation.

[0011] In one or more embodiments of the present application, the method further comprises: if the original data is successfully obtained after performing the iterative read operation on the target physical page by the current gear number, accumulating the successful read number of the corresponding current gear number, and obtaining the program-erase cycle number of the target physical page, determining a target program-erase cycle interval according to the program-erase cycle number; and obtaining the target voltage gear table corresponding to the target bit page type and the target program-erase cycle interval according to the target bit page type and the target program-erase cycle interval, wherein the step of updating the ranking information corresponding to the current gear number comprises: after updating the successful read number of the current gear number, performing descending order ranking on the plurality of gear numbers according to the size of the successful read number of each of the plurality of gear numbers to obtain the updated target voltage gear table, wherein the gear number with the largest successful read number is selected first to perform the iterative read operation.

[0012] In one or more embodiments of the present application, the step of obtaining the target voltage gear table corresponding to the target bit page type comprises: obtaining the program-erase cycle number of the target physical page;

[0013] determining a target P / E cycle interval according to the programmed P / E cycle number; and obtaining the target voltage table corresponding to the target P / E cycle interval from the plurality of voltage tables corresponding to the target bit page type, according to the target bit page type and the target P / E cycle interval.

[0014] In one or more embodiments of the present application, the method further comprises: when a new voltage table corresponding to a new P / E cycle interval needs to be established, if one or more adjacent voltage tables corresponding to one or more adjacent P / E cycle intervals adjacent to the new P / E cycle interval have been established, copying one of the one or more adjacent voltage tables as initial content of the new voltage table.

[0015] In one or more embodiments of the present application, the method further comprises: obtaining an original voltage table; and dividing the original voltage table to obtain a plurality of voltage tables corresponding to the plurality of bit page types respectively according to a plurality of voltage data corresponding to the plurality of bit page types in the original voltage table, wherein each voltage table has voltage data of the corresponding bit page type, and the target voltage table is one or more of the plurality of voltage tables.

[0016] In one or more embodiments of the present application, the method further comprises: after obtaining the plurality of voltage tables, performing deduplication processing on a plurality of voltage sub-data of the voltage data of each voltage table, including: obtaining a plurality of target voltage sub-data having the same content in the plurality of voltage sub-data, wherein each voltage sub-data corresponds to a different original voltage sequence number of the original voltage table; and retaining only one target voltage sub-data in the plurality of target voltage sub-data; and after completing the deduplication processing, assigning a plurality of voltage sequence numbers to a plurality of remaining voltage sub-data respectively to obtain the plurality of voltage tables corresponding to the plurality of bit page types respectively.

[0017] One or more embodiments of the present disclosure provide a memory controller for controlling a storage device configured with a rewritable non-volatile memory module. The memory controller includes a memory interface control circuit electrically connected to the rewritable non-volatile memory module, and a processor electrically connected to the memory interface control circuit, wherein the processor is configured to: perform a read operation on a target physical page of the rewritable non-volatile memory module to obtain target data including a plurality of bit page data corresponding to a plurality of bit page types and error correction conditions corresponding to each bit page data, wherein each memory cell of the target physical page can store a plurality of bits corresponding to the plurality of bit page types, respectively; if an error correction condition of a target bit page data in the plurality of bit page data represents an unsuccessful error correction: obtain a target voltage level table of a target bit page type corresponding to the target bit page data; sequentially select a level sequence number as a current level sequence number according to an order of a plurality of level sequence numbers of the target voltage level table, to perform an iterative read operation on the target physical page through a voltage level corresponding to the current level sequence number, so as to obtain read target data including a plurality of read bit page data corresponding to the plurality of bit page types and error correction conditions corresponding to each read bit page data; and if the error correction condition of each read bit page data represents a successful error correction, determine that the original data stored in the target physical page is successfully obtained, and update the ordering information corresponding to the current level sequence number.

[0018] Based on the above, the data reading method and the memory controller provided by the embodiments of the present disclosure, by performing a read operation on a target physical page of a rewritable non-volatile memory module, obtaining target data including a plurality of bit page data corresponding to a plurality of bit page types and error correction conditions corresponding to each bit page data, if an error correction condition of a target bit page data in the plurality of bit page data represents an unsuccessful error correction, sequentially selecting a level sequence number according to an order of a plurality of level sequence numbers of a target voltage level table to perform an iterative read operation. By prioritizing the read successful level sequence number, the number of invalid read attempts is reduced, thereby improving the read efficiency. At the same time, by maintaining the voltage level table for different bit page types, the system can more accurately select the appropriate voltage level, thereby improving the data reading reliability while effectively reducing the processing burden of the memory controller. In addition, the present disclosure realizes an adaptive voltage adjustment strategy by counting and dynamically sorting the read successful level sequence number, not only improves the accuracy of the read operation, but also prolongs the service life of the storage device. BRIEF DESCRIPTION OF DRAWINGS

[0019] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0020] Figure 1 This is a block diagram illustrating a host system and storage device according to an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the critical voltage distribution and corresponding bit values ​​for different bit page types of a QLC according to an embodiment of the present invention.

[0022] Figure 3 This is a schematic diagram of the original voltage range table according to an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram illustrating the segmentation of the original voltage level table based on bit page type according to an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram illustrating the generation of voltage level tables corresponding to different bit page types via segmentation and deduplication operations according to an embodiment of the present invention.

[0025] Figure 6 This is a schematic diagram illustrating the adjustment of the priority of the current gear number in the sorting table based on updated sorting information, according to an embodiment of the present invention.

[0026] Figure 7 This is a schematic diagram illustrating the updating of the voltage range table after successfully acquiring the original data via a rereading operation, according to an embodiment of the present invention.

[0027] Figure 8 This is a schematic diagram of a voltage level table corresponding to different programmable erase cycle intervals belonging to the same bit page type, as shown in an embodiment of the present invention.

[0028] Figure 9 This is a flowchart illustrating a data reading method according to an embodiment of the present invention.

[0029] Explanation of icon numbers

[0030] 10: Host System

[0031] 20: Storage device

[0032] 211: First Processor

[0033] 110: Second Processor

[0034] 120: Host memory

[0035] 130: Data transmission interface circuit

[0036] 210: Memory controller

[0037] 212: Data Management Circuit

[0038] 213: Memory Interface Control Circuit

[0039] 214: Buffer memory

[0040] 220: Rewritable Non-volatile Memory Module

[0041] 230: Connection interface circuit

[0042] BP1: First bit page type

[0043] BP2: Second bit page type

[0044] BP3: Third bit page type

[0045] BP4: Fourth bit page type

[0046] RV1-RV15: Read reference voltage

[0047] RVG: Reference Voltage Group

[0048] TB0, TB40, TB50: Original voltage range table

[0049] TB41-TB44, TB51-TB54, TB55-TB58, TB81-TB83: Voltage Range Table

[0050] TB71: Target Voltage Range Table

[0051] TB72: Updated Target Voltage Range Table

[0052] A41-A44, A51-A54: Arrows (segmentation operation)

[0053] A55-A58: Arrows (Deduplication Operation)

[0054] A61-A63: Arrows (Update Operation)

[0055] A71-A72: Arrows (Update Operation)

[0056] S910-S940: Flowchart of Data Reading Method Detailed Implementation

[0057] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0058] Figure 1 This is a block diagram illustrating a host system and storage device according to an embodiment of the present invention. Please refer to... Figure 1The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), host memory 120, and a data transfer interface circuit 130. In this embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, host memory 120, and data transfer interface circuit 130 may be disposed on the motherboard of the host system 10.

[0059] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also referred to as a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0060] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0061] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a USB flash drive, memory card, solid-state drive (SSD), or wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, network interface card, wireless transmission device, keyboard, screen, and speaker.

[0062] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the Peripheral Component Interconnect Express (PCI Express) standard. Furthermore, data transmission between the data transmission interface circuit 130 and the connection interface circuit 230 utilizes the Non-Volatile Memory Express (NVMe) communication protocol.

[0063] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip containing the memory controller 210.

[0064] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it must be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0065] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to the instructions of the host system 10.

[0066] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data. Furthermore, in this embodiment, the control instructions / program codes can also be executed to perform data reading operations to implement the data reading method provided by this invention. The control instructions / program codes corresponding to the data reading method can also be implemented as hardware circuit units to implement the data reading method provided by this invention.

[0067] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (microprocessor), digital signal processor (DSP), programmable controller, application specific integrated circuits (ASIC), programmable logic device (PLD), or other similar circuit components, and the present invention is not limited thereto.

[0068] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0069] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213, and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to perform data transfer. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., performing a write operation according to a write instruction from the host system 10). Another example is reading data from one or more physical units (also called physical blocks) of the rewritable non-volatile memory module 220 (data can be read from multiple storage cells in one or more physical units) via the memory interface control circuit 213, and writing the read data to the host system 10 (e.g., host memory 120) via the connection interface circuit 230 (e.g., performing a read operation according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

[0070] The memory interface control circuit 213 is used to receive instructions from the processor 211 and, in conjunction with the data management circuit 212, to perform write (also known as programming) operations, read operations, or erase operations on the rewritable non-volatile memory module 220.

[0071] Furthermore, data to be written to the rewritable non-volatile memory module 220 is converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 needs to access the rewritable non-volatile memory module 220, the processor 211 will send a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform the corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating the writing of data, a read instruction sequence indicating the reading of data, an erase instruction sequence indicating the erasure of data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code, memory address, and physical address.

[0072] Furthermore, the memory controller 210 establishes a logical-to-physical address mapping table and a physical-to-logical address mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses (physical addresses) of physical units (e.g., physical erase units / physical blocks, physical pages) configured for the rewritable non-volatile memory module 220. In other words, the memory controller 210 can use the logical-to-physical address mapping table (also called the logical-to-physical mapping table) to look up the physical unit mapped to a logical unit (e.g., look up the physical page mapped to a logical page; look up the physical address mapped to a logical address), and the memory controller 210 can use the physical-to-logical address mapping table (also called the physical-to-logical mapping table) to look up the logical unit mapped to a physical unit (e.g., look up the logical page mapped to a physical page; look up the logical address mapped to a physical address).

[0073] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data used to manage the storage device 20 (e.g., various voltage level tables, various mapping tables, programmable erase cycle tables) so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 214. In one embodiment, the memory controller 210 may establish one or more write mapping tables within the buffer memory 214 to indicate the target entity address for writing valid data. It should be noted that in other embodiments, the buffer memory 214 may also be configured outside the memory controller 210. Alternatively, the buffer memory 214 may be configured both inside and outside the memory controller 210.

[0074] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213) and is used to store user data sent by the host system 10.

[0075] In this embodiment, each memory die (chip) in the rewritable non-volatile memory module 220 has multiple planes, and each plane has multiple physical blocks. Each physical block includes multiple physical programmable units (also called physical pages). Each physical page has multiple memory groups (also called physical bytes or bytes), and each memory group corresponds to a physical address. The physical address is used to record the physical location of the data stored in the memory group. It should be noted that the present invention is not limited to the size of each physical page and logical page. Each memory group has multiple memory cells (also called memory cells).

[0076] In one embodiment, the memory controller 210 uses error checking and correction (ECC) technology to identify and repair erroneous bits in the data. More specifically, when the memory controller 210 needs to read the original data TD stored in a target physical page of a rewritable non-volatile memory module in response to the host system 10, the memory controller 210 first performs a read operation on the target physical page to obtain target data containing multiple bit page data corresponding to multiple bit page types and their ECC check bits, wherein each storage unit of the target physical page can store multiple bits corresponding to the multiple bit page types respectively.

[0077] Subsequently, the memory controller 210 uses a decoder with a specific algorithm to obtain the error correction status of the target data, and determines whether the error correction was successful based on the error correction status. If the error correction status of the target bit page data among the multiple bit pages is deemed unsuccessful, it prepares for an iterative reread operation.

[0078] It should be noted that target bit page data refers to data stored in the same type of bit page.

[0079] In one embodiment, after acquiring the target data to be reread and the error correction status of each corresponding reread bit page, the memory controller 211 first checks the error correction status of each reread bit page. If the memory controller 211 finds that the error correction status of any reread bit page is still characterized as unsuccessful error correction, it will continue to perform iterative reread operations.

[0080] Specifically, the memory controller 211 selects the second-highest priority level number from the current sorting table or voltage level table as the new current level number. For example, suppose that after the memory controller 211 performs an iterative reread operation using the highest priority level number A, it finds that the error correction status of the reread bit page data corresponding to the second bit page type BP2 is still characterized as unsuccessful error correction, then the memory controller 211 will select the second-highest priority level number B as the new current level number and perform a new round of iterative reread operation.

[0081] The memory controller 211 continuously performs this cyclical operation: whenever it detects that the error correction status of any reread bit page data is unsuccessful, it selects the next higher priority slot number to perform the iterative reread operation. This process continues until a slot number is found that indicates successful error correction for all reread bit page data, or all available slot numbers have been tried.

[0082] In one embodiment, the specific execution process of the iterative reread operation is described in detail. The iterative reread operation performed by the memory controller 211 includes a series of specific steps.

[0083] First, the memory controller 211 determines the corresponding target voltage regulation level from the target voltage level table based on the current level number. For example, assuming the target bit page type is the first bit page type BP1 and the current level number is 2, the memory controller 211 will obtain the four target voltage regulation levels corresponding to that level number from the target voltage level table. For example, these voltage regulation levels are used to adjust the read reference voltages RV1, RV4, RV6, and RV11, respectively.

[0084] Next, the memory controller 211 adjusts the target read reference voltage for the corresponding target bit page type in the reference voltage group based on these target voltage adjustment levels. For example, if a target voltage adjustment level is 0x06, the memory controller 211 will increase the corresponding read reference voltage by 0.12 volts (0.02 volts × 6); if the target voltage adjustment level is 0xF9, it will decrease the read reference voltage by 0.14 volts (0.02 volts × [249-256]). It should be noted that when adjusting these target read reference voltages, the read reference voltages corresponding to other bit page types in the reference voltage group remain unchanged.

[0085] Finally, the memory controller 211 performs a reread operation on the target physical page using the adjusted complete reference voltage set. This reread operation acquires the complete reread target data containing data of all bit page types, even if only the read reference voltage for a specific bit page type has been adjusted. The memory controller 211 then processes this reread data through a decoder to obtain the error correction status of the corresponding reread bit page data, which is used to determine whether the current iterative reread operation was successful.

[0086] In one embodiment, for example, the memory controller 210 uses a low-density parity check (LDPC) decoder to calculate the relationship between parity bits and data bits through a parity matrix, and counts the number of error bits for each corresponding bit page. If the target error bit count of the target bit page data in the plurality of bit pages exceeds a preset error bit count threshold (e.g., the error correction status of the target bit page data in the plurality of bit pages is characterized as unsuccessful error correction), the memory controller 210 will mark the target bit page type of the target physical page for iterative rereading operation. Conversely, if the number of error bits of the read target data does not exceed the preset error bit count threshold, the memory controller 210 determines that the original data stored in the target physical page has been successfully acquired, and can transmit the original data TD to the host system 10.

[0087] To better understand the storage characteristics of the target physical page described in this invention, a QLC-type storage unit will be used as an example for explanation.

[0088] Figure 2 This is a schematic diagram of the critical voltage distribution and corresponding bit values ​​for different bit page types of a QLC according to an embodiment of the present invention.

[0089] In one embodiment, please refer to Figure 2 , Figure 2 In the RVG section, it represents the reference voltage group used for the read operation. Figure 2 The vertical axis represents the critical voltage distribution, and the horizontal axis represents the reference voltage. The "1" or "0" marked in the peak region indicates the bit value stored in the memory cell within that critical voltage range under the corresponding bit page type.

[0090] like Figure 2As shown, a QLC-type memory cell can store 4 bits of data using different threshold voltage values. Correspondingly, a QLC-type memory cell corresponds to four bit page types: a first bit page type BP1, a second bit page type BP2, a third bit page type BP3, and a fourth bit page type BP4. This means that each memory cell of the target physical page described in this invention can store multiple bits corresponding to the aforementioned bit page types. Specifically, each memory cell can simultaneously store the first bit corresponding to the first bit page type BP1, the second bit corresponding to the second bit page type BP2, the third bit corresponding to the third bit page type BP3, and the fourth bit corresponding to the fourth bit page type BP4.

[0091] During a read operation, different read reference voltages RV1 to RV15 from the reference voltage group RVG need to be applied to retrieve the bit value stored in the memory cell. For example... Figure 2 As shown, QLC type memory cells can obtain the bit values ​​stored in the memory cell by applying different read reference voltages RV1 to RV15. Specifically, reference voltages RV1, RV4, RV6, and RV11 are used to control the data reading of the corresponding first bit page type BP1 (also known as the Lower page); reference voltages RV3, RV7, RV9, and RV13 are used to control the data reading of the corresponding second bit page type BP2 (also known as the Middle page); reference voltages RV2, RV8, and RV14 are used to control the data reading of the corresponding third bit page type BP3 (also known as the Upper page); and reference voltages RV5, RV10, RV12, and RV15 are used to control the data reading of the corresponding fourth bit page type BP4 (also known as the eXtra page). By applying these read reference voltages, the bit values ​​stored in the memory cell under different bit page types can be obtained.

[0092] More specifically, in one embodiment, by applying an appropriate read reference voltage to the memory cell, the data stored in the memory cell can be determined based on its conduction status. Taking the first bit page type BP1 (Lower page) as an example, when a reference voltage RV8 is applied, if the critical voltage of the memory cell is lower than RV8, it indicates that the bit value stored in the memory cell in the first bit page type BP1 is "1"; conversely, if the critical voltage of the memory cell is higher than RV8, it indicates that the bit value stored is "0". Reading operations for other bit page types follow a similar principle. For example, for the second bit page type BP2 (Middle page), by sequentially applying reference voltages RV4, RV5, RV6, and RV12 and determining the conduction status of the memory cell under these reference voltages, the bit value stored in the memory cell in the second bit page type BP2 can be determined. In this way, bit values ​​corresponding to different bit page types can be read from the same memory cell.

[0093] However, as storage units are used over time, such as Figure 1 As shown, the critical voltage of the storage cell is prone to deviation. If the original read reference voltage is still used for reading, the target number of error bits in the target bit page data may exceed the preset error bit threshold (i.e., exceed the error correction capability of the error detection and correction coding), thus making it impossible to obtain the original data stored in the target physical page.

[0094] Based on this, the manufacturer of the rewritable non-volatile memory module 220 will define a target voltage level table. When the target number of error bits exceeds the preset error bit threshold, the memory controller 211 can select a level number as the current level number according to the order of multiple level numbers in the target voltage level table, so as to perform an iterative reread operation on the target physical page using the current level number. Specifically, the target voltage level table may contain 256 level numbers, represented in hexadecimal as 0x00-0xFF, where 0x01-0x7F are positive offset (right offset) voltage levels, and 0x80-0xFF are negative offset (left offset) voltage levels. The voltage adjustment range corresponding to each level number can be set to the same value, for example, 0.02 volts. Therefore, when the current level number corresponding to a certain read reference voltage is 0x03, the new read reference voltage value used in the iterative reread operation will be the initial value of the read reference voltage plus 0.02 volts multiplied by 3.

[0095] Figure 3 This is a schematic diagram of the original voltage range table according to an embodiment of the present invention.

[0096] In one embodiment, such as Figure 3As shown, the original voltage range table TB0 contains multiple voltage adjustment ranges for the read reference voltages for different bit page types. Specifically, the original voltage range table TB0 records multiple voltage adjustment ranges for the read reference voltages corresponding to the first bit page type BP1 (Lower), the second bit page type BP2 (Middle), the third bit page type BP3 (Upper), and the fourth bit page type BP4 (eXtra).

[0097] In this embodiment, the original voltage range table TB0 contains multiple sets of voltage adjustment ranges, each set of voltage adjustment ranges is numbered with a preset sequence number (for ease of explanation, only 8 preset ranges are used, such as 0 to 8; the present invention is not limited to the total number of voltage adjustment ranges). It should be noted that range number 0 is a preset range number, which is used to indicate that the existing reading voltage is maintained and no adjustment is made.

[0098] The voltage adjustment levels for the read reference voltages RV1, RV4, RV6, and RV11 corresponding to the first bit page type BP1 are recorded in the columns Lower-R1, Lower-R4, Lower-R6, and Lower-R11, respectively; the voltage adjustment levels for the read reference voltages RV3, RV7, RV9, and RV13 corresponding to the second bit page type BP2 are recorded in the columns Middle-R3, Middle-R7, Middle-R9, and Middle-R13, respectively; the voltage adjustment levels for the read reference voltages RV2, RV8, and RV14 corresponding to the third bit page type BP3 are recorded in the columns Upper-R2, Upper-R8, and Upper-R14, respectively (Upper-NU is empty); and the voltage adjustment levels for the read reference voltages RV5, RV10, RV12, and RV15 corresponding to the fourth bit page type BP4 are recorded in the columns eXtra-R5, eXtra-R10, eXtra-R12, and eXtra-R15, respectively.

[0099] For example, when the preset voltage adjustment level group corresponding to number 1 is selected, the voltage adjustment level for the read reference voltage RV1 corresponding to the first bit page type BP1 is 0x06, and the voltage adjustment level for RV4 is 0x04; the voltage adjustment level for the read reference voltage RV3 corresponding to the second bit page type BP2 is 0x05, and the voltage adjustment level for RV7 is 0x02; the voltage adjustment level for the read reference voltage RV2 corresponding to the third bit page type BP3 is 0x06, and the voltage adjustment level for RV8 is 0x01; the voltage adjustment level for the read reference voltage RV5 corresponding to the fourth bit page type BP4 is 0x04, and the voltage adjustment level for RV15 is 0x00, and so on. The memory controller 211 can adjust the corresponding read reference voltage value according to these voltage adjustment levels to perform iterative reread operations.

[0100] In one embodiment, when performing an iterative reread operation, the memory controller 211 determines the corresponding target voltage adjustment level based on the current level number, and adjusts the target read reference voltage of the corresponding target bit page type in the reference voltage group based on the target voltage adjustment level. For example, suppose the memory controller 211 needs to adjust the read reference voltage RV1 used to read data of the first bit page type BP1, and the voltage adjustment level corresponding to the current level number is 0x06 (hexadecimal). Since this voltage adjustment level is in the positive offset range (0x01-0x7F), the memory controller 211 will increase the voltage value of RV1 by 0.12 volts (0.02 volts × 6). Conversely, if the voltage adjustment level is 0xF9 (hexadecimal, i.e., 249 in decimal), since this value is in the negative offset range (0x80-0xFF), the memory controller 211 will decrease the target read reference voltage by 1.4 volts (0.02 volts × [249-256]).

[0101] The memory controller 211 then uses the adjusted reference voltage group to reread the target physical page to obtain the reread target data containing multiple reread bit page data corresponding to the multiple bit page types and the number of reread error bits (e.g., error correction status) corresponding to each reread bit page data. If the number of reread error bits still exceeds the preset error bit threshold (e.g., when the error correction status is characterized as unsuccessful error correction), the memory controller 211 selects the next gear number as the new current gear number to perform another round of iterative rereading operations until the original data stored in the target physical page is successfully obtained or all available gear numbers have been tried.

[0102] In one embodiment, the memory controller 211, in addition to maintaining the voltage level table, can also establish a corresponding sorting table. This sorting table records the priority information of each level number, where the priority information can be determined based on various factors, such as the number of successful rereads. By maintaining this independent sorting table, the order in which the level numbers are used can be dynamically adjusted while keeping the original voltage level table stable.

[0103] Specifically, when the memory controller 211 needs to perform an iterative reread operation, it first queries the sorting table to obtain the highest priority level number, and then retrieves the voltage level information corresponding to that level number from the voltage level table. This separate design allows the system to flexibly adjust the reread strategy without affecting the basic voltage level data.

[0104] After a successful reread operation, the memory controller 211 updates the priority information of the slot number in the sorting table. For example, it can increase the number of successful rereads and rearrange the priorities of each slot number according to the updated number of successful rereads, or it can directly set the priority of the successfully reread slot number to the highest to update the sorting table. This dynamic update mechanism ensures that slot numbers with a high success rate are given priority in subsequent reread operations.

[0105] In one embodiment, the memory controller 211 implements a gear number management mechanism based on a sorting table. This mechanism optimizes the selection order of gear numbers during iterative reread operations by maintaining an independent sorting table, while maintaining the stability of the original voltage gear table.

[0106] Specifically, the memory controller 211 first establishes a corresponding sorting table based on the target voltage level table. This sorting table records the sorting information of each level number and prioritizes the level numbers based on this sorting information. For example, if the target voltage level table contains level numbers 0 to 7, the sorting table may arrange them into a priority sequence based on the historical performance of each level number: 3, 1, 4, 2, 6, 5, 7, 0 (e.g., level number 3 has the highest priority).

[0107] When performing iterative reread operations, the memory controller 211 does not directly use the gear number order in the target voltage gear table. Instead, it obtains a sorting table and selects the gear number according to the priority order recorded therein. For example, when starting a new iterative reread operation, the memory controller 211 first selects the highest priority gear number 3 in the sorting table as the current gear number; if the reread operation using gear number 3 fails, it selects the second highest priority gear number 1, and so on.

[0108] More importantly, after each iterative reread operation, the memory controller 211 dynamically updates the sorting information. Specifically, after performing an iterative reread operation using a certain current gear number, the memory controller 211 updates the sorting information of that gear number based on the reread result. For example, if the reread operation is successful, the success count of that gear number may be increased; conversely, if the reread fails, its priority may be decreased. Subsequently, the memory controller 211 adjusts the priority order of that current gear number in the sorting table based on the updated sorting information.

[0109] Through this dynamic management mechanism, the sorting table can continuously optimize the order of voltage level numbers based on actual operating experience, while the original voltage level table remains unchanged, continuing to provide basic voltage regulation level information. This separate design not only improves the efficiency of rereading operations but also enhances the maintainability of the system.

[0110] Figure 6 This is a schematic diagram illustrating the adjustment of the priority of the current gear number in the sorting table based on updated sorting information, according to an embodiment of the present invention.

[0111] In one embodiment, Figure 6 The diagram details how the memory controller 211 dynamically manages the priority of gear positions using a sorting table, while maintaining the number of successful rereads for each gear position. A complete priority update process is illustrated in the diagram.

[0112] Specifically, Figure 6 The upper area displays a voltage level table TB51 (labeled B61), which contains multiple voltage adjustment levels for the first bit page type (Lower page). The table records level numbers 0 to 8 (level number 0 is the preset level), and each level number corresponds to four voltage adjustment levels, used to adjust the read reference voltages RV1, RV4, RV6, and RV11, respectively.

[0113] As shown by arrow A61, the memory controller 211 establishes a sorting table based on the voltage level table TB51. This sorting table prioritizes each level based on the number of successful rereads (e.g., sorting information). Level 1 has the highest priority with "11" successful rereads; level 2 has the second highest priority with "10" successful rereads; level 3 has the third highest priority with "9" successful rereads, and so on, forming a priority order from high to low.

[0114] In actual operation, the memory controller 211 selected gear number 6 to perform iterative reread operation, and after adjusting the reference voltage group using the voltage adjustment gears corresponding to gear number 6 (Lower-R1:0x05, Lower-R4:0xFA, Lower-R6:0xFB, Lower-R11:0xF0), it successfully acquired the original data in the target physical page.

[0115] As indicated by arrow A62, after this successful reread operation, the memory controller 211 increments the successful reread count for slot number 6 by 1, updating it from "6" to "7" (the sorting information has been updated). This update triggers a reordering of priorities in the sorting table.

[0116] Ultimately, as shown by arrow A63, due to the increased number of successful rereads for gear number 6, its position in the new sorting table TB52 rises, placing it between gear numbers with "8" and "6" successful rereads. This dynamic adjustment ensures that gear numbers with higher success rates are prioritized in subsequent reread operations.

[0117] In the above embodiments, the memory controller 211 manages the priority of the voltage level numbers by maintaining an independent sorting table. However, in another embodiment, the memory controller 211 can also directly record and update the successful reread count information in the voltage level table, thereby optimizing the reread operation. This method directly links the voltage level information to its usage effect by adding a successful reread count field to the voltage level table, and then reorders the voltage level numbers based on actual operating experience.

[0118] Furthermore, since the data in the target physical page is stored in different bit page types of the storage unit, sorting tables can be established for different bit page types. For example, sorting tables can be established for the first bit page type (Lowerpage), the second bit page type (Middle page), the third bit page type (Upper page), and the fourth bit page type (eXtra page). During the rereading operation of the target bit page data, the corresponding sorting tables can be adjusted according to the bit page type to which the target bit page data belongs.

[0119] The following examples will detail how this method of directly recording the number of successful rereads in the voltage range table is implemented.

[0120] Figure 7 This is a schematic diagram illustrating the updating of the voltage range table after successfully acquiring the original data via a rereading operation, according to an embodiment of the present invention.

[0121] In one embodiment, such as Figure 7 As shown, the target voltage level table TB71 corresponding to the first bit page type BP1 (also known as the Lower page) contains multiple sets of voltage adjustment levels. Each set of voltage adjustment levels contains voltage adjustment level values ​​used to adjust the read reference voltages RV1, RV4, RV6, and RV11, and each set of voltage adjustment levels corresponds to a level number (e.g., 0 to 8). The memory controller 211 also records the number of successful rereads corresponding to each level number to indicate the number of times the original data was successfully obtained by performing iterative reread operations using that level number.

[0122] For example, when the memory controller 211 performs a read operation on a target physical page, if it finds that the target error bit count of the target bit page data corresponding to the first bit page type BP1 exceeds a preset error bit count threshold, the memory controller 211 will retrieve the target voltage level table TB71 corresponding to the first bit page type BP1. Then, the memory controller 211 will select a level number from the target voltage level table TB71, sorted in descending order of the number of successful rereads. For example... Figure 7As shown, since the number of successful rereads corresponding to gear number 1 is "11", which is the highest among all gear numbers, the memory controller 211 first selects gear number 1 as the current gear number.

[0123] The memory controller 211 then obtains the corresponding target voltage regulation level according to the current level number 1, namely, the voltage regulation level 0x06 for RV1, the voltage regulation level 0x04 for RV4, the voltage regulation level 0x00 for RV6, and the voltage regulation level 0xF9 for RV11. Based on these voltage regulation levels, the memory controller 211 adjusts the voltage values ​​of the read reference voltages RV1, RV4, RV6, and RV11 corresponding to the first bit page type BP1 in the reference voltage group (the read voltages for other bit page types remain unchanged), and uses the adjusted reference voltage group to reread the target physical page to obtain the reread target data and the corresponding number of reread error bits.

[0124] If the number of reread error bits in the reread bit page data corresponding to the first bit page type BP1 (target bit page type) still exceeds the preset error bit threshold, the memory controller 211 will select the gear number 2 with the second highest number of successful rereads as the new current gear number, and use the corresponding voltage adjustment gear (RV1:0x00, RV4:0x04, RV6:0xFE, RV11:0xFA) to perform another round of iterative rereading operation. This process will continue until the number of reread error bits in all reread bit page data does not exceed the preset error bit threshold (e.g., the number of reread error bits in the reread bit page data of the first bit page type BP1 (target bit page type) does not exceed the preset error bit threshold), or all gear numbers in the target voltage gear table TB71 have been tried.

[0125] When the iterative reread operation successfully acquires the original data stored in the target physical page, the memory controller 211 updates the number of successful rereads of the current gear number that was successfully used, and re-sorts the gear numbers in the target voltage gear table TB71 in descending order based on the updated number of successful rereads, so that the gear numbers with higher number of successful rereads will be selected first for subsequent iterative reread operations.

[0126] Figure 4 This is a schematic diagram illustrating the segmentation of the original voltage level table based on bit page type according to an embodiment of the present invention.

[0127] In one embodiment, such as Figure 4As shown, the memory controller 211 can obtain the original voltage level table TB40, which contains multiple level data corresponding to multiple bit page types. In order to improve the reading speed of the target voltage level, the memory controller 211 can divide the original voltage level table TB40 into multiple voltage level tables according to the multiple level data corresponding to the multiple bit page types in the original voltage level table TB40.

[0128] Specifically, such as Figure 4 As shown by arrows A41, A42, A43 and A44, the memory controller 211 saves multiple voltage level data from the original voltage level table TB40 to voltage level tables of different bit page types.

[0129] For example, the range data corresponding to arrow A41 includes voltage adjustment ranges for adjusting the read reference voltages RV1, RV4, RV6, and RV11 of the first bit page type BP1, and is saved in the voltage range table TB41 corresponding to the first bit page type BP1; the range data corresponding to arrow A42 includes voltage adjustment ranges for adjusting the read reference voltages RV3, RV7, RV9, and RV13 of the second bit page type BP2, and is saved in the voltage range table TB42 corresponding to the second bit page type BP2; the range data corresponding to arrow A43 includes voltage adjustment ranges for adjusting the read reference voltages RV2, RV8, and RV14 of the third bit page type BP3, and is saved in the voltage range table TB43 corresponding to the third bit page type BP3; the range data corresponding to arrow A44 includes voltage adjustment ranges for adjusting the read reference voltages RV5, RV10, RV12, and RV15 of the fourth bit page type BP4, and is saved in the voltage range table TB44 corresponding to the fourth bit page type BP4.

[0130] In this way, when the memory controller 211 needs to perform an iterative reread operation on the target bit page data in the target physical page, it only needs to read the range data in the voltage range table corresponding to the target bit page type, instead of reading the complete original voltage range table TB40 as in the traditional method. For example, when the target bit page type is the first bit page type BP1, the memory controller 211 only needs to read the range data in the voltage range table TB41 to adjust the read voltage corresponding to the first bit page type BP1, thereby reducing the amount of data read and improving the speed of obtaining the target voltage range.

[0131] Figure 5 This is a schematic diagram illustrating the generation of voltage level tables corresponding to different bit page types via segmentation and deduplication operations according to an embodiment of the present invention.

[0132] In one embodiment, such as Figure 5As shown, the memory controller 211 can not only divide the original voltage level table TB50 into multiple voltage level tables, but also perform deduplication processing on these voltage level tables to improve the efficiency of reread operations.

[0133] Specifically, as shown by arrow A51, the memory controller 211 first extracts the voltage level data corresponding to the first bit page type BP1 from the original voltage level table TB50 into the voltage level table TB51. Similarly, as shown by arrows A52, A53, and A54, the memory controller 211 also extracts the voltage level data corresponding to the second bit page type BP2, the third bit page type BP3, and the fourth bit page type BP4 into the voltage level tables TB52, TB53, and TB54, respectively.

[0134] After acquiring these voltage level tables, the memory controller 211 performs deduplication on the level data in each voltage level table. Taking voltage level table TB51 as an example, the memory controller 211 detects that the level sub-data corresponding to level number 1 and level number 6 are exactly the same, that is, Lower-R1 is 0x06, Lower-R4 is 0x04, Lower-R6 is 0x00, and Lower-R11 is 0xF9. Since the content of these two sets of level sub-data is the same, during the deduplication process, the memory controller 211 only retains one set of level sub-data (in this example, retaining the level sub-data corresponding to level number 1).

[0135] As shown by arrow A55, after deduplication, the memory controller 211 renumbers the remaining voltage level sub-data in the voltage level table TB51 to generate a deduplicated voltage level table TB55. Similarly, as shown by arrow A56, the memory controller 211 also performs deduplication on the same voltage level sub-data (such as level number 3 and level number 8) in the voltage level table TB52, and renumbers the remaining voltage level sub-data to generate a deduplicated voltage level table TB56.

[0136] For voltage level table TB53, as shown by arrow A57, the memory controller 211 did not identify any identical level sub-data, so it renumbered all the level sub-data to generate voltage level table TB57. Finally, as shown by arrow A58, the memory controller 211 also performed the same deduplication process on voltage level table TB54 to generate a deduplicated voltage level table TB58.

[0137] In this way, the memory controller 211 also completes the initialization operation of multiple voltage level tables corresponding to different bit page types.

[0138] Through this segmentation and deduplication process, the memory controller 211 not only reduces the amount of data when reading the voltage level table, but also avoids repeatedly trying the same level sub-data in iterative reread operations, thereby improving the efficiency of the reread operation. For example, when the target bit page data corresponding to the first bit page type BP1 needs to be reread, the memory controller 211 only needs to use the level sub-data in the deduplicated voltage level table TB55 to adjust the read reference voltage, without having to repeatedly try the same level combination.

[0139] Figure 7 This is a schematic diagram illustrating the updating of the voltage range table after successfully acquiring the original data via a rereading operation, according to an embodiment of the present invention.

[0140] In one embodiment, for example, such as Figure 7 As shown, when the memory controller 211 performs a read operation on the target physical page, if it finds that the number of target error bits of the target bit page data corresponding to the first bit page type BP1 exceeds the preset error bit threshold, the memory controller 211 will obtain the target voltage level table TB71 corresponding to the first bit page type BP1.

[0141] In this embodiment, the target voltage level table TB71 records the number of successful rereads corresponding to each level number. For example, the number of successful rereads for level number 1 is "11", the number of successful rereads for level number 2 is "10", and so on. The number of successful rereads for each level number is accumulated and updated after the corresponding reread operation is successful. For example, if the original data is successfully obtained after performing the iterative reread operation on the target physical page through the current level number, the memory controller 211 accumulates the number of successful rereads for the corresponding current level number.

[0142] Based on the number of successful rereads, the memory controller 211 sorts all the gear numbers in the target voltage gear table TB71 in descending order. The gear number at the top of the list reflects the highest success rate of its reread operation. Therefore, in this embodiment, the memory controller 211 will first select the first gear number (e.g., gear number 1) as the current gear number to perform iterative reread operations according to the sorting order.

[0143] Suppose that after trying several voltage levels, the memory controller 211 performs an iterative reread operation on the target physical page using voltage level 6 (the corresponding voltage levels are Lower-R1:0x05, Lower-R4:0xFA, Lower-R6:0xFB, Lower-R11:0xF0), and successfully acquires the original data stored in the target physical page. At this point, the memory controller 211 will increment the number of successful rereads for voltage level 6 from "6" to "7".

[0144] As shown by arrow A71, after updating the successful reread count for gear number 6, the memory controller 211 updates the target voltage gear table according to the successful reread count of each gear number, generating an updated target voltage gear table TB72. As shown by arrow A72, since the successful reread count ("7") for gear number 6 is now greater than the successful reread count ("6") for gear number 5, gear number 6 is moved before gear number 5 in the updated target voltage gear table TB72. This sorting ensures that in subsequent iterative reread operations, gear numbers with higher successful reread counts are selected first, thereby improving the success rate of reread operations.

[0145] Figure 8 This is a schematic diagram of a voltage level table corresponding to different programming erase cycle intervals belonging to the same bit page type, as shown in an embodiment of the present invention.

[0146] In one embodiment, such as Figure 8 As shown, the memory controller 211 can establish corresponding voltage level tables for different programming and erasing cycle intervals. Taking the first bit page type BP1 as an example, voltage level table TB81 corresponds to the interval of 0 to 500 programming and erasing cycles, voltage level table TB82 corresponds to the interval of 501 to 1000 programming and erasing cycles, voltage level table TB83 corresponds to the interval of 1001 to 1500 programming and erasing cycles, and so on.

[0147] As can be seen from these voltage level tables, the voltage adjustment range increases with the number of program erase cycles. For example, for the read reference voltage RV1 (Lower-R1), the voltage adjustment range in voltage level table TB81 is 0x02 to 0x06, in voltage level table TB82 it is 0x04 to 0x08, and in voltage level table TB83 it is 0x06 to 0x0E. This reflects the characteristic that the memory cell requires a larger voltage adjustment range as the number of uses increases.

[0148] In the process of establishing these voltage level tables, the memory controller 211 may perform the following steps:

[0149] First, determine how to divide the program's erase loop interval, such as dividing it into intervals of 500 iterations;

[0150] An initial voltage level table is established for each interval, and a preset voltage adjustment range can be used.

[0151] In actual use, the voltage level table for each range is updated by the results of iterative rereading operations, and the number of successful rereads for each level number is maintained.

[0152] Periodically sort the voltage range numbers in the voltage range table for each range in descending order based on the number of successful rereads.

[0153] When the memory controller 211 needs to perform a read operation on a target physical page and finds that the target error bit count of the target bit page data exceeds a preset error bit count threshold, the memory controller 211 first obtains the number of program erase cycles for the target physical page. For example, if the obtained number of program erase cycles is 750, the memory controller 211 determines that the target program erase cycle range is 501 to 1000 cycles. Subsequently, based on the target bit page type (such as the first bit page type BP1) and the target program erase cycle range (501 to 1000 cycles), the memory controller 211 obtains the voltage level table TB82 from multiple voltage level tables corresponding to the first bit page type BP1 as the target voltage level table, and uses the voltage adjustment level in the target voltage level table to perform iterative reread operations.

[0154] In one embodiment, during actual use, the memory controller 211 needs to dynamically establish voltage level tables corresponding to different programming erase cycle intervals based on the number of programming erase cycles of the target physical page. When a new voltage level table corresponding to a new programming erase cycle interval needs to be established, the memory controller 211 can refer to the voltage level tables already established for adjacent intervals to improve the initial availability of the new voltage level table.

[0155] For example, suppose the memory controller 211 has established and maintained a voltage level table TB81 for the program erase cycle range of 0 to 500 cycles. When the memory controller 211 needs to perform a reread operation on a target physical page with a program erase cycle range of 501 to 1000 cycles, it finds that the voltage level table for this range has not yet been established.

[0156] In this scenario, since the program erase cycle interval with 501 to 1000 cycles is adjacent to the program erase cycle interval with 0 to 500 cycles, the memory controller 211 can select the voltage level table of the program erase cycle interval with 0 to 500 cycles as the initial content of the newly created voltage level table. For example, the memory controller 211 can select to copy the contents of voltage level table TB81 as the initial content of voltage level table TB82 for the program erase cycle interval with 501 to 1000 cycles.

[0157] Subsequently, during the reread operation of the target physical pages within the program erase cycle interval with 501 to 1000 program erase cycles, the memory controller 211 accumulates the successful reread counts of the successfully used voltage level numbers based on the actual reread results, and sorts the voltage level numbers in the voltage level table TB82 in descending order, thereby gradually optimizing the voltage level table for that program erase cycle interval. In this way, the memory controller 211 does not need to build a new voltage level table from scratch, but can use the already optimized voltage level tables of adjacent program erase cycle intervals as a basis to quickly build a voltage level table suitable for the new program erase cycle interval, improving the system's adaptability and efficiency. It should be noted that, in another embodiment, the memory controller 211 also copies the successful reread counts corresponding to all the voltage level numbers in the voltage level table for the 0 to 500 program erase cycle intervals, recording them as the initial successful reread counts for all the voltage level numbers in the voltage level table for the 501 to 1000 program erase cycle intervals, using them as initial values. By inheriting these statistical data, the newly created voltage level table can have a relatively reasonable level number sorting in the initial stage, thereby improving the success rate of early reread operations.

[0158] In one embodiment, when the memory controller 211 successfully obtains the original data after performing an iterative reread operation on the target physical page using the current gear number, the memory controller 211 not only accumulates the successful reread count for the current gear number, but also obtains the program erase cycle count for the target physical page. For example, suppose the memory controller 211 successfully performs an iterative reread operation using the voltage adjustment gears (Lower-R1:0x05, Lower-R4:0x03, Lower-R6:0xFE, Lower-R11:0xFC) corresponding to gear number 2 in the voltage gear table TB82, and the obtained program erase cycle count for the target physical page is 750.

[0159] At this point, the memory controller 211 determines the target programming erase cycle interval (501 to 1000 cycles) based on the acquired programming erase cycle count (750 times), and confirms the voltage level table TB82 as the target voltage level table to be updated based on the target bit page type (e.g., first bit page type BP1) and the target programming erase cycle interval. Next, after accumulating the successful reread count of level number 2, the memory controller 211 sorts the level numbers in descending order according to the number of successful rereads for each level number in the target voltage level table TB82 to obtain the updated target voltage level table TB82. This ensures that when performing iterative reread operations on target physical pages within the programming erase cycle count range of 501 to 1000, level numbers with higher successful reread counts are preferentially selected.

[0160] This method of updating the voltage level table based on the programmable erase cycle intervals allows the memory controller 211 to maintain the optimal voltage adjustment sequence for memory cells with different usage levels, thereby improving the efficiency of reread operations. For example, compared to the interval with a lower number of programmable erase cycles (e.g., 0 to 500 times), the interval with a higher number of programmable erase cycles (e.g., 1001 to 1500 times) may require a larger voltage adjustment range. By maintaining voltage level tables for these intervals separately, the appropriate voltage adjustment level can be selected more accurately for memory cells with different usage levels.

[0161] In several embodiments, in addition to maintaining the voltage level table based on the number of programmed erase cycles, the memory controller 211 can also consider other factors that affect the critical voltage distribution of memory cells and establish a more detailed voltage level table grouping for each bit page type.

[0162] For example, in one embodiment, since the critical voltage distribution of the memory cells shifts with changes in operating temperature, the memory controller 211 can maintain a voltage level table for each temperature range (e.g., 0-25°C, 26-50°C, 51-75°C, etc.). When the number of erroneous bits of the target bit page data exceeds a preset erroneous bit threshold within a certain temperature range (e.g., 40°C), the memory controller 211 will preferentially select the voltage level table corresponding to that temperature range (26-50°C) to perform an iterative reread operation.

[0163] Furthermore, in another embodiment, considering that data retention time affects the critical voltage distribution of the storage cells, the memory controller 211 can record the data write timestamp for each physical page and select the appropriate voltage level table based on the data storage time (e.g., 0-30 days, 31-90 days, 91-180 days, etc.). For example, for data stored for more than 90 days, a larger voltage adjustment range may be needed to compensate for the natural drift of the critical voltage.

[0164] In another embodiment, since memory cells at different locations within the same memory chip may have performance differences, the memory controller 211 can also maintain different voltage level tables based on the physical block's location within the chip. For example, memory cells located at the chip edge may require different voltage adjustment strategies than those in the central region.

[0165] In another embodiment, the memory controller 211 may also maintain a dedicated voltage level table for different data writing modes. For example, sequentially written data blocks may exhibit different critical voltage distribution characteristics than randomly written data blocks, thus requiring different combinations of voltage levels to perform reread operations.

[0166] To implement these grouping methods, the memory controller 211 needs to record and maintain corresponding attribute information. For example, temperature range identifiers, data write timestamps, physical location information, and write mode identifiers can be recorded in the management information of the target physical page. When a reread operation needs to be performed on the target physical page, the memory controller 211 can select the most suitable voltage level table based on this attribute information, thereby improving the accuracy and efficiency of the reread operation.

[0167] Figure 9 This is a flowchart illustrating a data reading method according to an embodiment of the present invention.

[0168] In one embodiment, such as Figure 9 As shown, the data reading method of the present invention includes the following steps:

[0169] First, in step S910, the memory controller 211 performs a read operation on the target physical page of the rewritable non-volatile memory module 220 to obtain target data containing multiple bit page data corresponding to multiple bit page types and the number of error bits for each bit page data. For example, if the target physical page uses a QLC type memory cell, the memory controller 211 can read the bit page data corresponding to the first bit page type BP1 to the fourth bit page type BP4, and calculate the number of error bits for each bit page data through error detection and correction coding. This allows the memory controller 211 to promptly detect the target bit page data that needs to be reread.

[0170] Next, in step S920, if the target error bit count of the target bit page data in the plurality of bit page data exceeds a preset error bit count threshold, a target voltage level table corresponding to the target bit page type of the target bit page data is obtained. For example, if it is found that the error bit count of the bit page data corresponding to the first bit page type BP1 exceeds the preset error bit count threshold, and the program erase cycle count of the target physical page is 750 times, the memory controller 211 will obtain the voltage level table TB82 corresponding to the program erase cycle interval 501 to 1000 times as the target voltage level table. This method of selecting the voltage level table based on bit page type and program erase cycle interval can more accurately select the appropriate voltage level for memory cells with different usage levels.

[0171] Then, in step S930, a gear number is selected as the current gear number according to the order of multiple gear numbers in the target voltage level table, so as to perform an iterative reread operation on the target physical page using the current gear number. For example, the memory controller 211 will preferentially select the gear number with the highest number of successful rereads in the voltage level table TB82, and use the voltage adjustment gear corresponding to the gear number (such as Lower-R1:0x04, Lower-R4:0x02, Lower-R6:0x00, Lower-R11:0xFD) to adjust the read reference voltages RV1, RV4, RV6, and RV11 to perform the iterative reread operation. This method of selecting the gear number based on the number of successful rereads can improve the success rate of the reread operation.

[0172] Finally, in step S940, if the number of reread error bits for each reread bitpage does not exceed the preset error bit threshold, it is determined that the original data stored in the target physical page has been successfully acquired, the iterative reread operation ends, and the target voltage level table is updated based on the current level number. For example, when the original data is successfully acquired using level number 2, the memory controller 211 increments the successful reread count of that level number by 1 and reorders the level numbers in the voltage level table TB82 according to the updated successful reread count. This dynamic update mechanism allows the voltage level table to be continuously optimized to adapt to the usage characteristics of the storage unit.

[0173] However, Figure 9 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 9 Each step can be implemented as multiple pieces of code or circuits; this invention is not limited thereto. Furthermore, Figure 9 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0174] This embodiment also provides a computer program product, including computer-readable code or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is executed in the processor of a host system, the processor performs the steps of the above-described data reading method. This computer program product can be implemented specifically through hardware, firmware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied as a computer storage medium; in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0175] As can be seen from the above embodiments, the data reading method and its memory controller provided by the present invention mainly have the following technical effects:

[0176] First, this invention maintains separate voltage level tables for different bit page types, enabling the memory controller to select the most suitable voltage level for each bit page type to perform a reread operation. For example, when the number of erroneous bits in the target bit page data corresponding to the first bit page type BP1 exceeds a preset erroneous bit threshold, the voltage level table for the first bit page type BP1 can be directly obtained without considering the voltage levels for other bit page types, thereby improving the accuracy of the reread operation.

[0177] Secondly, this invention establishes an adaptive voltage adjustment mechanism by recording the number of successful rereads for each gear position number and sorting the gear positions in descending order based on the number of successful rereads. When the voltage adjustment gear corresponding to a certain gear position number is successfully used for a reread operation, the priority of that gear position number will be increased accordingly, ensuring that the more likely voltage adjustment gear is used in subsequent reread operations. This significantly reduces the number of reread operation attempts.

[0178] Furthermore, this invention takes into account that the usage level of a memory cell affects its voltage adjustment requirements; therefore, it maintains an independent voltage level table for different program-erase cycle intervals. This fine-grained management approach allows the memory controller to select the appropriate voltage level table based on the actual usage level of the target physical page, improving the accuracy of reread operations. For example, a larger voltage adjustment range can be used for memory cells with a high number of program-erase cycles, while a relatively mild voltage adjustment strategy can be adopted for memory cells with low usage.

[0179] Furthermore, by segmenting and deduplicating the voltage level table, this invention not only reduces the amount of data read when reading the voltage level table but also avoids repeatedly trying the same voltage level combination during rereading operations. This optimization significantly improves the speed at which the memory controller acquires the target voltage level.

[0180] In summary, this invention, through a refined voltage level table management mechanism combined with dynamic updating and optimization strategies, improves the efficiency of reread operations while enhancing the data read reliability of the storage device. These technical effects not only reduce the processing burden on the memory controller but also extend the lifespan of the storage device.

[0181] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data reading method, applicable to a memory controller of a storage device configured with a rewritable non-volatile memory module, characterized in that, The method includes: A read operation is performed on the target physical page of the rewritable non-volatile memory module to obtain target data containing multiple bit page data corresponding to multiple bit page types and the error correction status of each bit page data, wherein each storage unit of the target physical page can store multiple bits corresponding to the multiple bit page types respectively; If the error correction status of the target bit page data in the plurality of bit page data is characterized as unsuccessful error correction: Obtain the target voltage level table corresponding to the target bit page type of the target bit page data; According to the order of the multiple range numbers in the target voltage range table, a range number is sequentially selected as the current range number. An iterative reread operation is then performed on the target physical page using the voltage adjustment range corresponding to the current range number. This yields reread target data containing multiple reread bit page data corresponding to the multiple bit page types, and the error correction status of each reread bit page data. If the error correction status of each reread bit page data is characterized as successful error correction, it is determined that the original data stored in the target physical page has been successfully obtained, and the sorting information corresponding to the current gear number is updated. If the original data is successfully obtained after performing the iterative reread operation on the target physical page using the current gear number, the number of successful rereads for the corresponding current gear number is accumulated, and the number of programmable erase loops for the target physical page is obtained. The target programming erase cycle interval is determined based on the number of programming erase cycles, and the target voltage level table corresponding to the target programming erase cycle interval is obtained from multiple voltage level tables corresponding to the target bit page type based on the target bit page type and the target programming erase cycle interval. The step of updating the sorting information corresponding to the current gear position number includes: after updating the number of successful rereads of the current gear position number, sorting the multiple gear position numbers in descending order according to the size of the number of successful rereads of each gear position number, so as to obtain the updated target voltage gear table. The gear number with the highest number of successful rereads will be selected first to perform the iterative reread operation.

2. The data reading method according to claim 1, characterized in that, After obtaining the error correction status of the target reread data and the corresponding reread bit pages, the method further includes: If the error correction status of each reread bit page data is characterized as unsuccessful error correction, then the next gear number is selected as the new current gear number to perform the iterative reread operation, and so on, until a gear number is found that makes the error correction status of each reread bit page data characterized as successful error correction.

3. The data reading method according to claim 1, characterized in that, The iterative reread operation includes: Determine the target voltage regulation level corresponding to the target voltage level table based on the current level number; Based on the target voltage adjustment level, adjust the target read reference voltage in the reference voltage group corresponding to the target bit page type; and The target physical page is reread using the adjusted reference voltage group to obtain reread target data containing multiple reread bit page data corresponding to the multiple bit page types and the error correction status of each reread bit page data.

4. The data reading method according to claim 1, characterized in that, Also includes: A sorting table is established based on the target voltage level table, and the sorting table prioritizes each level number according to the sorting information of each level number. The step of sequentially selecting a gear number as the current gear number based on the order of multiple gear numbers in the target voltage gear table includes: Obtain the sorting table, and select a gear number as the current gear number according to the priority of each gear number in the sorting table. The step of updating the sorting information corresponding to the current gear number includes: The sorting information of the current gear position number is updated, and the priority of the current gear position number in the sorting table is adjusted according to the updated sorting information.

5. The data reading method according to claim 1, characterized in that, The method further includes: When a new voltage level table corresponding to a new programmable erase cycle interval needs to be established, if one or more adjacent voltage level tables corresponding to one or more adjacent programmable erase cycle intervals adjacent to the new programmable erase cycle interval have already been established, one of the one or more adjacent voltage level tables is copied as the initial content of the new voltage level table.

6. The data reading method according to claim 1, characterized in that, The method further includes: Obtain the original voltage range table; Based on the multiple voltage level data corresponding to the multiple bit page types in the original voltage level table, the original voltage level table is segmented to obtain multiple voltage level tables corresponding to the multiple bit page types, wherein each voltage level table has the level data of the corresponding bit page type, and the target voltage level table is one or more of the multiple voltage level tables.

7. The data reading method according to claim 6, characterized in that, The method further includes: After obtaining the multiple voltage level tables, the multiple level sub-data of the level data in each voltage level table are deduplicated, including: Obtain multiple target gear position sub-data with identical content from the multiple gear position sub-data, wherein each gear position sub-data corresponds to a different original gear position number in the original voltage gear position table; and Only one target gear position sub-data is retained from the plurality of target gear position sub-data; and After the deduplication process is completed, multiple gear numbering is assigned to the multiple remaining gear sub-data to obtain the multiple voltage gear tables corresponding to the multiple bit page types.

8. A memory controller for controlling a storage device configured with a rewritable non-volatile memory module, characterized in that, The memory controller includes: A memory interface control circuit is provided for electrical connection to the rewritable non-volatile memory module; and A processor, electrically connected to the memory interface control circuit, wherein the processor is configured to: A read operation is performed on the target physical page of the rewritable non-volatile memory module to obtain target data containing multiple bit page data corresponding to multiple bit page types and the error correction status of each bit page data, wherein each storage unit of the target physical page can store multiple bits corresponding to the multiple bit page types respectively; If the error correction status of the target bit page data in the plurality of bit page data is characterized as unsuccessful error correction: Obtain the target voltage level table corresponding to the target bit page type of the target bit page data; According to the order of the multiple range numbers in the target voltage range table, a range number is sequentially selected as the current range number. An iterative reread operation is then performed on the target physical page using the voltage adjustment range corresponding to the current range number. This yields reread target data containing multiple reread bit page data corresponding to the multiple bit page types, and the error correction status of each reread bit page data. If the error correction status of each reread bit page data is characterized as successful error correction, it is determined that the original data stored in the target physical page has been successfully obtained, and the sorting information corresponding to the current gear number is updated. If the original data is successfully obtained after performing the iterative reread operation on the target physical page using the current gear number, the number of successful rereads for the corresponding current gear number is accumulated, and the number of programmable erase loops for the target physical page is obtained. The target programming erase cycle interval is determined based on the number of programming erase cycles; and the target voltage level table corresponding to the target programming erase cycle interval is obtained from multiple voltage level tables corresponding to the target bit page type based on the target bit page type. The updating of the sorting information corresponding to the current gear position number includes: after updating the number of successful rereads of the current gear position number, sorting the multiple gear position numbers in descending order according to the size of the number of successful rereads of each gear position number, so as to obtain the updated target voltage gear table. The gear number with the highest number of successful rereads will be selected first to perform the iterative reread operation.

9. The memory controller according to claim 8, characterized in that, The processor is also configured to: If the error correction status of each reread bit page data is characterized as unsuccessful error correction, then the next gear number is selected as the new current gear number to perform the iterative reread operation, and so on, until a gear number is found that makes the error correction status of each reread bit page data characterized as successful error correction.

10. The memory controller according to claim 8, characterized in that, The iterative reread operation includes: Determine the target voltage regulation level corresponding to the target voltage level table based on the current level number; Based on the target voltage adjustment level, adjust the target read reference voltage in the reference voltage group corresponding to the target bit page type; and The target physical page is reread using the adjusted reference voltage group to obtain reread target data containing multiple reread bit page data corresponding to the multiple bit page types and the error correction status of each reread bit page data.

11. The memory controller according to claim 8, characterized in that, The processor is also configured to: A sorting table is established based on the target voltage level table, and the sorting table prioritizes each level number according to the sorting information of each level number. Obtain the sorting table, and sequentially select a gear number as the current gear number according to the priority of each gear number in the sorting table; and The sorting information of the current gear position number is updated, and the priority of the current gear position number in the sorting table is adjusted according to the updated sorting information.

12. The memory controller according to claim 8, characterized in that, The processor is also configured to: When a new voltage level table corresponding to a new programmable erase cycle interval needs to be established, if one or more adjacent voltage level tables corresponding to one or more adjacent programmable erase cycle intervals adjacent to the new programmable erase cycle interval have already been established, one of the one or more adjacent voltage level tables is copied as the initial content of the new voltage level table.

13. The memory controller according to claim 8, characterized in that, The processor is also configured to: Obtain the original voltage range table; and Based on the multiple voltage level data corresponding to the multiple bit page types in the original voltage level table, the original voltage level table is segmented to obtain multiple voltage level tables corresponding to the multiple bit page types, wherein each voltage level table has the level data of the corresponding bit page type, and the target voltage level table is one or more of the multiple voltage level tables.

14. The memory controller according to claim 13, characterized in that, The processor is also configured to: After obtaining the multiple voltage level tables, the multiple level sub-data of the level data in each voltage level table are deduplicated, including: Obtain multiple target gear sub-data with the same content from the multiple gear sub-data, wherein each gear sub-data corresponds to a different original gear number in the original voltage gear table; Only one target gear position sub-data is retained from the plurality of target gear position sub-data; and After the deduplication process is completed, multiple gear numbering is assigned to the multiple remaining gear sub-data to obtain the multiple voltage gear tables corresponding to the multiple bit page types.

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