Data processing method and equipment

Abstract

The embodiment of the invention provides a data processing method and equipment, the method is applied to data storage equipment, and the data storage equipment comprises an extended memory; the method comprises the steps that a data operation request sent by a central processing unit (CPU) is received, the data operation request comprises an operation type and a to-be-operated address, a memory unit corresponding to the to-be-operated address is a memory unit in a local memory included in computing equipment to which the CPU belongs, and the operation type comprises data storage or data reading; determining a memory state of a memory unit corresponding to the address to be operated, wherein the memory state is a fault state or a normal state; and if the memory state is the fault state, storing data in the extended memory, or reading data from the extended memory. The method can improve the memory utilization rate of the computing device.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of server technology, and in particular, to a data processing method and device. Background Art

[0002] Reliability, availability and serviceability (RAS) of memory may be an important factor affecting the reliability of a computing device. For example, the computing device may be a server.

[0003] Currently, the RAS performance of the memory can be improved by setting part of the memory space in the computing device as the spare memory space. However, setting part of the memory space in the computing device as the spare memory space reduces the maximum available capacity of the memory in the computing device, resulting in low memory utilization of the computing device. Summary of the invention

[0004] The embodiments of the present application provide a data processing method and device to solve the technical problem of low memory utilization of computing devices.

[0005] In a first aspect, an embodiment of the present application provides a data processing method, which is applied to a data storage device, wherein the data storage device includes an extended memory; the method includes:

[0006] Receive a data operation request sent by a central processing unit (CPU), wherein the data operation request includes an operation type and an address to be operated, wherein the memory unit corresponding to the address to be operated is a memory unit in a local memory included in a computing device to which the CPU belongs, and the operation type includes storing data or reading data;

[0007] Determine a memory state of a memory unit corresponding to the address to be operated, wherein the memory state is a fault state or a normal state;

[0008] If the memory state is the fault state, data is stored in the extended memory or data is read from the extended memory.

[0009] In the above scheme, the data storage device can determine the memory status of the memory unit corresponding to the address to be operated of the data operation request; if the memory status is a fault state, the data storage device can store data in the extended memory or read data from the extended memory. In the above method, the extended memory in the data storage device can be used as a backup memory for the local memory, avoiding the use of the memory unit in the local memory as a backup memory unit. Through the above method, the local memory utilization rate can be improved while improving the RAS performance of the local memory of the computing device.

[0010] In a possible implementation, storing data in the extended memory or reading data from the extended memory includes:

[0011] Determine at least one spare address corresponding to the address to be operated, where the memory unit corresponding to the spare address is a memory unit in the extended memory;

[0012] The to-be-stored data corresponding to the operation request is stored in the memory unit corresponding to the spare address, or the to-be-read data corresponding to the operation request is read from the memory unit corresponding to the spare address.

[0013] In the above scheme, the data to be stored can be stored in the memory unit corresponding to the standby address, or the data to be read corresponding to the operation request can be read from the memory unit corresponding to the standby address. Among them, the memory unit corresponding to the standby address is a memory unit in the extended memory. Through the above scheme, the purpose of storing data in the extended memory or reading data from the extended memory is achieved.

[0014] In a possible implementation, the determining the standby address corresponding to the address to be operated includes:

[0015] Acquire an address mapping relationship between the local memory and the extended memory, the address mapping relationship comprising at least one first address and at least one second address corresponding to each first address, the first address being the address of the memory unit in the local memory, and the second address being the address of the memory unit in the extended memory;

[0016] Determine a target first address corresponding to the address to be operated, and determine at least one target second address corresponding to the target first address;

[0017] The at least one target second address is determined to be the at least one spare address.

[0018] In the above solution, the standby address corresponding to the address to be operated can be determined according to the address mapping relationship, thereby achieving the purpose of determining the standby address.

[0019] In a possible implementation, determining the memory state of the memory unit corresponding to the address to be operated includes:

[0020] Obtaining a fault table, the fault table being used to store target fault addresses of memory cells in the local memory where the number of times that repairable errors occur is greater than or equal to a preset threshold;

[0021] If the fault table is empty, determining that the memory state of the memory unit corresponding to the address to be operated is a normal state;

[0022] If the fault table is not empty, the memory state of the memory unit corresponding to the address to be operated is determined according to the fault table.

[0023] In the above solution, the memory state of the memory unit corresponding to the address to be operated can be determined according to the fault table, thereby achieving the purpose of determining the memory state of the memory unit corresponding to the address to be operated.

[0024] In a possible implementation, the fault table includes a data state of the target fault address; and determining the memory state of the memory unit corresponding to the address to be operated according to the fault table includes:

[0025] Determine whether the fault table includes the address to be operated;

[0026] If so, determining the memory state of the memory unit corresponding to the address to be operated according to the data state of the address to be operated;

[0027] If not, it is determined that the memory state of the memory unit corresponding to the address to be operated is a normal state.

[0028] In the above scheme, the memory state of the memory unit corresponding to the address to be operated can be determined according to the data state of the address to be operated in the fault table, thereby achieving the purpose of determining the memory state of the memory unit corresponding to the address to be operated.

[0029] In a possible implementation, the data state is an uncompleted migration state or a completed migration state; and determining the memory state of the memory unit corresponding to the address to be operated according to the data state of the address to be operated includes:

[0030] If the data state of the address to be operated is an uncompleted migration state, determining that the memory state of the memory unit corresponding to the address to be operated is a normal state;

[0031] If the data state of the address to be operated is a migration completion state, it is determined that the memory state of the memory unit corresponding to the address to be operated is a failure state.

[0032] In the above scheme, the memory state of the memory unit corresponding to the address to be operated can be determined according to the data state of the address to be operated in the fault table, thereby achieving the purpose of determining the memory state of the memory unit corresponding to the address to be operated.

[0033] In a possible implementation, the method further includes:

[0034] If the memory state is the normal state, data is stored in the memory unit corresponding to the address to be operated, or data is read from the memory unit corresponding to the address to be operated.

[0035] In the above scheme, data can be read from a memory unit whose memory state is a normal state, or data can be stored in a memory unit whose memory state is a normal state, thereby achieving the purpose of storing data or reading data.

[0036] In a possible implementation, the memory unit is any one of the following: the entire memory, a physical memory array, or a memory particle.

[0037] In the above solution, the memory unit may be the entire memory, a physical memory array, or a memory particle, which can improve the reliability of memory units of different granularities.

[0038] In a possible implementation, the method further includes:

[0039] Acquire from the CPU a target fault address of a target memory unit in the local memory where a repairable error occurs;

[0040] Determining the number of times that a repairable error occurs in the target memory unit according to the target fault address;

[0041] If the number is greater than or equal to a preset threshold, the target fault address is stored in a fault table.

[0042] In the above scheme, the target fault address where the number of repairable errors exceeds a preset threshold can be recorded in the fault table, so that the data storage device can determine the memory state of the memory unit corresponding to the address to be operated according to the fault table.

[0043] In a possible implementation, the memory unit is a physical memory array or a memory particle; after storing the target fault address in the fault table, the method further includes:

[0044] Acquire an address mapping relationship between the local memory and the extended memory;

[0045] Determine, according to the address mapping relationship, an address to be migrated corresponding to the target fault address, wherein the address to be migrated is an address of a memory unit in the extended memory;

[0046] The data stored in the target memory unit is migrated to the memory unit corresponding to the address to be migrated.

[0047] In the above solution, if the memory unit is a physical memory array or a memory particle, and the memory address corresponding to the memory unit is the target fault address, the data in the memory unit can be migrated to the extended memory, so that the data in the memory unit has higher reliability.

[0048] In a possible implementation, storing data in a memory unit corresponding to the address to be operated, or reading data from a memory unit corresponding to the address to be operated, includes:

[0049] storing data in a memory unit corresponding to the address to be operated through a first memory controller corresponding to the local memory, or reading data from a memory unit corresponding to the address to be operated through the first memory controller;

[0050] The storing of data in the extended memory or reading of data from the extended memory comprises:

[0051] The data is stored in the extended memory through a second memory controller corresponding to the extended memory, or data is read from the extended memory through the second memory controller.

[0052] In the above scheme, data can be stored in the memory unit corresponding to the address to be operated, or data can be read from the memory unit corresponding to the address to be operated, through the first memory controller, and data can be stored in the extended memory, or data can be read from the extended memory, thereby achieving the purpose of storing or reading data.

[0053] In a possible implementation, the memory unit is the entire memory; and storing data in the memory unit corresponding to the address to be operated includes:

[0054] The data to be stored corresponding to the operation request is stored in the memory unit corresponding to the address to be operated, and the data to be stored is stored in the extended memory at the same time.

[0055] In the above solution, if the memory unit is the entire memory, the data to be stored can be stored in the memory unit corresponding to the address to be operated and the extended memory at the same time, so as to achieve the purpose of data mirroring storage.

[0056] In a possible implementation, the method further includes:

[0057] Acquire configuration information, wherein the configuration information includes addresses of each memory unit in the local memory, addresses of each memory unit in the extended memory, a security level of the local memory, and the number of extended memory units corresponding to each memory unit in the local memory, wherein the security level is a memory level, a physical memory array level, or a memory particle level, and the extended memory unit is a memory unit in the extended memory;

[0058] An address mapping relationship between the local memory and the extended memory is determined according to the security level and the quantity.

[0059] In the above scheme, the address mapping relationship between the local memory and the extended memory can be determined according to the security level of the local memory and the number of extended memory units corresponding to each memory unit, thereby achieving the purpose of determining the address mapping relationship.

[0060] In a possible implementation, determining the address mapping relationship between the local memory and the extended memory according to the security level and the quantity includes:

[0061] According to the security level, determining the memory unit as the entire memory, the physical memory array, or the memory particle;

[0062] Determining, in the extended memory, at least one of the extended memory cells for each memory cell in the local memory according to the number;

[0063] Determining a first address of each memory unit in the local memory and a second address of each of the extended memory units;

[0064] Each of the first addresses and at least one of the second addresses corresponding to each of the first addresses are stored in the address mapping relationship.

[0065] In the above solution, the correspondence between each memory unit in the local memory and the memory unit in the extended memory can be determined, thereby achieving the purpose of determining the address mapping relationship.

[0066] In a second aspect, an embodiment of the present application provides a data processing method, which is applied to a CPU, and the method includes:

[0067] Obtain a target fault address of a target memory unit where a repairable error occurs in the local memory;

[0068] Determining the number of times that a repairable error occurs in the target memory unit according to the target fault address;

[0069] If the number is greater than or equal to a preset threshold, the target fault address is sent to a data storage device.

[0070] In the above scheme, the CPU can determine the number of repairable errors that occur in the target memory unit, and when the number exceeds a preset threshold, send the target fault address to the data storage device so that the data storage device can store the target fault address in the fault table.

[0071] In a third aspect, an embodiment of the present application provides a data storage device, which is applied to a data storage device, wherein the data storage device includes an extended memory, and the device includes a receiving module, a fault decision module, and an operation module, wherein:

[0072] The receiving module is used to receive a data operation request sent by a central processing unit (CPU), wherein the data operation request includes an operation type and an address to be operated, the memory unit corresponding to the address to be operated is a memory unit in a local memory included in a computing device to which the CPU belongs, and the operation type includes storing data or reading data;

[0073] The fault decision module is used to determine the memory state of the memory unit corresponding to the address to be operated, and the memory state is a fault state or a normal state;

[0074] If the memory state is the fault state, the operation module is used to store data in the extended memory or read data from the extended memory.

[0075] In the above scheme, the data storage device can receive a data operation request sent by the CPU, the data operation request includes an operation type and an address to be operated, the operation type includes storing data or reading data; the memory state of the memory unit corresponding to the address to be operated can be determined; if the memory state is a fault state, the data storage device can store data in the extended memory or read data from the extended memory. In the above method, the extended memory in the data storage device can be used as a backup memory for the local memory, avoiding the use of the memory unit in the local memory as a backup memory unit. Through the above device, the local memory utilization rate can be improved while improving the RAS performance of the local memory of the computing device.

[0076] In a possible implementation, the operation module is specifically used to:

[0077] Determine at least one spare address corresponding to the address to be operated, where the memory unit corresponding to the spare address is a memory unit in the extended memory;

[0078] The to-be-stored data corresponding to the operation request is stored in the memory unit corresponding to the spare address, or the to-be-read data corresponding to the operation request is read from the memory unit corresponding to the spare address.

[0079] In the above scheme, the data to be stored can be stored in the memory unit corresponding to the standby address, or the data to be read corresponding to the operation request can be read from the memory unit corresponding to the standby address. Among them, the memory unit corresponding to the standby address is a memory unit in the extended memory. Through the above scheme, the purpose of storing data in the extended memory or reading data from the extended memory is achieved.

[0080] In a possible implementation, the operation module is specifically used to:

[0081] Acquire an address mapping relationship between the local memory and the extended memory, the address mapping relationship comprising at least one first address and at least one second address corresponding to each first address, the first address being the address of the memory unit in the local memory, and the second address being the address of the memory unit in the extended memory;

[0082] Determine a target first address corresponding to the address to be operated, and determine at least one target second address corresponding to the target first address;

[0083] The at least one target second address is determined to be the at least one spare address.

[0084] In the above solution, the standby address corresponding to the address to be operated can be determined according to the address mapping relationship, thereby achieving the purpose of determining the standby address.

[0085] In a possible implementation, the fault decision module is specifically used to:

[0086] Obtaining a fault table, the fault table being used to store target fault addresses of memory cells in the local memory where the number of times that repairable errors occur is greater than or equal to a preset threshold;

[0087] If the fault table is empty, determining that the memory state of the memory unit corresponding to the address to be operated is a normal state;

[0088] If the fault table is not empty, the memory status of the memory unit corresponding to the address to be operated is determined according to the fault table.

[0089] In the above solution, the memory state of the memory unit corresponding to the address to be operated can be determined according to the fault table, thereby achieving the purpose of determining the memory state of the memory unit corresponding to the address to be operated.

[0090] In a possible implementation, the fault decision module is specifically used to:

[0091] Determine whether the fault table includes the address to be operated;

[0092] If yes, determining the memory state of the memory unit corresponding to the address to be operated according to the data state of the address to be operated;

[0093] If not, it is determined that the memory state of the memory unit corresponding to the address to be operated is a normal state.

[0094] In the above scheme, the memory state of the memory unit corresponding to the address to be operated can be determined according to the data state of the address to be operated in the fault table, thereby achieving the purpose of determining the memory state of the memory unit corresponding to the address to be operated.

[0095] In a possible implementation, the data state is an uncompleted migration state or a completed migration state; the fault decision module is specifically configured to:

[0096] If the data state of the address to be operated is an uncompleted migration state, determining that the memory state of the memory unit corresponding to the address to be operated is a normal state;

[0097] If the data state of the address to be operated is a migration completion state, it is determined that the memory state of the memory unit corresponding to the address to be operated is a failure state.

[0098] In the above scheme, the memory state of the memory unit corresponding to the address to be operated can be determined according to the data state of the address to be operated in the fault table, thereby achieving the purpose of determining the memory state of the memory unit corresponding to the address to be operated.

[0099] In a possible implementation, the operation module is further configured to:

[0100] If the memory state is the normal state, data is stored in the memory unit corresponding to the address to be operated, or data is read from the memory unit corresponding to the address to be operated.

[0101] In the above scheme, data can be read from a memory unit whose memory state is a normal state, or data can be stored in a memory unit whose memory state is a normal state, thereby achieving the purpose of storing data or reading data.

[0102] In a possible implementation, the memory unit is any one of the following: the entire memory, a physical memory array, or a memory particle.

[0103] In the above solution, the memory unit may be the entire memory, a physical memory array, or a memory particle, which can improve the reliability of memory units of different granularities.

[0104] In a possible implementation, the fault decision module is further configured to:

[0105] Acquire from the CPU a target fault address of a target memory unit in the local memory where a repairable error occurs;

[0106] Determining the number of times that a repairable error occurs in the target memory unit according to the target fault address;

[0107] If the number is greater than or equal to a preset threshold, the target fault address is stored in the fault table.

[0108] In the above scheme, the target fault address where the number of repairable errors exceeds a preset threshold can be recorded in the fault table, so that the data storage device can determine the memory state of the memory unit corresponding to the address to be operated according to the fault table.

[0109] In a possible implementation, the device further includes a data migration module, the memory unit is the physical memory array or the memory particle, and after the target fault address is stored in the fault table, the data migration module is used to:

[0110] Acquire an address mapping relationship between the local memory and the extended memory;

[0111] Determine, according to the address mapping relationship, an address to be migrated corresponding to the target fault address, wherein the address to be migrated is an address of a memory unit in the extended memory;

[0112] The data stored in the target memory unit is migrated to the memory unit corresponding to the address to be migrated.

[0113] In the above solution, if the memory unit is a physical memory array or a memory particle, and the memory address corresponding to the memory unit is the target fault address, the data in the memory unit can be migrated to the extended memory, so that the data in the memory unit has higher reliability.

[0114] In a possible implementation, the operation module is used to:

[0115] storing data in a memory unit corresponding to the address to be operated through a first memory controller corresponding to the local memory, or reading data from a memory unit corresponding to the address to be operated through the first memory controller;

[0116] The data is stored in the extended memory through a second memory controller corresponding to the extended memory, or data is read from the extended memory through the second memory controller.

[0117] In the above scheme, data can be stored in the memory unit corresponding to the address to be operated, or data can be read from the memory unit corresponding to the address to be operated, through the first memory controller, and data can be stored in the extended memory, or data can be read from the extended memory, thereby achieving the purpose of storing or reading data.

[0118] In a possible implementation, the memory unit is the entire memory, and the operation module is specifically configured to:

[0119] The data to be stored corresponding to the operation request is stored in the memory unit corresponding to the address to be operated, and the data to be stored is stored in the extended memory at the same time.

[0120] In the above solution, if the memory unit is the entire memory, the data to be stored can be stored in the memory unit corresponding to the address to be operated and the extended memory at the same time, so as to achieve the purpose of data mirroring storage.

[0121] In a possible implementation, the device further includes an address conversion module, and the address conversion module is used to:

[0122] Acquire configuration information, wherein the configuration information includes addresses of each memory unit in the local memory, addresses of each memory unit in the extended memory, a security level of the local memory, and the number of extended memory units corresponding to each memory unit in the local memory, wherein the security level is a memory level, a physical memory array level, or a memory particle level, and the extended memory unit is a memory unit in the extended memory;

[0123] An address mapping relationship between the local memory and the extended memory is determined according to the security level and the quantity.

[0124] In the above scheme, the address mapping relationship between the local memory and the extended memory can be determined according to the security level of the local memory and the number of extended memory units corresponding to each memory unit, thereby achieving the purpose of determining the address mapping relationship.

[0125] In a possible implementation, the address conversion module is used to:

[0126] According to the security level, determining the memory unit as the entire memory, the physical memory array, or the memory particle;

[0127] Determining, in the extended memory, at least one of the extended memory cells for each memory cell in the local memory according to the number;

[0128] Determining a first address of each memory unit in the local memory and a second address of each of the extended memory units;

[0129] Each of the first addresses and at least one of the second addresses corresponding to each of the first addresses are stored in the address mapping relationship.

[0130] In the above solution, the correspondence between each memory unit in the local memory and the memory unit in the extended memory can be determined, thereby achieving the purpose of determining the address mapping relationship.

[0131] In a fourth aspect, an embodiment of the present application provides a data storage device, comprising a processor, and a memory communicatively connected to the processor;

[0132] The processor is used to execute the method described in any one of the first aspects to store data in the memory or read data from the memory.

[0133] In the above scheme, the data storage device can receive a data operation request sent by the CPU, the data operation request includes an operation type and an address to be operated, the operation type includes storing data or reading data; the memory state of the memory unit corresponding to the address to be operated can be determined; if the memory state is a fault state, the data storage device can store data in the extended memory or read data from the extended memory. In the above method, the extended memory in the data storage device can be used as a backup memory for the local memory, avoiding the use of the memory unit in the local memory as a backup memory unit. Through the above device, the local memory utilization rate can be improved while improving the RAS performance of the local memory of the computing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0134] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0135] Figure 1 A schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0136] Figure 2 A schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0137] Figure 3 A schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0138] Figure 4A A schematic diagram of the structure of a data storage device provided in an embodiment of the present application;

[0139] Figure 4B A schematic diagram of the structure of another data storage device provided in an embodiment of the present application;

[0140] Figure 5 A flowchart of a data processing method provided in an embodiment of the present application;

[0141] Figure 6 A flowchart of another data processing method provided in an embodiment of the present application;

[0142] Figure 7 A schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0143] Figure 8 A flowchart of another data processing method provided in an embodiment of the present application;

[0144] Fig. 9 A schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0145] Fig.10 A flowchart of another data processing method provided in an embodiment of the present application;

[0146] Fig.11 A schematic diagram of the structure of another computing device provided in an embodiment of the present application;

[0147] Fig.12 A flowchart of another data processing method provided in an embodiment of the present application;

[0148] Fig.13 A flowchart of another data processing method provided in an embodiment of the present application;

[0149] Fig.14 A flowchart of another data processing method provided in an embodiment of the present application;

[0150] Fig.15 A schematic diagram of the structure of a data storage device provided in an embodiment of the present application;

[0151] Fig.16 A schematic diagram of the structure of another data storage device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0152] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0153] To facilitate understanding, the technical terms involved in the embodiments of the present application are first explained.

[0154] Memory: Also known as internal memory or main memory, it is installed in the memory slot on the motherboard of a computing device. Memory can be used to store the calculation data of the processor. For example, memory can be random access memory (RAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), dual inline memory modules (DIMM), persistent memory (PMEM), or double data rate synchronous dynamic random access memory (DDR).

[0155] Physical memory array (Rank): The interface width between the central processing unit (CPU) and the memory is 64 bits (bit), while the bandwidth of a single memory particle (device) is only 4 / 8 / 16 bits. Therefore, multiple memory particles need to be connected in parallel to form a set with a bit width of 64 bits to be interconnected with the CPU. This set is called a physical memory array (Physical Bank). In order to distinguish it from the logical storage array (Logical Bank), manufacturers call this set a physical memory array (Rank).

[0156] RAS: A professional term in computer hardware engineering, including reliability, availability and serviceability. Reliability is the possibility of a system producing correct output within a given time; availability is the possibility of a system being able to be operated within a given time; serviceability describes the ease and speed with which a system can be repaired or maintained.

[0157] For ease of understanding, the following Figure 1 , the computing device involved in the embodiments of the present application is described.

[0158] Figure 1 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. Figure 1 The computing device may include a CPU and a memory, and the CPU and the memory may be communicatively connected. The CPU may write computing data to the memory, or may read computing data from the memory.

[0159] Optionally, the CPU may include a memory controller. The CPU may write operation data to the memory through the memory controller, or may read operation data from the memory through the memory controller.

[0160] The present application embodiment does not limit the specific type of computing device. The computing device can be any device including Figure 1 The computing device may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware. For example, the computing device may be a server, a desktop computer, a tablet computer, or an artificial intelligence device. The server may be, for example, a graphics processing unit (GPU) server or an artificial intelligence (AI) server.

[0161] The memory may be RAM, DRAM, SDRAM, DIMM, PMEM, or DDR, etc. The number of memories may be one or more, which is not limited in the present application embodiment.

[0162] In the related art, Figure 1 Part of the memory units shown in the figure are set as main memory units, and the remaining memory units are set as spare memory units. The memory unit can be the entire memory, a physical memory array or a memory particle.

[0163] The CPU can write data to the main memory unit and the backup memory unit at the same time; or, when the main memory unit fails, the CPU can write data to the backup memory unit. Through the above method, the RAS performance of the memory can be improved, thereby improving the reliability of the computing device.

[0164] In the above method, if the memory unit is the entire memory, a backup memory needs to be set for each main memory; if the memory unit is a physical memory array, a backup physical memory array needs to be set for each main physical memory array; if the memory unit is a memory particle, a backup memory particle needs to be set for each main memory particle.

[0165] Below, taking the memory unit as the entire memory as an example, combined with Figure 2 , the above method is explained.

[0166] Figure 2 This is a schematic diagram of another computing device provided in an embodiment of the present application. Figure 2 , a computing device may include a CPU and multiple memories.

[0167] The CPU can connect to memory 1 and memory 2 through channel 0, can connect to memory 3 and memory 4 through channel 1, can connect to memory 5 and memory 6 through channel 2, and can connect to memory 7 and memory 8 through channel 3.

[0168] In the above computing device, memory 1, memory 2, memory 3 and memory 4 can be set as main memories, and memory 5, memory 6, memory 7 and memory 8 can be set as backup memories. Among them, memory 5 can be a backup memory of memory 1, memory 6 can be a backup memory of memory 2, memory 7 can be a backup memory of memory 3, and memory 8 can be a backup memory of memory 4.

[0169] It should be noted that in the above computing device, each main memory and the corresponding backup memory should be exactly the same memory. That is, each main memory and the corresponding backup memory should be memories produced by the same manufacturer, with the same model and the same capacity. For example, memory 1 and memory 5 should be memories produced by the same manufacturer, with the same model and the same capacity.

[0170] Based on the above settings, when the CPU writes data to any main memory, it can also write the same data to the corresponding backup memory at the same time, so as to improve the RAS performance of multiple memories in the computing device. For example, when the CPU writes data 1 to memory 1, it can also write data 1 to memory 5 at the same time.

[0171] However, due to the setting of the backup memory, the maximum capacity of the memory in the above computing device is halved, resulting in a low memory utilization rate of the computing device.

[0172] It should be noted that if the memory unit is a physical memory array or memory particle, the CPU can write data to the corresponding backup memory unit when the main memory unit fails. If the main memory unit is not faulty, the CPU does not need to write data to both the main memory unit and the backup memory unit at the same time.

[0173] Exemplarily, it is assumed that the memory unit is a memory particle, and it is assumed that the memory particle 2 is a backup memory of the memory particle 1. When the CPU writes data 1 to the memory particle 1, if the memory particle 1 is not faulty, the CPU can directly write data 1 to the memory particle 1 without writing data 1 to the memory particle 1 at the same time; if the memory particle 1 is faulty, the CPU can write data 1 to the memory particle 2.

[0174] In view of this, the embodiment of the present application provides a data processing method to improve the memory utilization of the computing device while improving the memory RAS performance. Figure 3 , the data processing method provided in the embodiment of the present application is described.

[0175] Figure 3 This is a schematic diagram of the structure of another computing device provided in an embodiment of the present application. Figure 3 , a computing device may include a CPU, a data storage device, a local memory controller, and a local memory.

[0176] The data storage device can be connected to the CPU and the local memory controller respectively. The local memory controller can be connected to the local memory.

[0177] The local memory may be a memory installed in a slot on a computing device motherboard, such as RAM, DRAM, SDRAM, DIMM, PMEM, or DDR.

[0178] The local memory controller may be a memory control chip that is independently provided from the CPU, or the local memory controller may be integrated on the CPU.

[0179] The data storage device may be a storage device that complies with the Compute Express Link (CXL) protocol. The data storage device may include a CXL controller and an extended memory. The number of extended memories may be one or more, which is not limited in the embodiments of the present application. The CXL controller may be connected to the extended memory to store data in the extended memory or read data from the extended memory.

[0180] The CXL controller may be a control chip that complies with the CXL protocol.

[0181] The extended memory can be RAM, DRAM, SDRAM, DIMM, PMEM, or DDR, etc.

[0182] In one example, an extended memory controller may also be set in the CXL controller. Figure 4A As shown, Figure 4A This is a schematic diagram of the structure of a data storage device provided in an embodiment of the present application. Figure 4A The data storage device may include a CXL controller and an extended memory. The CXL controller may be connected to the extended memory. The CXL controller may include an extended memory controller. The CXL controller may store data in the extended memory or read data from the extended memory through the extended memory controller.

[0183] In another example, the extended memory controller may also be a memory control chip independently provided from the CXL controller. Figure 4B As shown, Figure 4B This is a schematic diagram of the structure of another data storage device provided in an embodiment of the present application. Figure 4B The data storage device may include a CXL controller, an extended memory controller, and an extended memory. The extended memory controller may be connected to the CXL controller and the extended memory, respectively.

[0184] In the embodiment of the present application, the extended memory in the data storage device can be used as a backup memory for the local memory. The setting of the extended memory can improve the RAS performance of the local memory in the computing device.

[0185] In the data processing method provided in the embodiment of the present application, all memory units in the local memory of the computing device can be used as main memory units, thereby avoiding a reduction in the maximum capacity of the content in the computing device and improving the memory utilization of the computing device.

[0186] In other embodiments, the computing device may not include a data storage device, and the data storage device may be connected to an interface exposed to the computing device, thereby achieving connection between the data storage device and the CPU of the computing device.

[0187] The technical solutions of the embodiments of the present application are described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0188] Figure 5 A flowchart of a data processing method provided in an embodiment of the present application. Figure 5 , the method may include:

[0189] S501. Receive a data operation request sent by a CPU, where the data operation request includes an operation type and an address to be operated.

[0190] This embodiment is applied to a data storage device, and the data storage device includes an extended memory.

[0191] The operation type includes storing data or reading data. Storing data refers to storing the data to be stored in the memory unit corresponding to the address to be operated. Reading data refers to reading the data to be read from the memory unit corresponding to the address to be operated.

[0192] The memory unit corresponding to the address to be operated is a memory unit in the local memory included in the computing device to which the CPU belongs.

[0193] It should be noted that the structure of the CPU, local memory, and data storage device can be found in Figure 3 .

[0194] In this embodiment, the memory unit may be the entire memory, a physical memory array, or a memory particle. The address to be operated may be used to indicate the memory unit where the to-be-stored data corresponding to the data operation request needs to be stored, or the memory unit where the to-be-read data corresponding to the data operation request is located.

[0195] Exemplarily, if the memory unit is the entire memory, the address to be operated can be used to indicate the memory where the data to be stored needs to be stored, or the address to be operated can be used to indicate the memory where the data to be read is located. If the memory unit is a physical memory array, the address to be operated can be used to indicate the physical memory array where the data to be stored needs to be stored, or the address to be operated can be used to indicate the physical memory array where the data to be read is located. If the memory unit is a memory particle, the address to be operated can be used to indicate the memory particle where the data to be stored needs to be stored, or the address to be operated can be used to indicate the memory particle where the data to be read is located.

[0196] S502: Determine a memory state of a memory unit corresponding to the address to be operated, where the memory state is a fault state or a normal state.

[0197] If the memory status is a fault status, execute S503.

[0198] In this embodiment, when determining the memory status of the memory unit corresponding to the address to be operated, a fault table can be obtained, where the fault table is used to store the target fault addresses of the memory units in which the number of repairable errors occurring in the local memory is greater than or equal to a preset threshold; if the fault table is empty, it is determined that the memory status of the memory unit corresponding to the address to be operated is normal; if the fault table is not empty, the memory status of the memory unit corresponding to the address to be operated is determined according to the fault table.

[0199] In this embodiment, the memory unit in the local memory in which the number of repairable errors occurring is greater than or equal to the preset threshold may be a memory unit in the local memory with a higher probability of failure occurring.

[0200] The fault table can be stored in a data storage device. That is, the data storage device can obtain the fault table locally. It should be noted that the generation process of the fault table can be referred to Fig.14 For the update process of the fault table, please refer to Fig.13 The embodiments are not described in detail here.

[0201] In this embodiment, the fault table includes the data status of the target fault address, and the data status is an incomplete migration state or a completed migration state. When determining the memory status of the memory unit corresponding to the address to be operated according to the fault table, it can be determined whether the address to be operated is included in the fault table; if so, the memory status of the memory unit corresponding to the address to be operated is determined according to the data status of the address to be operated; if not, it is determined that the memory status of the memory unit corresponding to the address to be operated is a normal state. If the data status of the address to be operated is an incomplete migration state, it is determined that the memory status of the memory unit corresponding to the address to be operated is a normal state; if the data status of the address to be operated is a completed migration state, it is determined that the memory status of the memory unit corresponding to the address to be operated is a fault state.

[0202] Specifically, if the fault table is empty, the data storage device can directly determine that the memory state of the memory unit corresponding to the address to be operated is in a normal state. If the fault table is not empty, but the address to be operated is not included in the fault table, the data storage device can determine that the memory state of the memory unit corresponding to the address to be operated is in a normal state. If the fault table is not empty, and the address to be operated is included in the fault table, but the data state of the fault address is an incomplete migration state, the data storage device can determine that the memory state of the memory unit corresponding to the address to be operated is in a normal state. If the fault table is not empty, the address to be operated is included in the fault table, and the data state of the fault address is a completed migration state, the data storage device can determine that the memory state of the memory unit corresponding to the address to be operated is a fault state.

[0203] S503: Store data in the extended memory or read data from the extended memory.

[0204] In this embodiment, if the operation type is to store data and the memory state of the memory unit corresponding to the address to be operated is in a fault state, the data storage device can store the data to be stored corresponding to the operation request to the extended memory to improve the reliability of the data to be stored. If the operation type is to read data and the memory state of the memory unit corresponding to the address to be operated is in a fault state, the data storage device can read the data to be read corresponding to the operation request from the extended memory.

[0205] In this embodiment, the data storage device may further include a second memory controller corresponding to the extended memory. The second memory controller may be used to write data to the extended memory according to a data write request; or the second memory controller may be used to read data from the extended memory according to a data read request. The second memory controller may be Figure 4A and Figure 4B The extended memory controller is shown.

[0206] In this embodiment, the data storage device may store the data to be stored in the extended memory through the second memory controller; or the data storage device may read the data to be read from the extended memory through the second memory controller.

[0207] It should be noted that if the memory state of the memory unit corresponding to the address to be operated is normal, the data storage device can store data in the memory unit corresponding to the address to be operated, or read data from the memory unit corresponding to the address to be operated.

[0208] In this embodiment, the data storage device may also be connected to a first memory controller corresponding to the local memory. The first memory controller may be used to write data to the local memory according to a data write request; or the first memory controller may be used to read data from the local memory according to a data read request. The second memory controller may be Figure 3The local memory controller is shown.

[0209] In this embodiment, the data storage device may store the data to be stored in the memory unit corresponding to the address to be operated through the first memory controller; or, the data storage device may read the data to be read from the memory unit corresponding to the address to be operated through the first memory controller.

[0210] In this embodiment, the first memory controller may be arranged outside the data storage device, and the first memory controller may be connected to the data storage device in a wired or wireless manner.

[0211] Optionally, the first memory controller may also be arranged on the data storage device.

[0212] It should be noted that if the memory unit is the entire memory, when the data storage device stores the data to be stored in the memory unit corresponding to the address to be operated, it can also store the data to be stored in the extended memory at the same time.

[0213] In the data processing method provided in the embodiment of the present application, the data storage device can receive a data operation request sent by the CPU, the data operation request includes an operation type and an address to be operated, the operation type includes storing data or reading data; the memory state of the memory unit corresponding to the address to be operated can be determined; if the memory state is a fault state, the data storage device can store data in the extended memory, or read data from the extended memory. In the above method, the extended memory in the data storage device can be used as a backup memory for the local memory, avoiding the use of the memory unit in the local memory as a backup memory unit. Through the above method, the local memory utilization rate can be improved while improving the RAS performance of the local memory of the computing device.

[0214] exist Figure 5 Based on the embodiment, if the memory state of the memory unit corresponding to the address to be operated is a fault state, the spare address corresponding to the address to be operated can be determined, and the data to be stored corresponding to the data operation request can be stored in the memory unit corresponding to the spare address, or the data to be read corresponding to the data operation request can be read from the memory unit corresponding to the spare address. Figure 6 The above method is described.

[0215] Figure 6 A flowchart of another data processing method provided in an embodiment of the present application. Figure 6 , the method may include:

[0216] S601. Receive a data operation request sent by a CPU, where the data operation request includes an operation type and an address to be operated.

[0217] S602: Determine a memory state of a memory unit corresponding to the address to be operated, where the memory state is a fault state or a normal state.

[0218] If the memory status is a fault status, execute S603.

[0219] It should be noted that the specific implementation method of S601-S602 can refer to S501-S502 and will not be repeated here.

[0220] S603: Determine at least one spare address corresponding to the address to be operated.

[0221] The memory unit corresponding to the spare address is a memory unit in the extended memory.

[0222] In this embodiment, the memory unit corresponding to the standby address may be a standby memory unit of the memory unit corresponding to the address to be operated.

[0223] In this embodiment, when determining the backup address corresponding to the address to be operated, the data storage device can obtain the address mapping relationship between the local memory and the extended memory, the address mapping relationship includes at least one first address, and at least one second address corresponding to each first address, the first address is the address of the memory unit in the local memory, and the second address is the address of the memory unit in the extended memory; determine the target first address corresponding to the address to be operated, and determine at least one target second address corresponding to the target first address; determine at least one target second address as at least one backup address. Among them, at least one is one or more, and multiple is two or more.

[0224] Specifically, the first address identical to the address to be operated may be searched in the address mapping relationship, and the second address corresponding to the first address identical to the address to be operated may be determined as the standby address. The number of standby addresses may be one or more, wherein the number may be two or more.

[0225] Exemplarily, the address mapping relationship may be as shown in Table 1:

[0226] Table 1

[0227] First Address Second address First address 1 Second address 11, second address 12 First Address 2 Second address 21, second address 22 …… …… First address n The second address n1, the second address n2

[0228] As shown in Table 1, the second address corresponding to the first address 1 may be the second address 11 and the second address 12, the second address corresponding to the first address 2 may be the second address 21 and the second address 22, ..., the second address corresponding to the first address n may be the second address n1 and the second address n2, wherein n is an integer greater than or equal to 1.

[0229] Assuming that the address to be operated is the first address 2, the target first address is the first address 2, and the target second addresses corresponding to the target first address are the second address 21 and the second address 22. Therefore, the backup addresses can be determined to be the second address 21 and the second address 22.

[0230] In this embodiment, the address mapping relationship between the local memory and the extended memory can be stored in the data storage device. In other words, the data storage device can obtain the address mapping relationship locally.

[0231] It should be noted that the generation process of the address mapping relationship can be found in Fig.14 The embodiments are not described in detail here.

[0232] S604: Store the data to be stored in a memory unit corresponding to at least one spare address, or read the data to be read from a memory unit corresponding to at least one spare address.

[0233] In this embodiment, the backup address has at least the following two situations:

[0234] Case 1: The number of backup addresses is one.

[0235] In this case, the data storage device may store the data to be stored in the memory unit corresponding to the one spare address, or the data storage device may read the data to be read from the memory unit corresponding to the one spare address.

[0236] In this case, the amount of expansion memory required is smaller, making the cost of the data storage device lower.

[0237] Case 2: There are multiple backup addresses.

[0238] In this case, the data storage device may store the data to be stored in the memory unit corresponding to each spare address, or the data storage device may read the data to be read from the memory unit corresponding to any spare address.

[0239] In this case, each local memory unit can have multiple spare memory units, so that data reliability is higher.

[0240] Optionally, the data storage device may store the data to be stored in a memory unit corresponding to at least one spare address through a second memory controller; or, the data storage device may read the data to be read from a memory unit corresponding to at least one spare address through a second memory controller.

[0241] It should be noted that if the memory state of the memory unit corresponding to the address to be operated is normal, the data storage device can store data in the memory unit corresponding to the address to be operated, or read data from the memory unit corresponding to the address to be operated. Specific implementation methods can be found in S503, which will not be described here.

[0242] In the data processing method provided in this embodiment, the data storage device can receive a data storage request sent by the CPU, and the data operation request includes an operation type and an address to be operated; the memory state of the memory unit corresponding to the address to be operated can be determined; if the memory state is a fault state, the data storage device can determine at least one spare address corresponding to the address to be operated, and can store the data to be stored in the memory unit corresponding to at least one spare address, or read the data to be read from the memory unit corresponding to at least one spare address. In the above method, each memory unit in the local memory can have at least one spare memory unit, and the spare memory unit can be located in the extended memory. Through the above method, the local memory utilization rate can be improved while improving the RAS performance of the local memory of the computing device.

[0243] Next, combine Figure 7-Figure 12 , the data storage process is explained when the memory unit is the entire memory, the physical memory array and the memory particle.

[0244] First, through Figure 7 and Figure 8 , the case where the memory unit is the entire memory is explained.

[0245] Figure 7 This is a schematic diagram of the structure of another computing device provided in an embodiment of the present application. Figure 7 The computing device may include a CPU, a data storage device, a first memory controller, a local memory 1, and a local memory 2. The data storage device may include a CXL controller, an extended memory 1, and an extended memory 2.

[0246] In the above computing device, extended memory 1 may be a backup memory of local memory 1 , and extended memory 2 may be a backup memory of local memory 2 .

[0247] It should be noted that, in the above computing device, each local memory and the corresponding extended memory may be different memories. That is to say, for any local memory, the local memory and the corresponding extended memory may be memories produced by different manufacturers, or the model of the local memory and the model of the corresponding extended memory may be different, or the capacity of the local memory and the capacity of the corresponding extended memory may be different. Compared with the requirement in the prior art that the main memory and the backup memory are exactly the same memory, in the embodiment of the present application, the selection flexibility of the backup memory is higher.

[0248] It should be noted that, if after configuring backup memory for the local memory, the data storage device also stores the remaining extended memory, the extended memory can also be used as a local memory resource to store the calculation data of the computing device.

[0249] It should be noted that Figure 7 The example of each local memory having one corresponding extended memory is used for illustration only, and does not constitute a limitation on the embodiments of the present application. In other embodiments, each local memory may also have multiple corresponding extended memories.

[0250] It should be noted that, in other embodiments, the computing device may not include a data storage device, and the data storage device may be connected to an interface exposed to the computing device, thereby realizing a connection between the data storage device and the CPU of the computing device.

[0251] Next, combine Figure 8 ,right Figure 7 The data processing method in the computing device shown is described.

[0252] Figure 8 A flowchart of another data processing method provided in an embodiment of the present application. Figure 8 , the method may include:

[0253] S801. Receive a data operation request sent by a CPU, where the data operation request includes an operation type and an address to be operated.

[0254] In this embodiment, the data storage device may receive a data operation request sent by the CPU.

[0255] In this embodiment, it is assumed that the operation type is to store data, it is assumed that the data to be stored is data 1, and it is assumed that the address to be operated corresponding to the data to be stored is the address of the local memory 2.

[0256] S802: Determine the memory state of the local memory corresponding to the address to be operated, where the memory state is a fault state or a normal state.

[0257] In this embodiment, it is assumed that the data storage device can determine, according to the fault table, that the memory state of the local memory (local memory 2) corresponding to the address to be operated is a fault state.

[0258] It should be noted that if the memory state of the local memory (local memory 2) corresponding to the address to be operated is normal, the data storage device can store data 1 in the local memory 2 and execute S803 at the same time.

[0259] S803: Determine the standby address corresponding to the address to be operated.

[0260] In this embodiment, the data storage device may determine that the standby address corresponding to the local memory 2 is the address of the extended memory 2 according to the address mapping relationship between the local memory and the extended memory.

[0261] S804: Store the data to be stored in the extended memory corresponding to the standby address.

[0262] In this embodiment, since the memory state of the local memory 2 is a fault state, the data storage device can switch the storage position and store the data 1 in the extended memory 2 corresponding to the local memory 2.

[0263] In the data processing method provided in this embodiment, the backup memory of local memory 1 may be extended memory 1, and the backup memory of local memory 2 may be extended memory 2. If any local memory fails, the data to be stored may be stored in the corresponding backup memory, or the data to be read may be read from the backup memory. The above method can improve the local memory utilization while improving the RAS performance of the local memory of the computing device.

[0264] Secondly, through Fig. 9 and Fig.10 , the case where the memory unit is a physical memory array is described.

[0265] Fig. 9 This is a schematic diagram of the structure of another computing device provided in an embodiment of the present application. Fig. 9 , the computing device may include a CPU, a data storage device, a first memory controller, a local memory 1, and a local memory 2. The data storage device may include a CXL controller and an extended memory.

[0266] The local memory 1 may include a physical memory array, and the physical memory array included in the local memory 1 may be the physical memory array 0.

[0267] The local memory 2 may include a physical memory array, and the physical memory array included in the local memory 2 may be the physical memory array 1.

[0268] The extended memory may include four physical memory arrays, and the physical memory arrays included in the extended memory may be physical memory array 2, physical memory array 3, physical memory array 4, and physical memory array 5.

[0269] In the above computing device, physical memory array 2 and physical memory array 3 may be spare memory units of physical memory array 0, and physical memory array 5 may be spare memory units of physical memory array 1.

[0270] It should be noted that one or more spare physical memory arrays can be set for any physical memory array in the local memory according to user requirements. The embodiment of the present application does not limit the number of spare physical memory arrays.

[0271] It should be noted that, in the above computing device, a local memory may include only one physical memory array, or a local memory may include multiple physical memory arrays, so that the selection of the local memory is more flexible. Fig. 9 The example that each local memory includes a physical memory array is used for illustration only, and does not constitute a limitation on the embodiments of the present application.

[0272] Of course, in other embodiments, the computing device may not include a data storage device, and the data storage device may be connected to an interface exposed to the computing device, thereby realizing a connection between the data storage device and the CPU of the computing device.

[0273] Next, combine Fig.10 ,right Fig. 9 The data processing method in the computing device shown is described.

[0274] Fig.10 A flowchart of another data processing method provided in an embodiment of the present application. Fig.10 , the method may include:

[0275] S1001. Receive a data operation request sent by a CPU, where the data operation request includes an operation type and an address to be operated.

[0276] In this embodiment, the data storage device may receive a data operation request sent by the CPU.

[0277] In this embodiment, it is assumed that the operation type is to store data, it is assumed that the data to be stored is data 1, and it is assumed that the address to be operated corresponding to the data to be stored is the address of the physical memory array 0.

[0278] S1002: Determine the memory state of the physical memory array corresponding to the address to be operated, where the memory state is a fault state or a normal state.

[0279] In this embodiment, it is assumed that the data storage device can determine, according to the fault table, that the memory state of the physical memory array (physical memory array 0) corresponding to the address to be operated is a fault state.

[0280] It should be noted that if the memory state of the physical memory array (physical memory array 0) corresponding to the address to be operated is normal, the data storage device can store data 1 in the physical memory array 0 without executing S1003-S1004.

[0281] S1003: Determine a standby address corresponding to the address to be operated.

[0282] In this embodiment, the data storage device may determine that the spare address corresponding to the physical memory array 0 is the address of the physical memory array 2 and the address of the physical memory array 3 according to the address mapping relationship between the local memory and the extended memory.

[0283] S1004. Store the data to be stored in the extended memory corresponding to the spare address.

[0284] In this embodiment, since the memory state of the physical memory array 0 is a fault state, the data storage device can switch the storage position and store the data 1 in the physical memory array 2 and the physical memory array 3 corresponding to the physical memory array 0 respectively.

[0285] In the data processing method provided in this embodiment, the spare memory unit of the physical memory array in the local memory can be a physical memory array in the extended memory. If any physical memory array in the local memory fails, the data to be stored can be stored in the corresponding spare physical memory array. The above method can improve the local memory utilization while improving the RAS performance of the local memory of the computing device.

[0286] Finally, through Fig.11 and Fig.12 , the case where the memory unit is a memory particle is described.

[0287] Fig.11 This is a schematic diagram of the structure of another computing device provided in an embodiment of the present application. Fig.11 The computing device may include a CPU, a data storage device, a first memory controller, and a local memory. The data storage device may include a CXL controller and an extended memory.

[0288] The local memory may include 18 memory cells, and the 18 memory cells in the local memory may be D0, D1, ..., and D17.

[0289] The extended memory may also include 18 memory chips, which may be S0, S1, ..., and S17.

[0290] In the above computing device, the spare memory unit of the memory particle D0 may be the memory particle S2, and the spare memory unit of the memory particle D7 may be the memory particle S6.

[0291] It should be noted that in the above-mentioned computing device, the local memory may not be provided with memory particles for storing parity check results and / or Ming-Han codes. In other words, all memory particles in the local memory are used to store the computing data of the computing device, further improving the memory utilization of the local memory. The memory particles in the extended memory can be used to store parity check results and / or Ming-Han codes, and the memory particles in the extended memory can also be used as spare memory units for the memory particles in the local memory. In addition, the memory particles in the extended memory can also be used to store the computing data of the computing device.

[0292] In other embodiments, the computing device may not include a data storage device, and the data storage device may be connected to an interface exposed to the computing device, thereby achieving connection between the data storage device and the CPU of the computing device.

[0293] In this embodiment, a spare memory cell can be set for one or more memory cells in the local memory according to user needs. Fig.11 You can set spare memory chips for D0 and D7.

[0294] Next, combine Fig.12 ,right Fig.11 The data processing method in the computing device shown is described.

[0295] Fig.12 A flowchart of another data processing method provided in an embodiment of the present application. Fig.12 , the method may include:

[0296] S1201. Receive a data operation request sent by a CPU, where the data operation request includes an operation type and an address to be operated.

[0297] In this embodiment, the data storage device may receive a data operation request sent by the CPU.

[0298] In this embodiment, it is assumed that the operation type is to store data, it is assumed that the data to be stored is data 1, and it is assumed that the address to be operated corresponding to the data to be stored is the address of the memory chip D7.

[0299] S1202: Determine the memory state of the memory chip corresponding to the address to be operated, where the memory state is a fault state or a normal state.

[0300] In this embodiment, it is assumed that the data storage device can determine, according to the fault table, that the memory state of the memory cell (memory cell D7) corresponding to the address to be operated is a fault state.

[0301] It should be noted that if the memory state of the memory cell (memory cell D7) corresponding to the address to be operated is normal, the data storage device can store data 1 in the memory cell D7 without executing S1203-S1204.

[0302] S1203: Determine a standby address corresponding to the address to be operated.

[0303] In this embodiment, the data storage device can determine that the standby address corresponding to the address to be operated is the address of the memory cell S7 according to the address mapping relationship between the local memory and the extended memory.

[0304] S1204. Store the data to be stored in the extended memory corresponding to the standby address.

[0305] In this embodiment, since the memory state of the physical memory array 0 is a fault state, the data storage device can switch the storage position and store the data 1 in the memory cell S7.

[0306] In the data processing method provided in this embodiment, the spare memory unit of the memory particle in the local memory can be a memory particle in the extended memory. If any memory particle in the local memory fails, the data to be stored can be stored in the corresponding spare memory particle. The above method can improve the local memory utilization rate while improving the RAS performance of the local memory of the computing device.

[0307] Based on any of the above embodiments, in the data processing method provided in the embodiment of the present application, the data storage device can also update the fault table according to the fault information of the local memory. For any memory unit in the fault table, the data storage device can migrate the data in the memory unit to the spare memory unit corresponding to the memory unit. Fig.13 The above method is described.

[0308] Fig.13 A flowchart of another data processing method provided in an embodiment of the present application. Fig.13 , the method may include:

[0309] S1301. Obtain from the CPU a target fault address of a target memory unit where a repairable error occurs in a local memory.

[0310] The target memory unit may be a memory unit in the local memory where a repairable error occurs. For example, the target memory unit may be the entire memory, a physical memory array, or a memory particle.

[0311] The target fault address may be the address of the target memory unit. For example, if the target memory unit is memory cell 0, the target fault address may be the address of memory cell 0.

[0312] It should be understood that if a recoverable error occurs in the local memory of the computing device, the CPU can obtain the target fault address.

[0313] In this embodiment, the data storage device may obtain the target fault address from the CPU in real time, or the data storage device may obtain the target fault address from the CPU periodically.

[0314] In one example, if the data storage device obtains the target fault address from the CPU in real time, then after a repairable error occurs in the local memory, the data storage device can immediately obtain the target fault address from the CPU.

[0315] In another example, if the data storage device periodically obtains the target fault address from the CPU, the data storage device may periodically obtain all target fault addresses in the local memory in the current cycle from the CPU.

[0316] S1302. Determine the number of times that a repairable error occurs in a target memory unit according to the target fault address.

[0317] In this embodiment, the data storage device may record the number of acquisitions of each target fault address.

[0318] Exemplarily, when the data storage device obtains the target fault address 1 for the first time, the acquisition number of the target fault address 1 may be recorded as 1. When the data storage device obtains the target fault address 1 for the second time, the acquisition number of the target fault address 1 may be recorded as 2.

[0319] In this embodiment, after the data storage device obtains the target fault address, it can determine the number of times that the target memory unit has a repairable error according to the recorded historical fault addresses and the number of times each historical fault address is obtained.

[0320] The historical fault address may be a target fault address acquired by the data storage device before the current moment.

[0321] Specifically, after the data storage device obtains the target fault address, it can search for the target fault address in the historical fault addresses. If the target fault address does not exist in the historical fault addresses, the data storage device can determine that the number of times a repairable error has occurred in the target memory unit is 1. If the target fault address exists in the historical fault addresses, the data storage device can update the number of acquisitions of the historical fault address corresponding to the target fault address to the original number plus 1, and can determine that the number of times a repairable error has occurred in the target memory unit is the updated number.

[0322] For example, it is assumed that the historical fault addresses and the number of acquisition times of the historical fault addresses are as shown in Table 2:

[0323] Table 2

[0324] Historical fault address Number of acquisitions Memory chip 2 1 Memory chip 5 3 Memory chip 9 2

[0325] As shown in Table 2, the historical fault addresses may include memory cell 2, memory cell 5, and memory cell 9. The acquisition times of memory cell 2 is 1, the acquisition times of memory cell 5 is 3, and the acquisition times of memory cell 9 is 2.

[0326] Assuming that the target fault address is memory cell 1, the data storage device can determine that the number of times a repairable error occurs in the target memory cell is 1.

[0327] Assuming that the target fault address is memory cell 5, the data storage device can determine that the number of times that a repairable error occurs in the target memory cell is 4.

[0328] It should be noted that, in one example, the CPU may also determine the number of times that a repairable error occurs in the target memory unit, and may send the number of times that a repairable error occurs in the target memory unit to the data storage device.

[0329] S1303: If the number is greater than or equal to the preset threshold, the target fault address is stored in the fault table.

[0330] The preset threshold can be set according to actual needs, and this embodiment does not limit the value of the preset threshold. For example, the preset threshold can be 5.

[0331] In this embodiment, for any target fault address, the data storage device may determine that the probability of a target memory unit corresponding to the target fault address failing is relatively high, and may add the target fault address to the fault table.

[0332] In other embodiments, the CPU may also determine the number of repairable errors that occur in the target memory unit. If the number is greater than or equal to a preset threshold, the target fault address is sent to the data storage device, and the data storage device may store the target fault address in a fault table.

[0333] S1304: Obtain an address mapping relationship between the local memory and the extended memory.

[0334] In this embodiment, if the target memory unit is a physical memory array or a memory cell, after the data storage device adds the target fault address to the fault table, it can also migrate the data stored in the target memory unit to the corresponding spare memory unit.

[0335] Before migrating data to the spare memory unit, the data storage device may obtain an address mapping relationship between the local memory and the extended memory.

[0336] S1305: Determine the address to be migrated corresponding to the target fault address according to the address mapping relationship.

[0337] The address to be migrated is the address of a memory unit in the extended memory.

[0338] The memory unit corresponding to the address to be migrated may be a spare memory unit of the target memory unit.

[0339] Specifically, the data storage device may search for the target fault address in the address mapping relationship, and may determine the address corresponding to the target fault address in the address mapping relationship as the address to be migrated.

[0340] S1306: Migrate the data stored in the target memory unit to the memory unit corresponding to the address to be migrated.

[0341] In this embodiment, the data storage device may migrate the data stored in the target memory unit to the corresponding spare memory unit to improve the reliability of the data.

[0342] The fault table may also include the data status of each target fault address. Before the data in the target memory unit is migrated, the data status of the corresponding target fault address may be an incomplete migration state; after the data in the target memory unit is migrated, the data status of the corresponding target fault address may be a completed migration state.

[0343] For any target fault address, before the data storage device completes the data migration of the target memory unit, the data storage device may record the data status of the target fault address as an incomplete migration status; after the data storage device completes the data migration of the target memory unit, the data storage device may update the data status of the target fault address to a completed migration status.

[0344] It should be noted that when the data state of the target fault address is an uncompleted migration state, if the address to be operated in the data storage request is the target fault address, the data storage device can still store the data to be stored in the memory unit corresponding to the target fault address. When the data state of the target fault address is a completed migration state, if the address to be operated in the data storage request is the target fault address, the data storage device can store the data to be stored in the spare memory unit corresponding to the target memory unit.

[0345] In the data processing method provided in this embodiment, the data storage device can obtain the target fault address of the target memory unit where a repairable error occurs in the local memory from the CPU, and can determine the number of times the repairable error occurs in the target memory unit based on the target fault address. If the number is greater than or equal to the preset threshold, the data storage device can store the target fault address in the fault table. If the target memory unit is a physical memory array or memory particle, the data storage device can also obtain the address mapping relationship between the local memory and the extended memory, and can determine the address to be migrated corresponding to the target fault address based on the address mapping relationship, and can migrate the data stored in the target memory unit to the memory unit corresponding to the address to be migrated. Through the above method, the data in the memory unit can be migrated to the corresponding spare memory unit before the memory unit in the local memory fails, thereby improving the reliability of the data in the computing device.

[0346] Based on any of the above embodiments, in the data processing method provided in the embodiment of the present application, the data storage device may also generate an address mapping relationship between the local memory and the extended memory according to the configuration information of the computing device. Fig.14 The above method is described.

[0347] Fig.14 A flowchart of another data processing method provided in an embodiment of the present application. Fig.14 , the method may include:

[0348] S1401. Obtain configuration information, where the configuration information includes the address of each memory unit in the local memory, the address of each memory unit in the extended memory, the security level of the local memory, and the number of extended memory units corresponding to each memory unit in the local memory.

[0349] The security level is a memory level, a physical memory array level, or a memory granule level, and the extended memory unit is a memory unit in the extended memory.

[0350] In this embodiment, the data storage device can automatically obtain configuration information during the startup phase of the computing device.

[0351] The configuration information may be configuration information of the computing device generated by the computing device according to user requirements (eg, the security level of the local memory, and the number of extended memory units corresponding to each memory unit in the local memory, etc.).

[0352] S1402. Determine the address mapping relationship between the local memory and the extended memory according to the security level and quantity.

[0353] In this embodiment, the data storage device can determine the memory unit as the entire memory, the physical memory array, or the memory particle according to the security level; determine at least one extended memory unit in the extended memory for each memory unit in the local memory according to the quantity; determine the first address of each memory unit in the local memory, and the second address of each extended memory unit; store each first address, and at least one second address corresponding to each first address, in an address mapping relationship.

[0354] Specifically, if the security level in the configuration information is at the memory level, the data storage device can determine one or more second addresses for the first address corresponding to each local memory, and generate an address mapping relationship; wherein the second address corresponds to a memory in the extended memory. If the security level in the configuration information is at the physical memory array level, the data storage device can determine one or more second addresses for the first address corresponding to each physical memory array in the local memory, and generate an address mapping relationship; wherein the second address corresponds to a physical memory array in the extended memory. If the security level in the configuration information is at the memory particle level, the data storage device can determine one or more second addresses for the first address corresponding to each memory particle in the local memory, and generate an address mapping relationship; wherein the second address corresponds to a memory particle in the extended memory.

[0355] It should be noted that, in this embodiment, only the security level is memory level, physical memory array level, or memory granule level as an example for illustration, and does not constitute a limitation on the technical solution provided in the embodiment of the present application. The security level in the configuration information can also be a security level of a smaller granularity to improve the reliability of memory units of a smaller granularity. For example, the security level can also be a page level.

[0356] Optionally, the configuration information may also specify the number of local memory units and the extended memory units corresponding to the local memory units. The data storage device may determine one or more second addresses for the first address corresponding to the specified memory according to the configuration information, and generate an address mapping relationship. For example, the configuration information may specify that an extended memory unit is configured for memory cell 1 and memory cell 5 in the local memory, and may specify that one extended memory unit is configured for memory cell 1, and two extended memory units are configured for memory cell 5.

[0357] Optionally, during the startup phase of the computing device, the data storage device may also create a fault table. It should be understood that during the startup phase of the computing device, the fault table created by the data storage device is an empty table.

[0358] In the data processing method provided in this embodiment, the data storage device can obtain configuration information and generate an address mapping relationship between the local memory and the extended memory based on the configuration information to facilitate storing data in the extended memory or migrating data in the local memory to the extended memory.

[0359] Fig.15 A schematic diagram of a data storage device provided in an embodiment of the present application. The data storage device is applied to a data storage device, the data storage device includes an extended memory, the data storage device 10 includes a receiving module 11, a fault decision module 12 and an operation module 13, wherein:

[0360] The receiving module 11 is used to receive a data operation request sent by a central processing unit CPU, wherein the data operation request includes an operation type and an address to be operated, the memory unit corresponding to the address to be operated is a memory unit in a local memory included in a computing device to which the CPU belongs, and the operation type includes storing data or reading data;

[0361] The fault decision module 12 is used to determine the memory state of the memory unit corresponding to the address to be operated, and the memory state is a fault state or a normal state;

[0362] If the memory state is the fault state, the operating module 13 is used to store data in the extended memory or read data from the extended memory.

[0363] The data storage device provided in this embodiment can be used to execute the data processing method shown in the above method embodiment. Its implementation principle and technical effects are similar and will not be described in detail here.

[0364] In a possible implementation, the operation module 13 is specifically used to:

[0365] Determine at least one spare address corresponding to the address to be operated, where the memory unit corresponding to the spare address is a memory unit in the extended memory;

[0366] The to-be-stored data corresponding to the operation request is stored in the memory unit corresponding to the spare address, or the to-be-read data corresponding to the operation request is read from the memory unit corresponding to the spare address.

[0367] In a possible implementation, the operation module 13 is specifically used to:

[0368] Acquire an address mapping relationship between the local memory and the extended memory, the address mapping relationship comprising at least one first address and at least one second address corresponding to each first address, the first address being the address of the memory unit in the local memory, and the second address being the address of the memory unit in the extended memory;

[0369] Determine a target first address corresponding to the address to be operated, and determine at least one target second address corresponding to the target first address;

[0370] The at least one target second address is determined to be the at least one spare address.

[0371] In a possible implementation, the fault decision module 12 is specifically configured to:

[0372] Obtaining a fault table, the fault table being used to store target fault addresses of memory cells in the local memory where the number of times that repairable errors occur is greater than or equal to a preset threshold;

[0373] If the fault table is empty, determining that the memory state of the memory unit corresponding to the address to be operated is a normal state;

[0374] If the fault table is not empty, the memory state of the memory unit corresponding to the address to be operated is determined according to the fault table.

[0375] In a possible implementation, the fault decision module 12 is specifically configured to:

[0376] Determine whether the fault table includes the address to be operated;

[0377] If so, determining the memory state of the memory unit corresponding to the address to be operated according to the data state of the address to be operated;

[0378] If not, it is determined that the memory state of the memory unit corresponding to the address to be operated is a normal state.

[0379] In a possible implementation, the data state is an uncompleted migration state or a completed migration state; the fault decision module 12 is specifically configured to:

[0380] If the data state of the address to be operated is an uncompleted migration state, determining that the memory state of the memory unit corresponding to the address to be operated is a normal state;

[0381] If the data state of the address to be operated is a migration completion state, it is determined that the memory state of the memory unit corresponding to the address to be operated is a failure state.

[0382] In a possible implementation, the operating module 13 is further configured to:

[0383] If the memory state is the normal state, data is stored in the memory unit corresponding to the address to be operated, or data is read from the memory unit corresponding to the address to be operated.

[0384] In a possible implementation, the memory unit is any one of the following: the entire memory, a physical memory array, or a memory particle.

[0385] In a possible implementation, the fault decision module 12 is further configured to:

[0386] Acquire from the CPU a target fault address of a target memory unit in the local memory where a repairable error occurs;

[0387] Determining the number of times that a repairable error occurs in the target memory unit according to the target fault address;

[0388] If the number is greater than or equal to a preset threshold, the target fault address is stored in the fault table.

[0389] Fig.16 A schematic diagram of the structure of another data storage device provided in an embodiment of the present application. Fig.15 On the basis of, the data storage device 10 further includes a data migration module 14 and an address conversion module 15, the memory unit is the physical memory array or the memory particle, and after the target fault address is stored in the fault table, the data migration module 14 is used to,

[0390] Acquire an address mapping relationship between the local memory and the extended memory;

[0391] Determine, according to the address mapping relationship, an address to be migrated corresponding to the target fault address, wherein the address to be migrated is an address of a memory unit in the extended memory;

[0392] The data stored in the target memory unit is migrated to the memory unit corresponding to the address to be migrated.

[0393] In a possible implementation, the operating module 13 is used to:

[0394] storing data in a memory unit corresponding to the address to be operated through a first memory controller corresponding to the local memory, or reading data from a memory unit corresponding to the address to be operated through the first memory controller;

[0395] The data is stored in the extended memory through a second memory controller corresponding to the extended memory, or data is read from the extended memory through the second memory controller.

[0396] In a possible implementation, the memory unit is the entire memory, and the operation module 13 is specifically configured to:

[0397] The data to be stored corresponding to the operation request is stored in the memory unit corresponding to the address to be operated, and the data to be stored is stored in the extended memory at the same time.

[0398] In a possible implementation, the address conversion module 15 is used to:

[0399] Acquire configuration information, wherein the configuration information includes addresses of each memory unit in the local memory, addresses of each memory unit in the extended memory, a security level of the local memory, and the number of extended memory units corresponding to each memory unit in the local memory, wherein the security level is a memory level, a physical memory array level, or a memory particle level, and the extended memory unit is a memory unit in the extended memory;

[0400] An address mapping relationship between the local memory and the extended memory is determined according to the security level and the quantity.

[0401] In a possible implementation, the address conversion module 15 is specifically used to:

[0402] According to the security level, determining the memory unit as the entire memory, the physical memory array, or the memory particle;

[0403] Determining, in the extended memory, at least one of the extended memory cells for each memory cell in the local memory according to the number;

[0404] Determining a first address of each memory unit in the local memory and a second address of each of the extended memory units;

[0405] Each of the first addresses and at least one of the second addresses corresponding to each of the first addresses are stored in the address mapping relationship.

[0406] The data storage device provided in this embodiment can be used to execute the data processing method shown in the above method embodiment. Its implementation principle and technical effects are similar and will not be described in detail here.

[0407] The receiving module, fault decision module, operation module, data migration module, and address conversion module in the data storage device provided in this embodiment can be run on a control chip. The control chip can be integrated into Figure 4A and Figure 4B In the CXL controller of the data storage device shown, or the control chip can also be separately arranged Figure 4A and Figure 4B A data storage device is shown on a CXL controller.

[0408] The embodiment of the present application also provides a data storage device, including a processor, and a memory communicatively connected to the processor;

[0409] The processor is used to execute the data processing method shown in the above method embodiment to store data in the memory or read data from the memory. Its implementation principle and technical effect are similar and will not be repeated here.

[0410] All or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a readable memory. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned memory (storage medium) includes: read-only memory (English: read-only memory, abbreviated: ROM), RAM, flash memory, hard disk, solid state drive, magnetic tape (English: magnetic tape), floppy disk (English: floppy disk), optical disc (English: optical disc) and any combination thereof.

[0411] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable terminal device to generate a machine, so that the instructions executed by the processing unit of the computer or other programmable terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0412] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0413] These computer program instructions can also be loaded onto a computer or other programmable terminal device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0414] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the embodiments of the present application are also intended to include these modifications and variations.

[0415] In the embodiments of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or device including the element. The term "or" and its variations may refer to "and / or". In the embodiments of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. In the embodiments of the present application, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, A and / or B, which may represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0416] After considering the invention disclosed in the specification and practice, those skilled in the art will easily think of other embodiments of the present application. The embodiments of the present application are intended to cover any variation, use or adaptive change of the embodiments of the present application, which follows the general principles of the embodiments of the present application and includes common knowledge or conventional technical means in the technical field that are not disclosed in the embodiments of the present application.

Claims

1. A data processing method, characterized in that: Applied to a data storage device, the data storage device includes an extended memory; the method includes: Receive a data operation request sent by a central processing unit (CPU), wherein the data operation request includes an operation type and an address to be operated, wherein the memory unit corresponding to the address to be operated is a memory unit in a local memory included in a computing device to which the CPU belongs, and the operation type includes storing data or reading data; Determine a memory state of a memory unit corresponding to the address to be operated, wherein the memory state is a fault state or a normal state; If the memory state is the fault state, data is stored in the extended memory or data is read from the extended memory.

2. The method according to claim 1, characterized in that The storing of data in the extended memory or reading of data from the extended memory comprises: Determine at least one spare address corresponding to the address to be operated, where the memory unit corresponding to the spare address is a memory unit in the extended memory; The to-be-stored data corresponding to the operation request is stored in the memory unit corresponding to the spare address, or the to-be-read data corresponding to the operation request is read from the memory unit corresponding to the spare address.

3. The method according to any one of claims 1 or 2, characterized in that: The determining of the memory state of the memory unit corresponding to the address to be operated includes: Obtaining a fault table, the fault table being used to store target fault addresses of memory cells in the local memory where the number of times that repairable errors occur is greater than or equal to a preset threshold; If the fault table is empty, determining that the memory state of the memory unit corresponding to the address to be operated is a normal state; If the fault table is not empty, the memory state of the memory unit corresponding to the address to be operated is determined according to the fault table.

4. The method according to claim 3, characterized in that: The fault table includes the data status of the target fault address; The determining, according to the fault table, a memory state of the memory unit corresponding to the address to be operated includes: Determine whether the fault table includes the address to be operated; If so, determining the memory state of the memory unit corresponding to the address to be operated according to the data state of the address to be operated; If not, it is determined that the memory state of the memory unit corresponding to the address to be operated is a normal state.

5. The method according to any one of claims 1 to 4, characterized in that: The memory unit is any one of the following: the entire memory, a physical memory array, or a memory particle.

6. The method according to any one of claims 3 to 5, characterized in that: The method further comprises: Acquire from the CPU a target fault address of a target memory unit in the local memory where a repairable error occurs; Determining the number of times that a repairable error occurs in the target memory unit according to the target fault address; If the number is greater than or equal to a preset threshold, the target fault address is stored in a fault table.

7. The method according to claim 6, characterized in that The memory unit is a physical memory array or a memory particle; after storing the target fault address in the fault table, the method further includes: Acquire an address mapping relationship between the local memory and the extended memory; Determine, according to the address mapping relationship, an address to be migrated corresponding to the target fault address, wherein the address to be migrated is an address of a memory unit in the extended memory; The data stored in the target memory unit is migrated to the memory unit corresponding to the address to be migrated.

8. The method according to any one of claims 5 to 7, characterized in that: The memory unit is the entire memory; storing data in the memory unit corresponding to the address to be operated includes: The data to be stored corresponding to the operation request is stored in the memory unit corresponding to the address to be operated, and the data to be stored is stored in the extended memory at the same time.

9. The method according to any one of claims 1 to 8, characterized in that: The method further comprises: Acquire configuration information, wherein the configuration information includes addresses of each memory unit in the local memory, addresses of each memory unit in the extended memory, a security level of the local memory, and the number of extended memory units corresponding to each memory unit in the local memory, wherein the security level is a memory level, a physical memory array level, or a memory particle level, and the extended memory unit is a memory unit in the extended memory; An address mapping relationship between the local memory and the extended memory is determined according to the security level and the quantity.

10. A data storage device, characterized in that: comprising a processor and a memory communicatively connected to the processor; The processor is used to execute the method according to any one of claims 1 to 9 to store data in the memory or read data from the memory.

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