CMP Process Simulation Method, Device, Storage Medium and Electronic Device

Abstract

The present application discloses a CMP process simulation method, apparatus, storage medium and electronic device. Among them, the CMP process simulation method includes obtaining a chip layout of a chip to be simulated and dividing the chip layout into a plurality of grids; converting the pattern information of each grid into two-dimensional features and extracting one-dimensional features of each grid through a physical model; inputting the one-dimensional features and the two-dimensional features into the fully-connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain a first feature vector and a second feature vector; fusing the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector; inputting the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result. This solution can improve the simulation accuracy of the CMP process.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of chemical mechanical polishing, and particularly to a CMP process simulation method, device, storage medium and electronic device. Background Art

[0002] The chemical mechanical planarization (CMP) process is the most widely used and most effective global planarization process in current integrated circuit manufacturing technologies, especially in the back-end copper interconnect process. The CMP process generally includes multiple steps such as chemical reaction and physical removal, and is a complex process in which various factors such as the size of abrasive particles, the properties of the polishing pad, the composition of the polishing liquid, the down pressure, and the relative speed between the polishing pad and the wafer interact with each other.

[0003] The CMP process is one of the important technologies and key process steps to ensure the flatness of the polished chip surface. In order to ensure the high flatness of the polished chip surface, cooperation between design and process is required. Therefore, technicians have conducted extensive research and attention on CMP process simulation methods. However, there are still many deficiencies in directly applying existing CMP process simulation methods to the field of manufacturability design and process simulation of advanced process nodes, and the simulation accuracy needs to be improved. Summary of the Invention

[0004] The embodiments of the present application provide a CMP process simulation method, device, storage medium and electronic device, which can improve the simulation accuracy of the CMP process.

[0005] In a first aspect, the embodiments of the present application provide a CMP process simulation method, including:

[0006] Obtain the chip layout of the chip to be simulated, and divide the chip layout into several grids;

[0007] Convert the pattern information of each grid into two-dimensional features, and extract one-dimensional features of each grid through a physical model;

[0008] Input the one-dimensional features and the two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain a first feature vector and a second feature vector;

[0009] Fuse the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector;

[0010] Input the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result.

[0011] In the CMP process simulation method provided by the embodiments of the present application, the conversion of the pattern information of each grid into two-dimensional features includes:

[0012] Mapping the pattern information of each grid into a grayscale image through an image algorithm to obtain two-dimensional features.

[0013] In the CMP process simulation method provided by the embodiments of the present application, after inputting the target feature vector into the prediction layer of the CMP simulation model to generate grid simulation results, it further includes:

[0014] Combining all the grid simulation results to obtain a layout simulation result.

[0015] In the CMP process simulation method provided by the embodiments of the present application, it further includes:

[0016] Constructing a CMP simulation model.

[0017] In the CMP process simulation method provided by the embodiments of the present application, the construction of the CMP simulation model includes:

[0018] Obtaining a test layout of a test chip, where the test layout has several regions, and each region has different pattern densities, line widths, and gaps;

[0019] Converting the pattern information of each region into two-dimensional features, and extracting one-dimensional features of each region through a physical model;

[0020] Performing CMP process treatment on the test layout with fixed process parameters to obtain a treatment result;

[0021] Using the one-dimensional features, the two-dimensional features, and the treatment result as training data to train a dual-channel fusion network model to obtain a CMP simulation model.

[0022] In the CMP process simulation method provided by the embodiments of the present application, the step of using the one-dimensional features, the two-dimensional features, and the treatment result as training data to train a dual-channel fusion network model to obtain a CMP simulation model includes:

[0023] Using the one-dimensional features and the two-dimensional features as the input of the dual-channel fusion network model, and using the treatment result as the target output of the dual-channel fusion model to train the dual-channel fusion network model to obtain a CMP simulation model.

[0024] In the CMP process simulation method provided by the embodiments of the present application, the dual-channel fusion network model uses the mean square error as the loss function.

[0025] Second aspect, an embodiment of the present application provides a CMP process simulation device, including:

[0026] A layout acquisition unit, configured to acquire the chip layout of the chip to be simulated, and divide the chip layout into a plurality of grids;

[0027] A feature acquisition unit, configured to convert the pattern information of each grid into two-dimensional features, and extract one-dimensional features of each grid through a physical model;

[0028] A feature input unit, configured to input the one-dimensional features and the two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively, to obtain a first feature vector and a second feature vector;

[0029] A feature fusion unit, configured to fuse the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector;

[0030] A CMP simulation unit, configured to input the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result.

[0031] Third aspect, the present application provides a storage medium, which stores a plurality of instructions, and the instructions are suitable for being loaded by a processor to execute the CMP process simulation method described in any one of the above.

[0032] Fourth aspect, the present application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the CMP process simulation method described in any one of the above is implemented.

[0033] In summary, the CMP process simulation method provided by the embodiment of the present application includes acquiring the chip layout of the chip to be simulated, and dividing the chip layout into a plurality of grids; converting the pattern information of each grid into two-dimensional features, and extracting one-dimensional features of each grid through a physical model; inputting the one-dimensional features and the two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively, to obtain a first feature vector and a second feature vector; fusing the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector; inputting the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result. This solution combines the data stability of the physical model and the strong fitting ability of the neural network, so that the CMP simulation is more robust, reduces the overfitting defect of pure neural network modeling, and further improves the simulation accuracy of the CMP process. Description of the Drawings

[0034] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0035] Figure 1 It is a schematic diagram of the application scenario of the CMP process simulation method provided by the embodiments of the present application.

[0036] Figure 2 It is a schematic flowchart of the CMP simulation model construction method provided by the embodiments of the present application.

[0037] Figure 3 It is a schematic flowchart of the CMP process simulation method provided by the embodiments of the present application.

[0038] Figure 4 It is a schematic diagram of the structure of the CMP simulation model construction device provided by the embodiments of the present application.

[0039] Figure 5 It is a schematic diagram of the structure of the CMP process simulation device provided by the embodiments of the present application.

[0040] Figure 6 It is a schematic diagram of the structure of the electronic device provided by the embodiments of the present application. Detailed implementation manners

[0041] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the present application. On the contrary, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0042] It should be noted that in this text, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, article or device comprising such element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0043] It should be understood that the specific embodiments described herein are merely for explaining the present application and are not used to limit the present application.

[0044] In the subsequent descriptions, the suffixes such as "module", "component" or "unit" used to denote elements are only for the convenience of explaining the present application and have no specific meaning in themselves. Therefore, "module", "component" or "unit" can be used interchangeably.

[0045] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0046] The CMP process is one of the important technologies and key process steps to ensure the flatness of the polished chip surface. In order to ensure the high flatness of the polished chip surface, cooperation between design and process is required. Therefore, technicians have conducted extensive research and attention on CMP process simulation methods. However, there are still many deficiencies in directly applying existing CMP process simulation methods to the field of manufacturability design and process simulation of advanced process nodes, and the simulation accuracy needs to be improved.

[0047] Based on this, the embodiments of the present application provide a CMP process simulation method, apparatus, storage medium, and electronic device. Specifically, the CMP process simulation apparatus can be integrated into an electronic device, which can be a server or a terminal device, etc. Among them, the terminal can include a mobile phone, a wearable intelligent device, a tablet computer, a laptop computer, and a personal computer (PC), etc.; the server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0048] For example, as Figure 1 shown, the electronic device can obtain the chip layout of the chip to be simulated, and divide the chip layout into several grids; convert the pattern information of each grid into two-dimensional features, and extract the one-dimensional features of each grid through a physical model; input the one-dimensional features and two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain a first feature vector and a second feature vector; fuse the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector; input the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result.

[0049] The technical solutions shown in the present application will be described in detail below through specific embodiments. It should be noted that the description order of the following embodiments does not limit the priority order of the embodiments.

[0050] Please refer to Figure 2 , Figure 2 which is a schematic flowchart of the CMP simulation model construction method provided by the embodiments of the present application. The specific process of the CMP simulation model construction method can be as follows:

[0051] 101. Obtain the test layout of the test chip. The test layout has several regions, and each region has different pattern densities, line widths, and gaps.

[0052] The Figure 1 layout is generally created through chip design software (such as Cadence, Mentor Graphics, Synopsys, etc.). In the semiconductor manufacturing industry, in order to ensure the standardization and compatibility of design data, specific file format standards, such as GDS (Graphic Data System) or OASIS (Open Artwork System Interchange Standard), are usually used to save these layouts.

[0053] When designing a test chip, the test layout is divided into several regions according to a fixed size (e.g., 10μm×10μm or 50μm×50μm), and different pattern structures such as pattern density, line width, and gap are set in each region. For example, Region A: high-density line array (line width = 0.1μm, spacing = 0.05μm). Region B: low-density isolated lines (line width = 0.5μm, spacing = 0.3μm). Region C: mixed structure (including randomly distributed line widths and gaps, simulating the actual chip layout).

[0054] It can be understood that during the CMP process, the material removal rate, planarization effect, and polishing uniformity of CMP are closely related to the pattern structure. For example, the pattern density affects the local removal rate, and the polishing rate may be lower in the high-density region. The line width affects the local uniformity, and the removal rates of wide lines and narrow lines may be different. The gap affects the flow of the polishing liquid and the stress distribution, which may lead to different removal characteristics.

[0055] By designing regions with different pattern densities, line widths, and gaps, the removal characteristics of different pattern structures under the same process conditions can be analyzed. Moreover, designing regions with multiple different pattern structures can simulate the diverse structures that may appear in actual chip manufacturing, avoid the model being only applicable to specific pattern structures, and improve the generalization ability. If only relying on a single pattern structure, the neural network may overfit, resulting in inaccurate model predictions.

[0056] 102. Convert the pattern information of each region into two-dimensional features, and extract one-dimensional features of each region through a physical model.

[0057] Specifically, the pattern information of each region can be mapped into a grayscale image (e.g., 256×256 pixels) through image processing technology, reflecting the height differences of different regions. This grayscale image is the two-dimensional feature.

[0058] The one-dimensional feature refers to the numerical vector representation of key parameters such as pattern density, line width, and gap. For example, density = 80%, line width = 0.2μm, minimum gap = 0.05μm.

[0059] Among them, the pattern density can be calculated through a density calculation formula. That is, density = (line width × line length) / area of the region × 100%. For example, for a region with an area of 100μm², a total line length of 50μm, and a line width of 0.1μm, the density = (0.1×50) / 100×100% = 5%.

[0060] The line width and gap can be automatically extracted through image processing algorithms (such as edge detection) to avoid manual errors.

[0061] 103. Perform CMP process on the test layout with fixed process parameters to obtain the processing result.

[0062] Among them, the fixed process parameters can be polishing pressure, polishing head rotation speed, slurry flow rate, polishing liquid type, etc.

[0063] After the CMP process is completed, the CMP processing results (such as height after polishing, material removal rate, etc.) of each area can be obtained through measuring equipment.

[0064] 104. Use the one-dimensional features, two-dimensional features, and processing results as training data to train the dual-channel fusion network model to obtain a CMP simulation model.

[0065] First, a number of one-dimensional features, two-dimensional features, and processing results can be divided into a training set, a test set, and a validation set according to a ratio. For example, the training set is 80%, the validation set is 10%, and the test set is 10%.

[0066] Then, use the one-dimensional features and two-dimensional features as the input of the dual-channel fusion network model, and use the processing result as the target output of the dual-channel fusion model to train the dual-channel fusion network model to obtain a CMP simulation model.

[0067] Among them, the dual-channel fusion network model has a fully connected neural network channel, a convolutional neural network channel, a feature fusion layer, and a prediction layer.

[0068] During the model training process, the fully connected neural network channel is used to process one-dimensional features. By learning the non-linear relationship between parameters (such as the correlation between density and material removal rate) through the prediction layer, a low-dimensional feature vector (such as 8-dimensional) can be output. The convolutional neural network channel is used to process two-dimensional features. By extracting local spatial features (such as edges, textures) through the convolutional layer and capturing the sensitive areas of polishing for the pattern layout, a high-dimensional feature vector (such as 128-dimensional) can be output. The feature fusion layer is used to fuse the feature vector output by the convolutional neural network channel and the feature vector output by the fully connected neural network channel to generate a target vector. The prediction layer is actually a fully connected layer, which can map the target features to the simulation results (such as height deviation, material removal rate).

[0069] And the processing result obtained in step 103 can be used to compare with this simulation result to optimize the model parameters of the dual-channel fusion network model according to the comparison result. When the difference between the processing result and the simulation result is within the threshold, it can be considered that the model training is completed, and a CMP simulation model is obtained.

[0070] The specific structures of the fully connected neural network channel and the convolutional neural network channel can be set according to the actual situation, and this embodiment does not limit them.

[0071] It can be understood that since all the training data are generated under fixed process parameters, the model learns the mapping relationship between the features and the simulation results under these parameters through training, and the influence of the process parameters is "encoded" into the weights of the model. In practical applications, the model assumes that the process parameters are the same as those during training, and the user does not need to input the process parameters additionally. If the parameters need to be changed, the model needs to be retrained or adjusted through transfer learning.

[0072] In some embodiments, during the training process of the dual-channel fusion network model, the Adam or SGD optimization algorithm can be used for gradient descent optimization to improve the convergence speed and prevent overfitting.

[0073] In addition, the mean squared error can be used as the loss function for the dual-channel fusion network model to optimize the weights of the neural network.

[0074] After the CMP simulation model is trained, it can be packaged as a Python library or a REST API and docked with a CMP simulation platform (such as COMSOL).

[0075] In summary, the method for constructing a CMP simulation model provided by the embodiments of the present application includes obtaining a test layout of a test chip, where the test layout has several regions, and each region has different pattern densities, line widths, and gaps; converting the pattern information of each region into two-dimensional features, and extracting one-dimensional features of each region through a physical model; performing a CMP process on the test layout with fixed process parameters to obtain a processing result; using the one-dimensional features, two-dimensional features, and the processing result as training data to train a dual-channel fusion network model to obtain a CMP simulation model. This solution can provide more stable input information by designing regions with different pattern densities, pattern widths, and pattern gaps, and combining the one-dimensional features extracted by the physical model, reduce the dependence of the neural network on the distribution of training data, and improve the generalization ability. Moreover, the introduction of one-dimensional features enables the neural network to still maintain a high prediction accuracy in the case of insufficient data, avoiding over-reliance on large-scale training data.

[0076] Furthermore, the convolutional neural network channel is responsible for processing two-dimensional features and extracting the pattern structure features of local regions, which can improve the adaptability to different pattern structures. The fully connected neural network channel is responsible for processing the one-dimensional features extracted by the physical model, which can enhance the understanding of global parameters and avoid the model relying only on local topography. By fusing the outputs of the fully connected neural network channel and the convolutional neural network channel, the prediction accuracy and model stability of the CMP simulation model can be improved, and at the same time, the problem of neural network overfitting can be avoided.

[0077] Please refer to Figure 3 , Figure 3It is a schematic flowchart of the CMP process simulation method provided by an embodiment of the present application. The specific process of the CMP process simulation method can be as follows:

[0078] 201. Obtain the chip layout of the chip to be simulated, and divide the chip layout into several grids.

[0079] In some embodiments, the chip layout can be divided into regular grids. For example, the chip is divided into regular grids according to a fixed size (such as 10μm×10μm or 50μm×50μm).

[0080] In some embodiments, the chip layout can also be adaptively meshed. For example, smaller grids are used for high-density regions and larger grids are used for low-density regions to improve the calculation efficiency.

[0081] 202. Convert the pattern information of each grid into two-dimensional features, and extract one-dimensional features of each grid through a physical model.

[0082] Specifically, the pattern information of each of the grids is mapped to a grayscale image through an image algorithm to obtain two-dimensional features.

[0083] The one-dimensional feature refers to a numerical vector representation of key parameters such as pattern density, line width, and gap. For example, density = 80%, line width = 0.2μm, and minimum gap = 0.05μm.

[0084] Among them, the pattern density can be calculated through a density calculation formula. That is, density = (line width × line length) / area of the region × 100%. For example, if the area of a certain region is 100μm², the total line length is 50μm, and the line width is 0.1μm, then the density = (0.1×50) / 100×100% = 5%.

[0085] The line width and gap can be automatically extracted through an image processing algorithm (such as edge detection) to avoid manual errors.

[0086] 203. Input the one-dimensional feature and the two-dimensional feature into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain a first feature vector and a second feature vector.

[0087] It should be noted that the CMP simulation model is the model constructed by the above-mentioned CMP simulation model construction method. The specific process of constructing the CMP simulation model can refer to the above embodiments, and this embodiment will not be elaborated one by one.

[0088] Specifically, the one-dimensional feature can be input into the fully connected neural network channel to obtain a first feature vector. The two-dimensional feature is input into the convolutional neural network channel to obtain a second feature vector.

[0089] 204. The first feature vector and the second feature vector are fused through the feature fusion layer of the CMP simulation model to generate a target feature vector.

[0090] In some embodiments, the first feature vector and the second feature vector can be directly concatenated. For example, a 128-dimensional vector output by the convolutional neural network channel and an 8-dimensional vector output by the fully connected neural network channel are concatenated into a 136-dimensional target feature vector. In some embodiments, the first feature vector and the second feature vector can also be weighted and fused.

[0091] 205. The target feature vector is input into the prediction layer of the CMP simulation model to generate a grid simulation result.

[0092] It can be understood that by combining all the grid simulation results, the layout simulation result can be obtained.

[0093] In summary, the CMP process simulation method provided by the embodiments of the present application includes obtaining the chip layout of the chip to be simulated and dividing the chip layout into several grids; converting the pattern information of each grid into two-dimensional features, and extracting one-dimensional features of each grid through a physical model; inputting the one-dimensional features and the two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain a first feature vector and a second feature vector; fusing the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector; inputting the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result. This solution combines the data stability of the physical model and the strong fitting ability of the neural network, thereby making the CMP simulation more robust, reducing the overfitting defect of pure neural network modeling, and further improving the simulation accuracy of the CMP process.

[0094] To facilitate better implementation of the CMP simulation model construction method provided by the embodiments of the present application, the embodiments of the present application also provide a CMP simulation model construction device. The meanings of the terms are the same as those in the above CMP simulation model construction method, and the specific implementation details can refer to the description in the method embodiments.

[0095] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of the CMP simulation model construction device provided by the embodiments of the present application. The CMP simulation model construction device may include a layout extraction unit 301, a feature extraction unit 302, a CMP processing unit 303, and a model training unit 304. Among them,

[0096] The layout extraction unit 301 is used to obtain the test layout of the test chip. The test layout has several regions, and each region has different pattern densities, line widths, and gaps.

[0097] The feature extraction unit 302 is configured to convert the pattern information of each region into two-dimensional features and extract one-dimensional features of each region through a physical model;

[0098] The CMP processing unit 303 is configured to perform CMP process on the test layout with fixed process parameters to obtain a processing result;

[0099] The model training unit 304 is configured to use the one-dimensional features, two-dimensional features, and the processing result as training data to train a dual-channel fusion network model to obtain a CMP simulation model.

[0100] For the specific implementation manners of the above units, reference may be made to the embodiments of the CMP process simulation method described above, which will not be elaborated herein one by one.

[0101] In summary, the CMP simulation model construction device provided by the embodiments of the present application obtains the test layout of the test chip through the layout extraction unit 301. The test layout has several regions, and each region has different pattern densities, line widths, and gaps. The feature extraction unit 302 converts the pattern information of each region into two-dimensional features and extracts one-dimensional features of each region through a physical model. The CMP processing unit 303 performs CMP process on the test layout with fixed process parameters to obtain a processing result. The model training unit 304 uses the one-dimensional features, two-dimensional features, and the processing result as training data to train a dual-channel fusion network model to obtain a CMP simulation model. This solution can provide more stable input information by designing regions with different pattern densities, pattern widths, and pattern gaps, and combining the one-dimensional features extracted by the physical model, reduce the dependence of the neural network on the distribution of training data, and improve the generalization ability. Moreover, the introduction of one-dimensional features enables the neural network to maintain a high prediction accuracy even in the case of insufficient data, avoiding over-reliance on large-scale training data.

[0102] To facilitate better implementation of the CMP process simulation method provided by the embodiments of the present application, the embodiments of the present application also provide a CMP process simulation device. The meanings of the nouns therein are the same as those in the above CMP process simulation method, and the specific implementation details can be referred to the description in the method embodiments.

[0103] Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of the CMP process simulation device provided by the embodiments of the present application. The CMP process simulation device may include a layout acquisition unit 401, a feature acquisition unit 402, a feature input unit 403, a feature fusion unit 404, and a CMP simulation unit 405. Among them,

[0104] The layout acquisition unit 401 is configured to acquire the chip layout of the chip to be simulated and divide the chip layout into several grids;

[0105] A feature acquisition unit 402, configured to convert the pattern information of each grid into two-dimensional features, and extract one-dimensional features of each grid through a physical model;

[0106] A feature input unit 403, configured to input the one-dimensional features and the two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively, to obtain a first feature vector and a second feature vector;

[0107] A feature fusion unit 404, configured to fuse the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector;

[0108] A CMP simulation unit 405, configured to input the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result.

[0109] For the specific implementation manners of the above units, reference may be made to the embodiments of the CMP process simulation method described above, which will not be elaborated herein one by one.

[0110] In summary, the CMP process simulation device provided by the embodiments of the present application obtains the chip layout of the chip to be simulated through the layout acquisition unit 401, and divides the chip layout into several grids; the feature acquisition unit 402 converts the pattern information of each grid into two-dimensional features, and extracts one-dimensional features of each grid through a physical model; the feature input unit 403 inputs the one-dimensional features and the two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively, to obtain a first feature vector and a second feature vector; the feature fusion unit 404 fuses the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector; the CMP simulation unit 405 inputs the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result. This solution combines the data stability of the physical model and the strong fitting ability of the neural network, thereby making the CMP simulation more robust, reducing the overfitting defect of pure neural network modeling, and further improving the simulation accuracy of the CMP process.

[0111] The embodiments of the present application further provide an electronic device, which may integrate the CMP process simulation device of the embodiments of the present application. As Figure 6 shown, it shows a schematic structural diagram of the electronic device involved in the embodiments of the present application. Specifically:

[0112] The electronic device may include components such as a processor 501 with one or more processing cores and a memory 502 with one or more computer-readable storage media. Those skilled in the art can understand, Figure 6The electronic device structure shown does not constitute a limitation on the electronic device, and may include more or fewer components than shown, or combine certain components, or have different component arrangements. Among them:

[0113] The processor 501 is the control center of the electronic device, connecting various parts of the entire electronic device through various interfaces and circuits. By running or executing software programs and / or this application stored in the memory 502, and by calling the data stored in the memory 502, it executes various functions of the electronic device and processes data, thereby monitoring the electronic device as a whole. Optionally, the processor 501 may include one or more processing cores; preferably, the processor 501 may integrate an application processor and a modem processor. Among them, the application processor mainly processes operating storage media, user interfaces, application programs, etc., and the modem processor mainly processes wireless communications. It can be understood that the above-mentioned modem processor may not be integrated into the processor 501.

[0114] The memory 502 can be used to store software programs and this application. The processor 501 executes various functional applications and data processing by running the software programs and this application stored in the memory 502. The memory 502 may mainly include a program storage area and a data storage area. Among them, the program storage area can store operating storage media, application programs required for at least one function, etc.; the data storage area can store data created according to the use of the electronic device. In addition, the memory 502 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state storage devices. Correspondingly, the memory 502 may also include a memory controller to provide the processor 501 with access to the memory 502.

[0115] Although not shown, the electronic device may also include a display unit, an input unit, a power supply, etc., which will not be elaborated here. Specifically in this embodiment, the processor 501 in the electronic device will, according to the following instructions, load the executable files corresponding to the processes of one or more application programs into the memory 502, and the processor 501 will run the application programs stored in the memory 502 to achieve various functions as follows:

[0116] Obtain the chip layout of the chip to be simulated, and divide the chip layout into several grids;

[0117] Convert the pattern information of each grid into two-dimensional features, and extract the one-dimensional features of each grid through a physical model;

[0118] Input the one-dimensional features and two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain a first feature vector and a second feature vector;

[0119] Fuse the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector;

[0120] Input the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result.

[0121] Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions or by controlling relevant hardware through instructions. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0122] For this reason, an embodiment of the present application provides a storage medium, which stores multiple instructions that can be loaded by a processor to execute the steps in any one of the methods provided by the embodiments of the present application. For example, the instructions can perform the following steps:

[0123] Obtain the chip layout of the chip to be simulated and divide the chip layout into several grids;

[0124] Convert the pattern information of each grid into two-dimensional features and extract the one-dimensional features of each grid through a physical model;

[0125] Input the one-dimensional features and the two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain a first feature vector and a second feature vector;

[0126] Fuse the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector;

[0127] Input the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result.

[0128] For the specific implementation of each of the above operations, reference can be made to the previous embodiments and will not be elaborated here.

[0129] Among them, the storage medium may include: read-only memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disc, etc.

[0130] Since the instructions stored in the storage medium can execute the steps in any one of the methods provided by the embodiments of the present application, the beneficial effects that can be achieved by any one of the methods provided by the embodiments of the present application can be realized. For details, refer to the previous embodiments and will not be elaborated here.

[0131] The CMP process simulation method, device, storage medium, and electronic device provided by the present application have been introduced in detail above. Specific examples are used in this article to elaborate on the principles and implementation manners of the present application. The descriptions of the above embodiments are only used to help understand the core idea of the present application. At the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A CMP process simulation method, characterized in that, Including: Obtain the chip layout of the chip to be simulated, and divide the chip layout into several grids; Convert the pattern information of each grid into two-dimensional features, and extract one-dimensional features of each grid through a physical model, where the one-dimensional features refer to the numerical vector representation of pattern density, line width, and gap; Input the one-dimensional features and the two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain a first feature vector and a second feature vector; Fuse the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector; Input the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result.

2. The CMP process simulation method according to claim 1, wherein The converting the pattern information of each grid into two-dimensional features includes: Map the pattern information of each grid into a grayscale image through an image algorithm to obtain two-dimensional features.

3. The CMP process simulation method according to claim 1, wherein After inputting the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result, it further includes: Combine all the grid simulation results to obtain a layout simulation result.

4. The CMP process simulation method according to claim 1, wherein, It also includes: Construct a CMP simulation model.

5. The CMP process simulation method according to claim 4, wherein The constructing the CMP simulation model includes: Obtain the test layout of the test chip, where the test layout has several regions, and each region has different pattern densities, line widths, and gaps; Convert the pattern information of each region into two-dimensional features, and extract one-dimensional features of each region through a physical model; Perform CMP process on the test layout with fixed process parameters to obtain a processing result; Use the one-dimensional features, the two-dimensional features, and the processing result as training data to train a dual-channel fusion network model to obtain a CMP simulation model.

6. The CMP process simulation method according to claim 5, wherein The using the one-dimensional features, the two-dimensional features, and the processing result as training data to train a dual-channel fusion network model to obtain a CMP simulation model includes: Use the one-dimensional features and the two-dimensional features as the input of the dual-channel fusion network model, and use the processing result as the target output of the dual-channel fusion model to train the dual-channel fusion network model to obtain a CMP simulation model.

7. The CMP process simulation method according to claim 5, wherein The dual-channel fusion network model uses the mean square error as the loss function.

8. A CMP process simulation device, characterized in that, Including: A layout acquisition unit for obtaining the chip layout of the chip to be simulated and dividing the chip layout into several grids; A feature acquisition unit for converting the pattern information of each grid into two-dimensional features and extracting one-dimensional features of each grid through a physical model, where the one-dimensional features refer to the numerical vector representation of pattern density, line width, and gap; A feature input unit for inputting the one-dimensional features and the two-dimensional features into the fully connected neural network channel and the convolutional neural network channel of the CMP simulation model respectively to obtain a first feature vector and a second feature vector; A feature fusion unit for fusing the first feature vector and the second feature vector through the feature fusion layer of the CMP simulation model to generate a target feature vector; The CMP simulation unit is configured to input the target feature vector into the prediction layer of the CMP simulation model to generate a grid simulation result.

9. A storage medium, characterized in that, The storage medium stores multiple instructions, and the instructions are adapted to be loaded by a processor to execute the CMP process simulation method according to any one of claims 1-7.

10. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored on the memory and executable on the processor. Wherein, when the processor executes the computer program, it implements the CMP process simulation method according to any one of claims 1-7.

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