Simulation system, method and device and storage medium

Abstract

The invention provides a simulation system for simulating logic system design. The system comprises: a first hardware simulation tool configured to implement the core particle assembly; the control device is connected with the first hardware simulation tool, the control device is configured to obtain an encrypted file and a first secret key corresponding to the encrypted file, the encrypted file comprises at least one of a description file or a configuration file of the encrypted core particle assembly, and the first secret key corresponds to the encrypted file; the configuration file comprises a limit related to the use of the core particle component, and the description or configuration file of the core particle component is encrypted by a second key corresponding to the first key to generate the encrypted file; decrypting the encrypted file by using the first key to obtain at least one of description or configuration files of the core particle component; and sending a description of the core particle component to the first hardware simulation tool to implement the core particle component on the first hardware simulation tool.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a simulation system, method, device and storage medium. Background Art

[0002] A hardware simulation tool (e.g., a prototype verification board or a hardware emulator) can prototype and debug a logic system design including one or more modules. The logic system design can be, for example, a design for an integrated circuit (Application Specific Integrated Circuit, ASIC) or a system-on-chip (SOC) for a specific application. Therefore, the logic system design tested in the simulation tool can also be called a design under test (DUT). The simulation tool can simulate the design under test through one or more configurable components (e.g., a field programmable gate array (FPGA)), including executing various operations of the design under test, thereby testing and verifying the functions of each module of the design under test before manufacturing. By connecting a variety of peripheral daughter cards to the simulation tool, the effect of the design under test and various peripherals running as a complete system can also be tested.

[0003] As chip designs become larger, they become more and more dependent on existing module designs (also known as IP). This is especially true when using chiplets for chip design. Summary of the invention

[0004] A first aspect of the present application provides a simulation system for simulating a logic system design, wherein the logic system design includes a core-grain component and a design to be tested, and the system includes: a first hardware simulation tool configured to implement the core-grain component; and a control device connected to the first hardware simulation tool, the control device configured to: obtain an encrypted file and a first key corresponding to the encrypted file, the encrypted file including at least one of an encrypted description or configuration file of the core-grain component, the configuration file including limitations related to the use of the core-grain component, the description or configuration file of the core-grain component being encrypted via a second key corresponding to the first key to generate the encrypted file; decrypt the encrypted file using the first key to obtain at least one of the description or configuration file of the core-grain component; and send the description of the core-grain component to the first hardware simulation tool to implement the core-grain component on the first hardware simulation tool.

[0005] A second aspect of the present application provides a method for simulating a logic system design, wherein the logic system design includes a core-grain component and a design to be tested, and the method includes: obtaining an encrypted file and a first key corresponding to the encrypted file, the encrypted file including at least one of an encrypted description or configuration file of the core-grain component, the configuration file including limitations related to the use of the core-grain component, the description or configuration file of the core-grain component being encrypted via a second key corresponding to the first key to generate the encrypted file; decrypting the encrypted file using the first key to obtain at least one of the description or configuration file of the core-grain component; and sending the description of the core-grain component to a first hardware simulation tool to implement the core-grain component on the first hardware simulation tool.

[0006] A third aspect of the present application provides a non-transitory computer-readable storage medium, which stores a set of instructions for a computer, and the set of instructions is used to cause the computer to perform the method described in the second aspect when executed.

[0007] A fourth aspect of the present application provides an electronic device, comprising: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the electronic device executes the method described in the second aspect.

[0008] Through the above-mentioned device, system and method, the IP supplier of the chiplet component can use the control device to better control the use of the chiplet component at the user's site to fully protect its own intellectual property rights. At the same time, the user's use of the chiplet component is not affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1 A schematic diagram of the structure of an exemplary host according to an embodiment of the present application is shown.

[0011] Figure 2 A schematic diagram of a simulation system according to an embodiment of the present application is shown.

[0012] Figure 3 A schematic diagram of another simulation system according to an embodiment of the present application is shown.

[0013] Figure 4 A schematic diagram of a simulation system according to an embodiment of the present application is shown.

[0014] Figure 5 A flow chart of a method for simulating logic system design according to an embodiment of the present application is shown.

[0015] Figure 6 A schematic diagram of a control device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0016] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0017] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar words used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0018] As mentioned above, many large-scale chip designs now rely on chiplet technology. Chiplet technology can use existing cores produced by existing IP and package them into a chip. These existing cores can also become chiplet components.

[0019] This leads to a problem. The core component is an existing core that has been verified (even in production), but the overall chip includes an unverified DUT. Since the core component is usually a physical bare chip, the IP supplier of the core component is usually unable to provide the source code of the core component in order to protect its own design. Therefore, it is impossible to verify the core component uniformly with the DUT in digital form.

[0020] In addition, the IP supplier of the chiplet component also hopes to fully control the application scenarios of the chiplet component to ensure that the actual application scenarios match the application scenarios declared by the user. In other words, the IP supplier of the chiplet component hopes to further understand the actual situation of users' actual use of the chiplet component.

[0021] Therefore, in the context of chip design using chiplets, the need of the IP supplier of the chiplet component to protect the intellectual property security of its own design conflicts with the user's need to jointly verify the chiplet component and the design to be tested, preventing the chiplet technology from playing a better role.

[0022] Therefore, how to facilitate users to complete the verification of the entire chip while ensuring the intellectual property security of the core particle components is a technical problem that needs to be solved urgently.

[0023] Figure 1 FIG. 1 shows a schematic diagram of the structure of a host 100 according to an embodiment of the present application. The host 100 may be an electronic device running a simulation system. Figure 1 As shown, the host 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108 and a bus 110. The processor 102, the memory 104, the network interface 106 and the peripheral interface 108 are connected to each other through the bus 110 in communication with each other inside the electronic device.

[0024] Processor 102 may be a central processing unit (CPU), an image processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. Processor 102 may be used to perform functions related to the technology described in this application. In some embodiments, processor 102 may also include multiple processors integrated into a single logical component. Figure 1 As shown, the processor 102 may include a plurality of processors 102a, 102b, and 102c.

[0025] The memory 104 may be configured to store data (eg, instruction sets, computer codes, intermediate data, etc.). In some embodiments, the simulation test system for simulation test design may be a computer program stored in the memory 104. Figure 1 As shown, the data stored in the memory may include program instructions (e.g., program instructions for implementing the method for locating errors of the present application) and data to be processed (e.g., the memory may store temporary codes generated during the compilation process). The processor 102 may also access the program instructions and data stored in the memory, and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disk, a magnetic disk, a hard disk, a solid-state drive (SSD), a flash memory, a memory stick, etc.

[0026] The network interface 106 can be configured to provide communication with other external devices to the host 100 via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination thereof. It is understood that the type of network is not limited to the above specific examples. In some embodiments, the network interface 106 can include any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc., in any combination.

[0027] The peripheral interface 108 can be configured to connect the host 100 to one or more peripheral devices to achieve information input and output. For example, the peripheral devices can include input devices such as a keyboard, a mouse, a touch pad, a touch screen, a microphone, and various sensors, and output devices such as a display, a speaker, a vibrator, and an indicator light.

[0028] The bus 110 may be configured to transmit information between various components of the host 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0029] It should be noted that, although the above electronic device architecture only shows the processor 102, the memory 104, the network interface 106, the peripheral interface 108 and the bus 110, in the specific implementation process, the electronic device architecture may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above electronic device architecture may also only include the components necessary for implementing the embodiment of the present application, and does not necessarily include all the components shown in the figure.

[0030] Figure 2 A schematic diagram of a simulation system 200 according to an embodiment of the present application is shown.

[0031] like Figure 2 As shown, the simulation system 200 may include a simulation tool 202 and a host 100 connected to the simulation tool 202 .

[0032] The simulation tool 202 is a hardware system for simulating a design under test (DUT). The simulation tool 202 may be a prototype verification board or a hardware emulator. A design under test may include multiple modules. The design under test may be a combinational logic circuit, a sequential logic circuit, or a combination of the two. The simulation tool 202 may include one or more configurable circuits (e.g., FPGA) for simulating the design under test.

[0033] The simulation tool 202 may include an interface unit 2022 for communicatively coupling with the host 100 to perform communication between the host 100 and the simulation tool 202. In some embodiments, the interface unit 2022 may include one or more interfaces with electrical connection capability. For example, the interface unit 2022 may include an RS232 interface, a USB interface, a LAN port, an optical fiber interface, an IEEE1394 (FireWire interface), etc. In some embodiments, the interface unit 2022 may be a wireless network interface. For example, the interface unit 2022 may be a WIFI interface, a Bluetooth interface, etc.

[0034] The host 100 may transmit the compiled DUT, debugging instructions, etc. to the simulation tool 202 via the interface unit 2022. The simulation tool 202 may also transmit simulation data, etc. to the host 100 via the interface unit 2022.

[0035] The simulation tool 202 may also include a memory 2024 for storing simulation data (e.g., various signal values) generated by the design under test during the simulation process. In some embodiments, the signal values ​​generated by the design under test during the simulation process may be directly read by the host 100. It is understood that the memory 2024 may also be independent of the simulation tool 202, for example, using an external memory.

[0036] The simulation tool 202 may also include an FPGA 2026 for implementing the logic system design in hardware on the FPGA. It is understandable that the simulation tool 202 may include multiple FPGAs, which are only examples in the figure.

[0037] In addition to being connected to the host 100 , the emulation tool 202 may also be connected to one or more daughter cards 204 via an interface unit 2022 .

[0038] The daughter card is used to provide peripherals to the DUT to form a complete electronic system when using the simulation tool 202 for prototype verification. Prototype verification refers to a verification method that restores the actual use scenario of the chip as much as possible before the chip is taped out to verify whether the chip function is accurate and complete. The daughter card 204 can include a memory daughter card (for example, providing a DDR memory interface), a communication daughter card (for example, providing multiple network interfaces or a wireless network card interface), etc.

[0039] The host 100 can be used to configure the simulation tool 202 to simulate a design to be tested. The design to be tested can be a complete logic system design or one or more modules of a complete logic system design. In some embodiments, the host 100 can be a virtual host in a cloud computing system. The logic system design (e.g., ASIC or System-On-Chip) can be designed by a hardware description language (e.g., Verilog, VHDL, System C, or System Verilog). The host 100 configuration simulation tool 202 may include configuring the simulation environment (e.g., the connection relationship between multiple simulation tools 202 or the connection relationship between the simulation tool and the daughter card), etc.

[0040] The host 100 may compile the logic system design in the form of source code into an executable file. From a design perspective, the logic system design may include a design to be tested and a test bench (Testbench) corresponding to the design to be tested.

[0041] From the perspective of synthesis, the logic system design may include a synthesizable part and a non-synthesizable part. The synthesizable part usually corresponds to the actual physical design (e.g., a chip), while the non-synthesizable part usually includes an initialization module, a test bench, etc. The executable file formed by the non-synthesizable part after compilation can usually be run by the host 100. The synthesizable part also needs to be synthesized after compilation to form a bit file. The bit file can be used to configure the FPGA 2026 to run according to the design requirements of the synthesizable part.

[0042] The host 100 may also receive a request from a user to debug the design to be tested. As described above, the design to be tested may include one or more modules. The description of the design to be tested may be completed in a hardware description language. The host 100 may perform synthesis based on the description of the design to be tested to generate, for example, a gate-level circuit netlist (not shown) of the design to be tested. The gate-level circuit netlist of the design to be tested may be loaded into the simulation tool 202 for operation, and then a circuit structure corresponding to the design to be tested may be formed in the simulation tool 202. Therefore, the circuit structure of the design to be tested may be obtained according to the description, and accordingly, the circuit structure of each block in the design to be tested may also be obtained similarly.

[0043] It is understandable that in the scenario of applying core-grain technology, the entire simulation system may include multiple hardware simulation tools (e.g., prototype verification or hardware emulators), each of which may be used to configure a core-grain component (e.g., an existing core). As described above, a core-grain component is usually a logic system design or a component of a logic system design that has been verified and therefore does not require further verification of its own functions and designs.

[0044] Figure 3A schematic diagram of another simulation system 300 according to an embodiment of the present application is shown.

[0045] like Figure 3 As shown, the simulation system 300 may include a hardware simulation tool 302 configured with a design to be tested and hardware simulation tools 304-310 configured with core particle components. It is understood that Figure 3 The connection method in the figure is only exemplary, and the user can configure the connection between the hardware simulation tools 302-310 according to the actual connection between the design to be tested and each core particle component. The host 100 is not shown in the figure. It can be understood that the host 100 and the hardware simulation tools 302-310 are directly or indirectly connected.

[0046] In this way, by connecting multiple hardware simulation tools, it is possible to build a simulation system 300 for a complete chip design including the design to be tested.

[0047] By executing the simulation task through the simulation system 300 , sufficient verification of the complete chip design can be achieved.

[0048] The core components configured in the hardware simulation tool 304-310 can come from different IP suppliers. Since the IP supplier cannot provide source code, it usually provides the user with a compiled bit file (bitfile) for configuring the hardware simulation tool. However, the bit file itself is often not encrypted (it is needed to directly configure the FPGA of the hardware simulation tool, and once encrypted, it cannot be used), and the use of the bit file is often not controlled by the IP supplier.

[0049] In order to strengthen the management of core particle components, the present application provides an innovative simulation system.

[0050] Figure 4 A schematic diagram of a simulation system 400 according to an embodiment of the present application is shown.

[0051] The simulation system 400 may include a hardware simulation tool 402, a hardware simulation tool 404, and a control device 420. It is understood that the simulation system 400 may include more hardware simulation tools.

[0052] The hardware simulation tool 402 may be configured to implement the core particle component, and the hardware simulation tool 404 may be configured to implement the design under test. In the present application, as described above, simulation may include configuring a programmable logic device (e.g., FPGA) to simulate the behavior of a logic system design, thereby allowing a user to verify in advance whether the chip design has errors without a finished chip.

[0053] It is understood that the simulation system 400 may include more hardware simulation tools for implementing the core particle components or the design to be tested. As described above, the hardware simulation tool may be a prototype verification board or a hardware simulator. It is understood that external boards such as daughter cards may be further connected to the hardware simulation tool, which is not shown here.

[0054] The control device 420 may be a separate hardware or a part of the host 100. The control device 420 is connected to the hardware emulation tool 402 and the hardware emulation tool 404. When the control device 420 is a separate hardware, in addition to being connected to the hardware emulation tool 402 and the hardware emulation tool 404, the control device 420 is also connected to the host 100 (not shown). In some embodiments, the control device 420 may also be connected to a remote control terminal (e.g., a server of an IP provider of a chiplet component).

[0055] The control device 420 may be configured to receive an encrypted file. The encrypted file 410 is provided by the IP supplier of the core particle component. The encrypted file 410 may include a description or configuration file 4104 of the core particle component 4102. The description or configuration file 4104 of the core particle component 4102 may be encrypted by a key to generate the encrypted file 410.

[0056] The description of the core-grain component 4102 may be a source file of the core-grain component or a bit file after synthesis.

[0057] Configuration file 4104 may include limitations related to the use of the description of coregrain component 4102. For example, configuration file 4104 may include the identity (ID) of hardware simulation tool 402 used to implement the description of coregrain component 4102; the identity (e.g., MAC address or network address, etc.) of control device 420 or host connected to hardware simulation tool 402; the time (e.g., 1 month) during which the description of coregrain component 4102 can be effectively run on hardware simulation tool 402; or the network address of a remote control terminal connected to control device 420; etc. In some embodiments, configuration file 4104 may also include information of a design to be tested that runs in conjunction with coregrain component 4102 and the identity of hardware simulation tool 404 that implements the design to be tested.

[0058] The control device 420 can control the core grain component 4102 to run on the hardware simulation tool 402 according to the configuration file 4104. For example, when the network address of the control device to which the hardware simulation tool 402 where the core grain component 4102 is located is connected does not match the information in the configuration file 4104, the control device 420 can send an instruction to request the hardware simulation tool 402 to stop running.

[0059] In some embodiments, the control device 420 is an independent hardware and is further connected to the host 100 ( Figure 4 In some other embodiments, the control device 420 is a part of the host 100. For example, the control device 420 may be the host 100 running specific control software.

[0060] The embodiment of the present application also provides a method for simulating logic system design. Figure 5 A flow chart of a method 500 for simulating a logic system design according to an embodiment of the present application is shown. The logic system design includes a core particle component and a design to be tested. The method 500 may include the following steps.

[0061] In step 502, an encrypted file and a first key corresponding to the encrypted file are obtained, the encrypted file including at least one of an encrypted description or configuration file of the core-grain component, the configuration file including limitations related to the use of the core-grain component, the description or configuration file of the core-grain component is encrypted via a second key corresponding to the first key to generate the encrypted file.

[0062] In step 504, the encrypted file is decrypted using the first key to obtain at least one of the description or configuration file of the coregrain component.

[0063] In step 506 , the description of the coregrain component is sent to a first hardware simulation tool to implement the coregrain component on the first hardware simulation tool.

[0064] In step 508, the operation of the core particle component on the first hardware simulation tool is controlled according to the configuration file.

[0065] The configuration file includes: an identity of the first hardware simulation tool, an identity of a control device connected to the first hardware simulation tool, a time during which the description of the core particle component is allowed to run on the first hardware simulation tool, or at least one of a network address of a remote control terminal connected to the control device.

[0066] Figure 6 A schematic diagram of a control device 420 according to an embodiment of the present application is shown.

[0067] like Figure 6 As shown, the control device 420 may include a memory 602 for storing a set of instructions; and at least one processor 604 configured to execute the set of instructions so that the electronic device performs the above method.

[0068] The embodiment of the present application further provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores a set of instructions for a computer, and the set of instructions is used to cause the computer to perform the above method when executed.

[0069] Through the above-mentioned device, system and method, the IP supplier of the chiplet component can use the control device to better control the use of the chiplet component at the user's site to fully protect its own intellectual property rights. At the same time, the user's use of the chiplet component is not affected.

[0070] Some embodiments of the present application are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0071] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of simplicity.

[0072] Although the present application has been described in conjunction with specific embodiments of the present application, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the discussed embodiments.

[0073] This application is intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A simulation system for simulating logic system design, wherein: The logic system design includes a core particle component and a design to be tested, and the system includes: a first hardware simulation tool configured to implement the core particle component; and A control device connected to the first hardware simulation tool, wherein the control device is configured as follows: Obtaining an encrypted file and a first key corresponding to the encrypted file, wherein the encrypted file includes at least one of an encrypted description or configuration file of the core-grain component, the configuration file includes restrictions related to the use of the core-grain component, and the description or configuration file of the core-grain component is encrypted by a second key corresponding to the first key to generate the encrypted file; decrypting the encrypted file using the first key to obtain at least one of a description or a configuration file of the coregrain component; and The description of the coregrain component is sent to the first hardware emulation tool to implement the coregrain component on the first hardware emulation tool.

2. The system of claim 1, further comprising: A second hardware simulation tool is configured to implement the design to be tested, wherein the control device is also connected to the second hardware simulation tool.

3. The system of claim 1, wherein: The configuration file includes: At least one of the identity of the first hardware simulation tool, the identity of the control device connected to the first hardware simulation tool, the time allowed for the description of the core particle component to run on the first hardware simulation tool, or the network address of the remote control terminal connected to the control device.

4. The system of claim 1 or 3, wherein: The control device is also configured as: The operation of the core particle component on the first hardware simulation tool is controlled according to the configuration file.

5. A method for simulating logic system design, wherein: The logic system design includes a core particle component and a design to be tested, and the method includes: Obtaining an encrypted file and a first key corresponding to the encrypted file, wherein the encrypted file includes at least one of an encrypted description or configuration file of the core-grain component, the configuration file includes restrictions related to the use of the core-grain component, and the description or configuration file of the core-grain component is encrypted by a second key corresponding to the first key to generate the encrypted file; decrypting the encrypted file using the first key to obtain at least one of a description or a configuration file of the coregrain component; and The description of the coregrain component is sent to a first hardware emulation tool to implement the coregrain component on the first hardware emulation tool.

6. The method of claim 5, wherein: The configuration file includes: At least one of the identity of the first hardware simulation tool, the identity of the control device connected to the first hardware simulation tool, the time allowed for the description of the core particle component to run on the first hardware simulation tool, or the network address of the remote control terminal connected to the control device.

7. The method of claim 5 or 6, further comprising: The operation of the core particle component on the first hardware simulation tool is controlled according to the configuration file.

8. A non-transitory computer-readable storage medium storing a set of instructions for a computer, the set of instructions being used to cause the computer to perform the method according to any one of claims 5 to 7 when executed.

9. A control device comprising: a memory for storing a set of instructions; and at least one processor configured to execute the set of instructions so that the control device performs the method according to claims 5-7.

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