Circuit simulation analysis method and device, storage medium and electronic equipment

Abstract

The invention discloses a circuit simulation analysis method and device, a storage medium and electronic equipment, and relates to the technical field of circuits, and the method comprises the steps: firstly, obtaining circuit nodes corresponding to a circuit netlist, circuit simulation variables distributed on the circuit nodes, and classification information of the circuit simulation variables; generating a circuit matrix corresponding to the circuit simulation variable; determining a target precondition corresponding to the current time step according to whether the precondition corresponding to the previous time step of the current time step of the solving circuit matrix is multiplexed or not; and finally, solving the circuit matrix based on the target precondition corresponding to the current time step, and obtaining a simulation analysis result corresponding to the circuit simulation variable. According to the method, the circuit matrix solution is accelerated by using the specially designed precondition subs, and whether the precondition subs corresponding to the previous time step can be multiplexed or not is judged, so that the generation time of the precondition subs corresponding to the current time step can be effectively shortened, the solution time and memory consumption of the circuit matrix are remarkably reduced, and the circuit matrix solution efficiency is improved. And the simulation analysis efficiency of the circuit is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a circuit simulation analysis method, device, storage medium and electronic device. Background Art

[0002] Large-scale integrated circuit simulation is the foundation of modern integrated circuit electronic design automation (EDA). Accurate circuit simulation analysis results can provide important references for circuit designers, help improve circuit design and increase chip yield.

[0003] At present, in the process of obtaining circuit simulation analysis results, related technologies widely use sparse matrix direct method solvers to solve circuit matrices.

[0004] However, the computational complexity of solving the circuit matrix using the direct method solver in the related art is relatively high. As the circuit scale increases, the solution time and memory consumption of the circuit matrix increase too fast, resulting in low efficiency in obtaining circuit simulation analysis. Summary of the invention

[0005] In view of this, the present application provides a circuit simulation analysis method, device, storage medium and electronic device, the main purpose of which is to improve the current related technology that uses a direct method solver to solve the circuit matrix, which has a high computational complexity. As the circuit scale increases, the solution time and memory consumption of the circuit matrix increase too quickly, which leads to a technical problem of low efficiency in obtaining circuit simulation analysis.

[0006] In a first aspect, the present application provides a circuit simulation analysis method, comprising:

[0007] Obtaining circuit nodes corresponding to the circuit netlist, circuit simulation variables distributed on the circuit nodes, and classification information thereof;

[0008] Generate a circuit matrix corresponding to the circuit simulation variable;

[0009] Determine a target preconditioner corresponding to the current time step according to whether the preconditioner corresponding to the previous time step of the current time step of solving the circuit matrix is ​​reused;

[0010] The circuit matrix is ​​solved based on the target preconditioner corresponding to the current time step to obtain simulation analysis results corresponding to the circuit simulation variables.

[0011] Optionally, determining the target preconditioner corresponding to the current time step according to solving whether the preconditioner corresponding to the previous time step of the current time step of the circuit matrix is ​​reused includes:

[0012] Obtaining a preconditioner corresponding to a previous time step of the current time step, wherein the preconditioner is obtained by dividing the circuit matrix;

[0013] The target preconditioner corresponding to the current time step is determined according to whether the preconditioner corresponding to the previous time step of the current time step meets the preset reuse condition.

[0014] Optionally, determining the target preconditioner corresponding to the current time step according to whether the preconditioner corresponding to the previous time step of the current time step satisfies a preset reuse condition includes:

[0015] If the preconditioner corresponding to the previous time step of the current time step satisfies the preset reuse condition, the preconditioner corresponding to the previous time step of the current time step is determined as the target preconditioner corresponding to the current time step;

[0016] If the preconditioner corresponding to the previous time step of the current time step does not meet the preset reuse condition, the preconditioner corresponding to the previous time step of the current time step is updated, and the updated preconditioner is determined as the target preconditioner corresponding to the current time step.

[0017] Optionally, solving the circuit matrix based on the target preconditioner corresponding to the current time step to obtain the simulation analysis result corresponding to the circuit simulation variable includes:

[0018] Based on the target preconditioner corresponding to the current time step, obtaining a preconditioner equation group corresponding to the circuit matrix in the current time step;

[0019] Solve the precondition equation group to obtain simulation analysis results corresponding to the circuit simulation variables.

[0020] Optionally, generating a circuit matrix corresponding to the circuit simulation variable includes:

[0021] Determine a submatrix corresponding to the circuit simulation variable according to a connection relationship of circuit nodes corresponding to the circuit simulation variable;

[0022] Based on the sub-matrix, a circuit matrix corresponding to the circuit simulation variable is generated.

[0023] Optionally, obtaining a circuit node corresponding to the circuit netlist, circuit simulation variables distributed on the circuit node, and classification information thereof, includes:

[0024] Classifying the circuit nodes corresponding to the circuit netlist using a branch tree to determine the types of the circuit nodes;

[0025] According to the type of the circuit node, circuit simulation variables and classification information thereof distributed on the circuit node are obtained.

[0026] In a second aspect, the present application provides a circuit simulation analysis device, comprising:

[0027] An acquisition module is configured to acquire circuit nodes corresponding to the circuit netlist, circuit simulation variables distributed on the circuit nodes, and classification information thereof;

[0028] A generating module, configured to generate a circuit matrix corresponding to the circuit simulation variable;

[0029] A determination module is configured to determine a target preconditioner corresponding to a current time step according to whether a preconditioner corresponding to a previous time step of solving the current time step of the circuit matrix is ​​reused;

[0030] The acquisition module is configured to solve the circuit matrix based on the target preconditioner corresponding to the current time step to obtain the simulation analysis results corresponding to the circuit simulation variables.

[0031] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the circuit simulation analysis method described in the first aspect is implemented.

[0032] In a fourth aspect, the present application provides an electronic device, comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor implements the circuit simulation analysis method described in the first aspect when executing the computer program.

[0033] In a fifth aspect, the present application provides a computer program product, which includes a computer program, and is characterized in that when the computer program is executed by a processor, it implements the circuit simulation analysis method described in the first aspect.

[0034] By means of the above technical scheme, the present application provides a circuit simulation analysis method, device, storage medium and electronic device. Compared with the current existing technology, the present application can first obtain the circuit nodes corresponding to the circuit netlist, the circuit simulation variables distributed on the circuit nodes and their classification information; then generate a circuit matrix corresponding to the circuit simulation variables; then determine the target preconditioner corresponding to the current time step based on whether the preconditioner corresponding to the previous time step of the current time step of the circuit matrix is ​​reused; finally, solve the circuit matrix based on the target preconditioner corresponding to the current time step to obtain the simulation analysis results corresponding to the circuit simulation variables. By using specially designed preconditioners to accelerate the solution of the circuit matrix and judging whether the preconditioner corresponding to the previous time step of the current time step is reused, the generation time of the target preconditioner corresponding to the current time step can be reduced, thereby reducing the solution time and memory consumption of the circuit matrix, and effectively improving the simulation analysis efficiency of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0037] Figure 1 A schematic diagram of a flow chart of a circuit simulation analysis method provided in an embodiment of the present application is shown;

[0038] Figure 2 A schematic diagram of a flow chart of a circuit simulation analysis method provided in an embodiment of the present application is shown;

[0039] Figure 3 A schematic diagram showing an example provided by an embodiment of the present application;

[0040] Figure 4 A schematic diagram showing an example provided by an embodiment of the present application;

[0041] Figure 5 A schematic diagram showing an example provided by an embodiment of the present application;

[0042] Figure 6 A schematic diagram showing an example provided by an embodiment of the present application;

[0043] Figure 7 A schematic diagram showing an example provided by an embodiment of the present application;

[0044] Figure 8 A schematic diagram showing an example provided by an embodiment of the present application;

[0045] Fig. 9 A schematic diagram showing an example provided by an embodiment of the present application;

[0046] Fig.10 A schematic diagram showing an example provided by an embodiment of the present application;

[0047] Fig.11 A schematic structural diagram of a circuit simulation analysis device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0048] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0049] At present, the solution process of circuit matrix solution using direct method solver can be divided into four parts: preprocessing, symbolic decomposition, numerical decomposition and forward-backward substitution. In the preprocessing stage, the matrix will be reordered. Symbolic decomposition can obtain the non-zero element structure of L and U matrices after matrix decomposition by eliminating the dependency between tree structure prediction variables. In the numerical decomposition stage, the non-zero elements are filled into the matrix structure through real numerical operations. However, this method increases the solution time and memory consumption too fast as the circuit scale increases.

[0050] In order to improve the current related technology using direct method solver to solve the circuit matrix with high computational complexity, as the circuit scale increases, the circuit matrix solution time and memory consumption increase too fast, thus resulting in low efficiency in obtaining circuit simulation analysis. This embodiment provides a circuit simulation analysis method, such as Figure 1 As shown, the method includes:

[0051] Step 101: Obtain circuit nodes corresponding to the circuit netlist, circuit simulation variables distributed on the circuit nodes, and classification information thereof.

[0052] Among them, the circuit netlist can be a text file used for circuit topology and component parameters, which may include circuit node number, component type (such as resistors, capacitors, inductors, diodes, transistors, voltage sources, current sources, etc.), component connection relationships, component parameters (resistance value, capacitance value, inductance value, etc.) and other information.

[0053] In some embodiments, simulation tools can be used to extract circuit topology and component parameters from the circuit netlist, determine all circuit nodes in the circuit, and identify circuit simulation variables distributed on each circuit node, such as node voltage, branch current, etc., based on the connection relationship between each circuit node and other components, and classify the circuit simulation variables to obtain classification information of the circuit simulation variables, such as circuit simulation variables on power branches, circuit simulation variables on general linear nodes, etc. Specifically, simulation-related parameters, such as time step, frequency range, etc., can also be set to simulate and analyze the circuit structure corresponding to the circuit netlist, predict the performance of the circuit, and verify whether the circuit design meets expectations.

[0054] For example, in transistor-level circuit simulation, transistors, resistors, capacitors and other components can be used to describe the designed circuit, and the corresponding differential-algebraic equation (DAE) can be constructed according to Kirchhoff's law and solved by numerical methods. Correspondingly, in the field of integrated circuit design, SPICE can be used to solve it, and SPICE can provide a DAE model for circuit simulation and the corresponding numerical solution process.

[0055] Step 102: Generate a circuit matrix corresponding to the circuit simulation variables.

[0056] In some embodiments, the circuit matrix can be a set of linear or nonlinear equations describing the circuit behavior generated according to the circuit structure and component parameters, based on Kirchhoff's laws and the volt-ampere characteristic equations of the components, and then the set of equations is solved by numerical methods to obtain circuit simulation variables, thereby converting the circuit problem into a set of equations solving problem.

[0057] Exemplarily, the circuit simulation variables may be arranged in a preset order, and then the sub-matrices corresponding to the respective circuit simulation variables may be determined according to the definitions of the respective circuit simulation variables, and an initial block matrix may be generated according to the sub-matrices as the circuit matrix corresponding to the circuit simulation variables.

[0058] Step 103: Determine the target preconditioner corresponding to the current time step according to whether the preconditioner corresponding to the previous time step of the current time step of solving the circuit matrix is ​​reused.

[0059] In some examples, the target preconditioner may be the preconditioner corresponding to the current time step, and the target preconditioner may be selected as close as possible to the original matrix to reduce the condition number of the circuit matrix, thereby accelerating the convergence speed of the iterative solver and reducing the solution time; wherein, the preconditioner can be used to accelerate the process of iterative solution of the circuit matrix.

[0060] In some embodiments, at the beginning of the current time step, it can be checked whether the preconditioner used in the previous time step of the current time step is still applicable to the current time step. Exemplarily, it can be determined whether the preconditioner of the previous time step meets the preset reuse conditions, for example, the circuit structure has not changed significantly, the component parameters have changed slightly, the matrix condition number has not deteriorated, etc. If the reuse conditions are met, the preconditioner of the previous time step can continue to be used as the target preconditioner of the current time step; otherwise, the preconditioner can be regenerated as the target preconditioner corresponding to the current time step.

[0061] In this way, the generation time of the target preconditioner corresponding to the current time step can be further reduced, thereby reducing the solution time and memory consumption of the circuit matrix, reducing the time of circuit simulation analysis, and improving the efficiency of obtaining circuit simulation results.

[0062] Step 104: Solve the circuit matrix based on the target preconditioner corresponding to the current time step to obtain simulation analysis results corresponding to the circuit simulation variables.

[0063] In some embodiments, during each iterative solution process, the target preconditioner corresponding to the current time step is determined, and the circuit matrix is ​​converted into a preconditioner matrix using the target preconditioner. By solving the preconditioner equation group, the simulation analysis results corresponding to the circuit simulation variables are obtained, thereby simplifying the solution process, accelerating the convergence speed of the iterative solver, reducing the solution time, and thus improving the simulation analysis efficiency of the circuit.

[0064] Compared with the current existing technology, this embodiment can first obtain the circuit nodes corresponding to the circuit netlist, the circuit simulation variables distributed on the circuit nodes and their classification information; then generate a circuit matrix corresponding to the circuit simulation variables; then determine the target preconditioner corresponding to the current time step according to whether the preconditioner corresponding to the previous time step of the current time step of the circuit matrix is ​​reused; finally, solve the circuit matrix based on the target preconditioner corresponding to the current time step to obtain the simulation analysis results corresponding to the circuit simulation variables. By using specially designed preconditioners to accelerate the solution of the circuit matrix and judging whether the preconditioner corresponding to the previous time step of the current time step is reused, the generation time of the target preconditioner corresponding to the current time step can be reduced, thereby reducing the solution time and memory consumption of the circuit matrix, and effectively improving the simulation analysis efficiency of the circuit.

[0065] In order to further illustrate the specific implementation process of the method of this embodiment, this embodiment provides the following Figure 2 The specific method shown includes:

[0066] Step 201: Classify the circuit nodes corresponding to the circuit netlist using a branch tree to determine the types of the circuit nodes.

[0067] For example, in a circuit simulator, one may use Figure 3The branch tree shown classifies the types of circuit nodes. In this way, for each circuit, only one node type classification is required. Specifically, it can be first determined whether the node is connected to the power supply. If it is connected, it is marked as a coupling node. If not, it is further determined whether it is connected to a device. If so, it is further determined whether it is connected to a linear element and marked as an interface node and a device node respectively. If the node is not connected to any device, all neighbor nodes of the node are traversed. If at least one of its neighbor nodes is connected to a device, the node is marked as an isolated linear node, otherwise it is marked as a linear node.

[0068] For example, Figure 4 As shown, an example circuit is shown, which contains a total of 7 linear elements: 5 resistors, 2 capacitors, 2 nonlinear devices: 1 diode, 1 transistor, and 1 independent voltage source. Among them, nodes 1, 5, and 6 are only connected to linear circuit elements, node 7 is only connected to nonlinear devices, nodes 8, 9, and 10 are connected to linear elements and devices at the same time, and nodes 2 and 3 are directly connected to the power supply. Observe node 1. Since all its neighboring nodes (nodes 3, 9, and 10) are not linear nodes, node 1 can be classified as an isolated linear node. Accordingly, the specific classification of the circuit nodes of this example circuit is as follows:

[0069] (1) Linear node: A circuit node that is connected only to linear elements (resistors, capacitors, etc.), e.g. Figure 4 Middle nodes 1, 5, and 6.

[0070] (2) Device node: A circuit node that is only connected to nonlinear devices (BJT, MOSFET, etc.), e.g. Figure 4 Middle node 7.

[0071] (3) Interface node (port): A circuit node that is connected to both linear and nonlinear devices and is not connected to any power source, such as Figure 4 Middle nodes 8, 9, 10.

[0072] (4) Coupled node: A circuit node that is connected to at least one power source, such as Figure 4 Middle nodes 2 and 3.

[0073] (5) Isolated linear node: If a circuit node is a linear node and all its neighboring nodes are not linear nodes, it is called an isolated linear node. For example Figure 4 Middle node 1.

[0074] (6) General linear node (linear): If a circuit node belongs to a linear node and does not belong to an isolated linear node, it is called a general linear node, for example Figure 4 Mid nodes 5 and 6.

[0075] Optionally, before the entire simulation process begins, the circuit model needs to be reduced to reduce the scale of the problem to be solved. After that, the SPICE simulator needs to perform a DC operating point analysis to place the devices in the circuit in the correct operating area. Common DC operating point analysis methods include the pseudo-transient method, the homology method, and the GMIN stepping method commonly used in SPICE. After obtaining the initial value of the DAE system through the DC operating point analysis, the SPICE simulator first calls the time integral solver to time discretize the DAE and obtains a set of nonlinear algebraic systems in each time step. Next, the SPICE simulator will call the nonlinear equations solver to solve it, and the nonlinear solver needs to call the sparse matrix solver to solve the residual linear equations. In the entire simulation process, the solution of the sparse matrix occupies a lot of simulation time, and its performance is crucial to the circuit simulator.

[0076] Step 202: According to the type of the circuit node, obtain the circuit simulation variables and classification information distributed on the circuit node.

[0077] In some embodiments, the circuit simulation variables may include circuit unknown variables, which are distributed on circuit nodes. According to the classification of the circuit nodes in step 201, the following classification of the circuit unknown variables may be given:

[0078] i: unknown variable of current in the power branch;

[0079] v lin : The voltage at a general linear node is an unknown variable;

[0080] v slin : The voltage unknown variable on the isolated linear node;

[0081] v dev : The voltage on the device node is an unknown variable;

[0082] v port : The voltage on the interface node is an unknown variable;

[0083] v cp : The voltage on the coupling node is an unknown variable.

[0084] Step 203: Generate a circuit matrix corresponding to the circuit simulation variables.

[0085] Optionally, step 203 may specifically include: determining a sub-matrix corresponding to the circuit simulation variable according to a connection relationship of circuit nodes corresponding to the circuit simulation variable; and generating a circuit matrix corresponding to the circuit simulation variable based on the sub-matrix.

[0086] In some embodiments, based on the classification of the circuit unknown variables in step 202, the circuit unknown variables are classified according to x=(v slin ,v cp ,i,v lin ,v dev ,v port ), are arranged in the order of. According to the definition of circuit unknown variables, the circuit matrix Has the following form:

[0087]

[0088] Specifically, the circuit matrix has the above form mainly for the following three reasons:

[0089] (1) The current variable i is defined in the power branch. In the circuit, the power supply is only connected to the coupling node, so the submatrix J 13 ,J 31 ,J 34 ,J 43 ,J 35 ,J 53 ,J 36 ,J 63 All are zero matrices;

[0090] (2) Voltage variable v dev The node is only connected to nonlinear devices, so the submatrix J 15 ,J 51 ,J 45 ,J 54 are all zero matrices. However, due to v port The node is connected to both the device and the linear element, and the submatrix J 56 ,J 65 Still a zero matrix;

[0091] (3) According to the definition of an isolated node, all its neighboring nodes do not contain linear nodes, so the submatrix J 14 ,J 41 are all zero matrices.

[0092] In addition, according to the definition of an isolated node, all its neighboring nodes are not linear nodes, let alone isolated linear nodes, so the matrix J 11 is a diagonal matrix. By reclassifying and sorting the variables, the circuit matrix has the above-mentioned circuit matrix with a special sparse structure.

[0093] Step 204: Determine the target preconditioner corresponding to the current time step according to whether the preconditioner corresponding to the previous time step of the current time step of solving the circuit matrix is ​​reused.

[0094] Optionally, step 204 may specifically include: obtaining a preconditioner corresponding to a previous time step of the current time step, the preconditioner being obtained by dividing the circuit matrix; and determining a target preconditioner corresponding to the current time step according to whether the preconditioner corresponding to the previous time step of the current time step satisfies a preset multiplexing condition.

[0095] For example, the block circuit matrix Divide as follows:

[0096]

[0097] Accordingly, a preconditioner may be constructed according to the above division, and the preconditioner may include a Schur Block Jacobi preconditioner, a Block Jacobi preconditioner, and the like.

[0098] For example, the Schur Block Jacobi preconditioner P SBJ It can be expressed as:

[0099]

[0100] in, is the Schur-complement matrix The block diagonal approximation of .

[0101] For example, the Block Jacobi preconditioner P BJAC It can be expressed as:

[0102]

[0103] is a simple block diagonal approximation of the circuit matrix after reordering and partitioning. It should be noted that when the circuit to be solved does not contain any isolated linear nodes, the preconditioning matrix P = P SBJ Degenerates to P = P BJAC .

[0104] In some embodiments, the target preconditioner corresponding to the current time step is determined based on whether the preconditioner corresponding to the previous time step of the current time step satisfies the preset reuse condition, which may specifically include: if the preconditioner corresponding to the previous time step of the current time step satisfies the preset reuse condition, the preconditioner corresponding to the previous time step of the current time step is determined as the target preconditioner corresponding to the current time step; if the preconditioner corresponding to the previous time step of the current time step does not satisfy the preset reuse condition, the preconditioner corresponding to the previous time step of the current time step is updated, and the updated preconditioner is determined as the target preconditioner corresponding to the current time step.

[0105] For example, Figure 5As shown, a flow chart of circuit simulation using the preconditioning iteration method is shown. Specifically, the circuit netlist may be first parsed, and then the circuit structure may be analyzed, and the unknown variables (such as voltage and current) may be sorted. The system matrix and the right-hand side items may be generated according to the circuit structure, and then it may be determined whether the preconditioner needs to be reused. If the preconditioner does not need to be reused, the preconditioner may be regenerated. After the preconditioner is determined, the system linear equations may be solved using an iterative method, and it may be determined whether the nonlinear equation solver converges. If the nonlinear solver does not converge, the current time step may be rolled back and returned to the step of "generating the system matrix and the right-hand side items". The device model may be updated after adjusting the time step, and the current time step simulation may be performed again. If the nonlinear solver converges, it may be checked whether the time integration is ended. If it is found that the time integration is not ended, it may be returned to the step of "generating the system matrix and the right-hand side items". If it is found that the time integration is ended, the simulation result may be output.

[0106] Step 205: Based on the target preconditioner corresponding to the current time step, obtain the preconditioner equation group corresponding to the circuit matrix in the current time step.

[0107] In specific application scenarios, the number of isolated linear nodes varies greatly. slin When the ratio exceeds a certain value, it will affect P=P BJAC The iterative efficiency of the preconditioner, in this case, we need to choose P = P SBJ To solve.

[0108] Accordingly, whether P = P BJAC Still P=P SBJ The preconditioner, in the preconditioned GMRES iteration method, ultimately comes down to solving the preconditioned equations. The preconditioned equations can be expressed as:

[0109] Pv=z.

[0110] Step 206: Solve the precondition equation group to obtain simulation analysis results corresponding to the circuit simulation variables.

[0111] In some embodiments, solving the preconditioner equations can ultimately be reduced to solving the following two block matrices on the main diagonal of the preconditioners:

[0112]

[0113] Correspondingly, for the matrix M 11 , whose matrix elements are only distributed on the main diagonal, can be solved by simply taking the inverse. Due to its small size, the direct method solver is used to solve it. The algebraic multigrid (AMG) method can be used for solving the problem. Figure 6 As shown in the figure, the basic principle of the AMG method is shown, which can polish the initial residual to eliminate high-frequency errors, then project it to a coarser space and further polish it, repeating this process until the number of unknown variables in the coarse space is small enough to be solved accurately, and then interpolate the errors at each level to a finer space to obtain the final solution.

[0114] In some examples, simulation analysis results may be generated based on circuit simulation variables obtained by solving a set of preconditioned equations. For example, waveforms corresponding to the circuit simulation variables may be output, and corresponding result reports may be generated to facilitate circuit analysis.

[0115] As a possible implementation, Figure 7 As shown, a transistor-level circuit simulation flow chart is shown, and the circuit simulation technical solution may specifically include the following steps:

[0116] (1) Input: circuit netlist, simulation related parameter settings;

[0117] (2) Traverse the netlist to obtain circuit connectivity information;

[0118] (3) Classify and reorder all unknown variables according to the circuit node type branch judgment tree;

[0119] (4) Generate an initial block matrix J;

[0120] (5) If #v slin >tol*M, then generate the preconditioning matrix P=P SBJ , otherwise generate the preconditioning matrix P = P BJAC ;

[0121] (6) Start time integration stepping:

[0122] (7) Start nonlinear iteration:

[0123] (8) If the preconditioning matrix is ​​not reused, then update the preconditioning matrix P, otherwise reuse the previous preconditioning matrix;

[0124] (9) Update the matrix J and the right-hand term b;

[0125] (10) Call the GMRES iteration method to solve Δx = gmres (J, P, Δx0, b, m);

[0126] (11) Update the iterative solution x new =x old +Δx;

[0127] (12) Repeat steps (8) to (11) until the nonlinear equation system converges;

[0128] (13) Repeat steps (7) to (12) until the time integration method completes all time integration steps;

[0129] (14) Output: circuit simulation results.

[0130] Exemplarily, it is assumed that the number of unknown variables n of the simulated circuit is composed of the following parts:

[0131] n=n slin +n cp +n i +n lin +n dev +n port .

[0132] Then, the time complexity of this embodiment is The space complexity is The time complexity of the sparse matrix direct method solver in related technologies is as high as The space complexity is as high as It can be seen that the method of this embodiment has a faster solution speed and a smaller storage space.

[0133] Accordingly, Figure 8 A schematic diagram of the comparison of the iterative residual reduction curves of the incomplete LU decomposition preconditioned iterative solution algorithm (dashed line) and the preconditioned iterative solution algorithm GMRES proposed in this embodiment (solid line) is shown. This embodiment has better convergence and stability, and can quickly reduce the residual of the iterative solution; Fig. 9 The fitting curves of the solution time of the third-party direct method solvers MKLPARDISO, KLU, SuperLU, MUMPS, CKTSO and the preconditioned iterative solution algorithm (This Work) proposed in this embodiment as a function of the matrix dimension are shown. It can be seen that the solution time of this embodiment changes slowly with the increase of the matrix dimension, which can reduce the time of simulation analysis. Fig.10 The solution time and peak memory usage of the third-party direct method solver MKL PARDISO and the preconditioned iterative solution algorithm proposed in this embodiment (This Work) are compared case by case. It can be seen that the solution time and memory consumption of this embodiment are lower, which indicates that the solution method proposed in this embodiment has lower space complexity.

[0134] In some embodiments, a circuit simulation analysis can be performed on a server with a Linux system, which is equipped with two Intel (R) Xeon (R) Gold 6140 CPUs (18 cores, 2.30 GHz) and 188 GB of memory. The circuit matrices involved in the embodiments are all from different types of actual circuits. Table 1 shows the statistical information of unknown variables, non-zero elements, zero diagonal elements and positive non-diagonal elements of the test circuit matrix.

[0135] Table 1

[0136]

[0137] Next, the convergence criterion of the overall iterative solution is given:

[0138] ‖P -1 (b-AΔx n )‖2 <rtol*‖P -1 (b-AΔx0)‖2.

[0139] And the convergence criterion of the preconditioned equation Pz=v:

[0140]

[0141] Where z = [z (1)T ,z (2)T ,z (3)T ] T ,v=[v (1)T ,v (2)T ,v (3)T ] T In summary, the overall solution accuracy of the circuit matrix is ​​controlled by the overall relative residual threshold rtol, and the solution accuracy of the preconditioning equation is controlled by irtol. A higher preconditioning equation solution progress means fewer outer layer iteration steps, but may also lead to more inner layer preconditioning equation submatrix iteration steps. Therefore, it is crucial to strike a balance between the overall convergence speed and solution time.

[0142] In some embodiments, the method of this embodiment can be compared with the existing direct method solvers to analyze the solution time and acceleration ratio data. Accordingly, Table 2 shows the comparison of the solution time data (second) of the third-party direct method solvers MKL PARDISO, KLU, SuperLU, MUMPS, CKTSO and the preconditioned iterative solution algorithm proposed in this embodiment when the overall relative residual threshold rtol=1e-6, as well as the acceleration ratio data of the method of this invention relative to the third-party direct method solvers.

[0143] Table 2

[0144]

[0145] Specifically, when rtol=1e-6 and irtol=1e-1 are selected, compared with the direct method solvers KLU and CKTSO optimized for circuit matrices, for the 11 circuit test cases examined, the preconditioning iterative solution strategy proposed in this embodiment is accelerated by an average of 1.67× and 2.43×, respectively. When the scale of the circuit matrix considered is large, the iterative solution strategy proposed in this embodiment can obtain a greater acceleration ratio than the direct method solver. Specifically, when rtol=1e-6 and irtol=1e-1 are selected, compared with the direct method solvers KLU and CKTSO optimized for circuit matrices, for the 6 circuit test cases with dimensions greater than 2.00e+06 examined, the preconditioning iterative solution strategy proposed in this embodiment is accelerated by an average of 2.50× and 3.07×, respectively. Sp1 to Sp5 in Table 2 respectively represent the solution acceleration ratios of the method of this embodiment compared with MKL PARDISO, KLU, SuperLU, MUMPS and CKTSO.

[0146] Specifically, we can assume that the linear solver solution time varies with the matrix dimension and satisfies the following time complexity model T = aM b ,The time complexity fitting coefficients corresponding to different sparse matrix solvers are obtained by using nonlinear fitting method as shown in Table 3, which shows that the actual test of the sparse matrix solver proposed in this embodiment has The time complexity of the preconditioned iterative solution algorithm is thus more suitable for solving large-scale circuit matrix problem. Table 3 shows the time complexity fitting coefficients of the third-party direct method solvers MKL PARDISO, KLU, SuperLU, MUMPS, CKTSO and the preconditioned iterative solution algorithm proposed in this embodiment.

[0147] Table 3

[0148]

[0149] Compared with the current existing technology, this embodiment can use a branch tree to classify the circuit nodes corresponding to the circuit netlist. For each circuit, only one node type classification is required, and according to the preset reuse condition, it is determined whether the target preconditioner corresponding to the current time step reuses the preconditioner corresponding to the previous time step of the current time step, and by solving the preconditioner equation group, the simulation analysis results corresponding to the circuit simulation variables are obtained. By means of the preconditioner iteration method, the solution time is effectively reduced, the time complexity and space complexity are reduced, and it has better convergence and stability.

[0150] Further, as Figure 1 and Figure 2 The specific implementation of the method shown in the embodiment provides a circuit simulation analysis device, such as Fig.11 As shown, the device includes: an acquisition module 31, a generation module 32, and a determination module 33.

[0151] An acquisition module 31 is configured to acquire circuit nodes corresponding to the circuit netlist, circuit simulation variables distributed on the circuit nodes, and classification information thereof;

[0152] A generating module 32, configured to generate a circuit matrix corresponding to the circuit simulation variable;

[0153] A determination module 33 is configured to determine a target preconditioner corresponding to a current time step according to whether a preconditioner corresponding to a previous time step of a current time step of solving a circuit matrix is ​​reused;

[0154] The acquisition module 34 is configured to solve the circuit matrix based on the target preconditioner corresponding to the current time step, and obtain the simulation analysis results corresponding to the circuit simulation variables.

[0155] In some examples of this embodiment, the determination module 33 is specifically configured to obtain a preconditioner corresponding to a previous time step of the current time step, where the preconditioner is obtained by dividing the circuit matrix; and determine a target preconditioner corresponding to the current time step based on whether the preconditioner corresponding to the previous time step of the current time step satisfies a preset multiplexing condition.

[0156] In some examples of the present embodiment, the determination module 33 is specifically configured to determine the preconditioner corresponding to the previous time step of the current time step as the target preconditioner corresponding to the current time step if the preconditioner corresponding to the previous time step of the current time step satisfies the preset reuse condition; if the preconditioner corresponding to the previous time step of the current time step does not satisfy the preset reuse condition, update the preconditioner corresponding to the previous time step of the current time step, and determine the updated preconditioner as the target preconditioner corresponding to the current time step.

[0157] In some examples of this embodiment, the acquisition module 31 is specifically configured to acquire a set of preconditioned equations corresponding to the circuit matrix in the current time step based on the target preconditioner corresponding to the current time step; solve the set of preconditioned equations to acquire simulation analysis results corresponding to the circuit simulation variables.

[0158] In some examples of this embodiment, the generation module 32 is specifically configured to determine the sub-matrix corresponding to the circuit simulation variable according to the connection relationship of the circuit nodes corresponding to the circuit simulation variable; and generate the circuit matrix corresponding to the circuit simulation variable based on the sub-matrix.

[0159] In some examples of this embodiment, the acquisition module 31 is specifically configured to classify the circuit nodes corresponding to the circuit netlist using a branch tree to determine the type of the circuit node; and obtain the circuit simulation variables and their classification information distributed on the circuit nodes according to the type of the circuit node.

[0160] It should be noted that for other corresponding descriptions of the functional units involved in the circuit simulation analysis device provided in this embodiment, reference can be made to Figure 1 and Figure 2 The corresponding description in will not be repeated here.

[0161] Based on the above Figure 1 and Figure 2 The method shown in the embodiment also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned Figure 1 and Figure 2 The method shown.

[0162] Based on this understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, USB flash drive, mobile hard disk, etc.), including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of the present application.

[0163] Based on the above Figure 1 and Figure 2 The method shown, and Fig.11 In order to achieve the above-mentioned purpose, the embodiment of the present application also provides an electronic device, such as a personal computer, a server, which includes a storage medium and a processor; the storage medium is used to store a computer program; the processor is used to execute the computer program to achieve the above-mentioned Figure 1 and Figure 2 The method shown.

[0164] Optionally, the above-mentioned physical device may also include a user interface, a network interface, a camera, a radio frequency (RF) circuit, a sensor, an audio circuit, a WI-FI module, etc. The user interface may include a display, an input unit such as a keyboard, etc., and the optional user interface may also include a USB interface, a card reader interface, etc. The network interface may optionally include a standard wired interface, a wireless interface (such as a WI-FI interface), etc.

[0165] Those skilled in the art will appreciate that the above-mentioned physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or a combination of certain components, or different arrangements of components.

[0166] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the above-mentioned physical device, and supports the operation of the information processing program and other software and / or programs. The network communication module is used to realize the communication between the components inside the storage medium, and the communication with other hardware and software in the information processing physical device.

[0167] Through the description of the above implementation methods, those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform, or by hardware. By applying the solution of this embodiment, compared with the current prior art, this embodiment can classify the circuit nodes corresponding to the circuit netlist using a branch tree, and for each circuit, only one node type classification is required, and whether the target preconditioner corresponding to the current time step reuses the preconditioner corresponding to the previous time step of the current time step according to the preset reuse condition, and by solving the preconditioner equation group, the simulation analysis results corresponding to the circuit simulation variables are obtained, and by means of the preconditioner iteration method, the solution time is effectively reduced, the time complexity and space complexity are reduced, and better convergence and stability are achieved.

[0168] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0169] The above is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features applied for herein.

Claims

1. A circuit simulation analysis method, characterized in that: include: Obtaining circuit nodes corresponding to the circuit netlist, circuit simulation variables distributed on the circuit nodes, and classification information thereof; Generate a circuit matrix corresponding to the circuit simulation variable; Determine a target preconditioner corresponding to the current time step according to whether the preconditioner corresponding to the previous time step of the current time step of solving the circuit matrix is ​​reused; The circuit matrix is ​​solved based on the target preconditioner corresponding to the current time step to obtain simulation analysis results corresponding to the circuit simulation variables.

2. The method according to claim 1, characterized in that The determining of the target preconditioner corresponding to the current time step according to solving whether the preconditioner corresponding to the previous time step of the current time step of the circuit matrix is ​​reused comprises: Obtaining a preconditioner corresponding to a previous time step of the current time step, wherein the preconditioner is obtained by dividing the circuit matrix; The target preconditioner corresponding to the current time step is determined according to whether the preconditioner corresponding to the previous time step of the current time step meets the preset reuse condition.

3. The method according to claim 2, characterized in that The step of determining the target preconditioner corresponding to the current time step according to whether the preconditioner corresponding to the previous time step of the current time step satisfies the preset reuse condition comprises: If the preconditioner corresponding to the previous time step of the current time step satisfies the preset reuse condition, the preconditioner corresponding to the previous time step of the current time step is determined as the target preconditioner corresponding to the current time step; If the preconditioner corresponding to the previous time step of the current time step does not meet the preset reuse condition, the preconditioner corresponding to the previous time step of the current time step is updated, and the updated preconditioner is determined as the target preconditioner corresponding to the current time step.

4. The method according to claim 3, characterized in that The step of solving the circuit matrix based on the target preconditioner corresponding to the current time step to obtain the simulation analysis results corresponding to the circuit simulation variables includes: Based on the target preconditioner corresponding to the current time step, obtaining a preconditioner equation group corresponding to the circuit matrix in the current time step; Solve the precondition equation group to obtain simulation analysis results corresponding to the circuit simulation variables.

5. The method according to claim 1, characterized in that: The generating a circuit matrix corresponding to the circuit simulation variable comprises: Determining a submatrix corresponding to the circuit simulation variable according to a connection relationship of circuit nodes corresponding to the circuit simulation variable; Based on the sub-matrix, a circuit matrix corresponding to the circuit simulation variable is generated.

6. The method according to claim 5, characterized in that The obtaining of the circuit nodes corresponding to the circuit netlist, the circuit simulation variables distributed on the circuit nodes and their classification information includes: Classifying the circuit nodes corresponding to the circuit netlist using a branch tree to determine the types of the circuit nodes; According to the type of the circuit node, circuit simulation variables and classification information thereof distributed on the circuit node are obtained.

7. A circuit simulation analysis device, characterized in that: include: An acquisition module is configured to acquire circuit nodes corresponding to the circuit netlist, circuit simulation variables distributed on the circuit nodes, and classification information thereof; A generating module, configured to generate a circuit matrix corresponding to the circuit simulation variable; A determination module is configured to determine a target preconditioner corresponding to a current time step according to whether a preconditioner corresponding to a previous time step of solving the current time step of the circuit matrix is ​​reused; The acquisition module is configured to solve the circuit matrix based on the target preconditioner corresponding to the current time step to obtain the simulation analysis results corresponding to the circuit simulation variables.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

9. An electronic device comprising a storage medium, a processor, and a computer program stored in the storage medium and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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