A Functional Test Strategy Method for Multi-Layer Motherboards Based on Reliability Analysis

Abstract

The present invention relates to a functional test strategy method for a multi-layer motherboard based on reliability analysis, belonging to the technical field of electrical digital data processing, and includes the following steps: Step 1: Construct a functional parameter model of the multi-layer motherboard; Step 2: Construct a reliability model of the multi-layer motherboard; Step 3: According to the reliability model, determine the key test nodes of each layer of the multi-layer motherboard; Step 4: Test each layer of the multi-layer motherboard according to the key test nodes, and record the test data of each layer of the motherboard; Step 5: Analyze the test data of each layer of the motherboard, and compare and analyze the test data of each layer of the motherboard according to the reliability model to determine whether the multi-layer motherboard meets the reliability requirements; The beneficial effects of the present invention: If the reliabilities of each layer of the motherboard are the same or different, the total reliability of the multi-layer motherboard can be calculated. If one of the reliabilities of each layer of the motherboard does not have reliability, the total reliability of the multi-layer motherboard does not have reliability.

Description

Technical Field

[0001] The present invention belongs to the technical field of electrical digital data processing, and particularly relates to a functional test strategy method for a multi-layer motherboard based on reliability analysis. Background Art

[0002] A multi-layer motherboard often has multiple functions, including high-speed data transmission and multi-channel communication. When writing a test program for a multi-layer motherboard, it is difficult to test all the functions of the multi-layer motherboard, and it is easy to miss some special function tests of the multi-layer motherboard, resulting in potential problems in the multi-layer motherboard not being discovered in time.

[0003] Generally, when testing some special performances of a multi-layer motherboard, specific algorithms are required for data processing and analysis. If the specific algorithm itself has defects or is not accurate enough, it may misjudge the functional status of the multi-layer motherboard, judge a normal multi-layer motherboard as having problems, and may let go of a multi-layer motherboard with real problems. Therefore, it is necessary to test the functions of the multi-layer motherboard. Summary of the Invention

[0004] The present invention provides a functional test strategy method for a multi-layer motherboard based on reliability analysis, which is used to solve the technical problem of how to perform reliability testing and analysis on the functions of the multi-layer motherboard. The total reliability of the multi-layer motherboard is the product of the reliabilities of each layer of the motherboard. If the reliabilities of each layer of the motherboard are the same or different, the total reliability of the multi-layer motherboard can be calculated. If one of the reliabilities of each layer of the motherboard does not have reliability, the total reliability of the multi-layer motherboard does not have reliability.

[0005] In order to achieve the above object, the present invention is realized through the following technical solutions:

[0006] A functional test strategy method for a multi-layer motherboard based on reliability analysis includes the following steps:

[0007] Step 1: Construct a functional parameter model of the multi-layer motherboard , where the functional parameter model of the multi-layer motherboard includes electrical performance parameters and thermal performance parameters ;

[0008] Step 2: Construct a reliability model of the multi-layer motherboard. The reliability model is established based on the functional parameter model of the multi-layer motherboard, and the reliability model considers the conductivity between each layer of the motherboard and the heat dissipation efficiency between each layer of the motherboard;

[0009] Step 3: According to the reliability model, determine the key test nodes of each layer of the multi-layer motherboard. The key test nodes are the positions that have a greater impact on the motherboard function and are prone to failures in the reliability model;

[0010] Step 4: Test each layer of the multi-layer motherboard according to the key test nodes, and record the test data of each layer of the motherboard;

[0011] Step 5: Analyze the test data of each layer of the motherboard, compare and analyze the test data of each layer of the motherboard according to the reliability model, judge whether the multi-layer motherboard meets the reliability requirements, and if not, locate the position where the fault occurs.

[0012] Optionally, in Step 1, the electrical performance parameters include signal transmission delay and crosstalk;

[0013] Evaluating the signal transmission delay is to evaluate the distortion of the transmitted signal or the timing delay of the transmitted signal;

[0014] Crosstalk is the interference of the transmitted signals between two adjacent lines, and the quantitative analysis of crosstalk is estimated by electromagnetic simulation.

[0015] Optionally, in Step 1, the thermal performance parameter is mainly the thermal conductivity. The thermal conductivity of each layer of the multi-layer motherboard determines the heat conduction speed of the heat in the entire multi-layer motherboard. For the equivalent thermal conductivity of the multi-layer motherboard, the thermal conductivity of each layer of the motherboard is required. For a multi-layer motherboard containing layers, if the materials of each layer of the multi-layer motherboard are different, then the equivalent thermal conductivity is calculated by the formula: , where is the total thickness of the multi-layer motherboard, and are the thermal conductivity and the thickness of the th motherboard layer and the th motherboard layer, respectively.

[0016] Optionally, in Step 2, if the failures of each layer of the motherboard are independent of each other, and the failure of any one layer of the motherboard causes the failure of the entire multi-layer motherboard, and a multi-layer motherboard contains layers, then the total reliability of the multi-layer motherboard is the product of the reliabilities of each layer of the motherboard, specifically: , if the reliabilities of each layer of the motherboard are the same, then ;

[0017] Optionally, if a multi-layer motherboard contains layers, and the reliability of each layer of the motherboard is , , then the total reliability of the multi-layer motherboard is, , if the reliabilities of all layers of the motherboard are the same , then: .

[0018] Optionally, in step three, based on the reliability model, the testing of the key test nodes of each layer of the multi-layer motherboard is to test the thermal fatigue life of the key test nodes of each layer of the motherboard through Coffin-Manson software, and the thermal fatigue life is , where and are material constants, is the temperature change range.

[0019] Optionally, in step three, the correlation matrix method is used to determine the key test nodes of each layer of the multi-layer motherboard. Specifically: construct a correlation matrix, where the rows represent the fault locations and the columns represent the key test nodes. The matrix element represents the correlation degree between the th fault location and the th test node. The correlation degree can be quantified according to experience or historical data, and the value range of the correlation degree is -1 to 1. -1 indicates a perfect negative correlation, 0 indicates no correlation, and 1 indicates a strong correlation;

[0020] When determining the key test nodes, the sum of the correlations between each key test node and all fault locations can be calculated , where is the number of fault locations. The larger the value, the higher the correlation between the test node and the fault location, and the more likely it is to be a key test node.

[0021] Optionally, in step four, each layer of the multi-layer motherboard is tested according to the key test nodes. Among them, the electrical performance parameters are tested by the through-hole array conductivity test, and the heat dissipation efficiency is tested by the interlayer thermal resistance test;

[0022] The through-hole array conductivity test is: ; where is the number of open holes of each layer of the motherboard, is the number of short-circuited holes of each layer of the motherboard, is the total number of test holes of each layer of the motherboard; is the total conductivity of the through-holes of each layer of the motherboard;

[0023] The interlayer thermal resistance test is: ; where is the thickness of each layer of the motherboard; is the thermal conductivity of each layer of the motherboard, is the heat dissipation area of each layer of the motherboard, is the interface thermal resistance of each layer of the motherboard, is the thermal resistance of each layer of the motherboard.

[0024] Optionally, in step five, the steps for comparing and analyzing the test data of each layer of the main board are as follows:

[0025] Step a: Construct a test data matrix;

[0026] Step b: Conduct comparative analysis on multiple groups of data;

[0027] Step c: Generate a decision matrix; among them, formulate a priority improvement plan according to the analysis results:

[0028] Step d: Establish a reliability analysis report.

[0029] Advantages of the present invention:

[0030] 1. The failures of each layer of the main board of the present invention are independent of each other, and the failure of any one layer of the main board causes the failure of the entire multi-layer main board. Then, the total reliability of the multi-layer main board is the product of the reliabilities of each layer of the main board. Whether the reliabilities of each layer of the main board are the same or different, the total reliability of the multi-layer main board can be calculated. If one of the reliabilities of each layer of the main board does not have reliability, the total reliability of the multi-layer main board does not have it.

[0031] 2. The thermal conductivity of the present invention is that the materials of each layer of the main board of the multi-layer main board are different, and the thermal conductivities of each layer of the main board are different. The thermal conductivities of each layer of the main board of the multi-layer main board are calculated to obtain an equivalent thermal conductivity. The equivalent thermal conductivity makes the heat inside the entire multi-layer main board evenly distributed on each layer of the main board, determines the heat conduction speed inside the entire multi-layer main board, and at the same temperature of each layer of the main board and the total thickness of the entire multi-layer main board, by making the heat of different materials equivalent, the thermal conductivities of each layer of the main board of the entire multi-layer main board are the same, and the heat conduction speed inside the entire multi-layer main board is the same.

[0032] 3. The correlation matrix method is used to determine the key test nodes of each layer of the main board of the multi-layer main board, that is, construct a correlation matrix. The degree of correlation can be quantified according to experience or historical data. The value range of the degree of correlation is -1 to 1. -1 indicates complete negative correlation, 0 indicates no correlation, and 1 indicates strong correlation; when determining the key test nodes, the sum of the correlations between each key test node and all failure positions can be calculated. The higher the sum of the correlations between the test node and the failure position, the more likely it is to be a key test node. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0034] Figure 1 This is a schematic diagram of the working process of the present invention.

[0035] Figure 2 This is a flowchart for analyzing the test data of each layer of the main board of the present invention. Specific implementation manner

[0036] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0037] A multi-layer main board function test strategy method based on reliability analysis includes the following steps:

[0038] Step 1: Construct a functional parameter model of the multi-layer main board , where the functional parameter model of the multi-layer main board includes electrical performance parameters and thermal performance parameters , the electrical performance parameters include signal transmission delay and crosstalk;

[0039] Step 2: Construct a reliability model of the multi-layer main board. The reliability model is established based on the functional parameter model of the multi-layer main board, and the reliability model considers the conductivity between each layer of the main board and the heat dissipation efficiency between each layer of the main board;

[0040] Step 3: According to the reliability model, determine the key test nodes of each layer of the multi-layer main board. The key test nodes are the positions that have a greater impact on the main board function and are prone to failures in the reliability model;

[0041] Step 4: Test each layer of the multi-layer main board according to the key test nodes, and record the test data of each layer of the main board;

[0042] Step 5: Analyze the test data of each layer of the main board, compare and analyze the test data of each layer of the main board according to the reliability model, and determine whether the multi-layer main board meets the reliability requirements. If not, locate the position where the failure occurs (find the position prone to failure through the correlation of the key test nodes).

[0043] In step 1, evaluating the signal transmission delay is to evaluate the distortion situation of the transmitted signal or the timing delay situation of the transmitted signal. Specifically, evaluating the signal transmission delay is , where is the transmission delay, is the line length (i.e., the fiber length), is the propagation speed of the signal in the medium (such as: fiber), , is the speed of light in vacuum, is the relative dielectric constant of the medium;

[0044] Crosstalk is the interference of transmission signals between two adjacent lines. Crosstalk is related to the spacing between lines (optical fibers), signal frequency, and medium. The quantitative analysis of crosstalk is estimated through electromagnetic simulation. The quantitative analysis of crosstalk in electromagnetic simulation is the crosstalk analysis of microstrip lines, that is , is the crosstalk coefficient (e.g., coupling voltage or power ratio), is the signal frequency, is the driving signal voltage, is the spacing between adjacent transmission lines, is the thickness of the microstrip line medium, has the same meaning. In parallel microstrip lines, the core method to reduce crosstalk is to increase the spacing between adjacent transmission lines , reduce the thickness of the microstrip line medium , reduce the signal frequency or reduce the driving signal voltage .

[0045] In parallel microstrip lines, the crosstalk noise is calculated as: , where is the mutual capacitance, is the self-capacitance, is the source signal voltage. When the self-capacitance remains unchanged, the larger the mutual capacitance and the source signal voltage , the larger the crosstalk noise ; when the mutual capacitance and the source signal voltage remain unchanged, the larger the self-capacitance , the smaller the crosstalk noise .

[0046] Thermal performance parameters are mainly thermal conductivity. The thermal conductivity of each layer of the multi-layer motherboard determines the heat conduction speed within the entire multi-layer motherboard. Specifically, for a multi-layer motherboard, the equivalent thermal conductivity requires the thermal conductivity of each layer of the motherboard. The thermal conductivity of each layer of the motherboard is determined by the material, and the thermal conductivities of each layer of the motherboard are respectively , and the thicknesses of each layer of the motherboard are respectively . For a multi-layer motherboard containing layers, that is, the materials of each layer of the multi-layer motherboard are different, then the thermal conductivities of each layer of the motherboard are subjected to equivalent calculations to obtain the equivalent thermal conductivity . The calculation formula for the equivalent thermal conductivity is expressed as: , where is the total thickness of the multi-layer motherboard, and They are respectively the thermal conductivity of the main board (wherein, the thermal conductivities of each layer of the main board can be the same or different) and the thickness of the main board, to obtain the total thickness of the entire multi-layer main board and the equivalent thermal conductivity of each layer of the main board .

[0047] is to perform equivalent calculation on the different thermal conductivities of each layer of the main board to obtain a multi-layer main board with an equivalent thermal conductivity of the material. At the same temperature of each layer of the main board and the total thickness of the entire multi-layer main board, by making the heat of different materials equivalent, the thermal conductivities of each layer of the main board of the entire multi-layer main board are the same, and the heat conduction speed inside the entire multi-layer main board is the same.

[0048] In step two, a multi-layer main board includes layers. If the failures of each layer of the main board are independent of each other, and the failure of any one layer of the main board causes the failure of the entire multi-layer main board, then the total reliability of the multi-layer main board is the product of the reliabilities of each layer of the main board. Specifically: , if the reliabilities of each layer of the main board are the same, then ; if one of the reliabilities of each layer of the main board does not have reliability, then the total reliability of the multi-layer main board does not have.

[0049] If a multi-layer main board includes layers, and the reliabilities of each layer of the main board are respectively , is the value of reliability, is the reliability of the first layer of the main board, is the layer of the main board's reliability, is the layer of the main board's reliability, and the reliabilities of each layer of the main board are the same, , then the total reliability of the multi-layer main board is, , if the reliabilities of all layers of the main board are the same , then: . In addition, even if the reliabilities of each layer of the main board are not the same and there is no main board without reliability among the reliabilities of each layer of the main board, the total reliability of the multi-layer main board still exists.

[0050] In step three, based on the reliability model, the testing of the key test nodes of each layer of the main board of the multi-layer main board is to test the thermal fatigue life of the key test nodes of each layer of the main board through Coffin-Manson software, and the thermal fatigue life is ;

[0051] and is a material constant (to be calibrated through experiments), is the temperature change range. That is, the thermal fatigue life of the key test nodes of each layer of the main board is tested.

[0052] For example, for a certain material at = 200, = 1.2×105, = 1.2×105, then ≈ 275 cycles.

[0053] In step three, the correlation matrix method is used to determine the key test nodes of each layer of the multi-layer main board. Specifically: construct a correlation matrix, that is, assume there are key test nodes , then the dimension of the correlation matrix is , where represents the correlation coefficient between test nodes and . The rows represent the fault positions, and the columns represent the key test nodes. The matrix element represents the degree of correlation between the th fault position and the th test node. For two test nodes and , the calculation formula for the Pearson correlation coefficient is:

[0054] ;

[0055] where and are the data values of test nodes and in the th test respectively, and are the average values of test nodes and respectively, is the number of tests.

[0056] The degree of correlation can be quantified according to experience or historical data. The value range of the degree of correlation is -1 to 1. being -1 indicates complete negative correlation, being 0 indicates no correlation, being 1 indicates strong correlation;

[0057] Suppose there are three key test nodes , and , and the correlation matrix calculated after multiple tests is as follows:

[0058] ;

[0059] It can be seen from this matrix that and have a strong positive correlation (correlation coefficient is 0.8), and also have a certain positive correlation (correlation coefficient is 0.6), while and have a weak correlation (correlation coefficient is -0.3).

[0060] When determining the key test nodes, the sum of the correlations between each key test node and all fault locations can be calculated as , where is the number of fault locations, The larger the value, the higher the correlation between the test node and the fault location, and the more likely it is to be a key test node.

[0061] In step four, each layer of the multi-layer motherboard is tested according to the key test nodes. Among them, the electrical performance parameter is tested by the through-hole array conductivity test, and the heat dissipation efficiency is tested by the interlayer thermal resistance test;

[0062] The through-hole array conductivity test is: ; where is the number of open holes of each layer of the motherboard, is the number of short-circuited holes of each layer of the motherboard, is the total number of test holes of each layer of the motherboard; is the total conductivity of the through-holes of each layer of the motherboard; for example, the total number of test holes of the first layer of the motherboard is , is used to calculate the total conductivity of the through-holes of the first layer of the motherboard. Similarly, the total number of test holes of the second layer of the motherboard is , is used to calculate the total conductivity of the through-holes of the second layer of the motherboard.

[0063] The interlayer thermal resistance test is: ; where is the thickness of each layer of the motherboard; is the thermal conductivity of each layer of the motherboard, is the heat dissipation area of each layer of the motherboard, is the interface thermal resistance of each layer of the motherboard, is the thermal resistance of each layer of the motherboard.

[0064] In step five, the steps for comparing and analyzing the data are as follows:

[0065] Step a: Construct a test data matrix;

[0066] Merge all test data types into a matrix and directly calculate the total scores of all types through matrix multiplication;

[0067] (1) Construct a test data matrix:

[0068] ; where is the coverage score, is the construction complexity score, is the error detection ability score, is the maintenance cost score.

[0069] (2) Construct the calculation of the total score vector:

[0070] ; where is the weight vector, , is the weight of the coverage score, is the weight of the construction complexity score, is the weight of the error detection ability score, is the weight of the maintenance cost score, is the distribution of weights, that is is to evaluate the level of each weight in the weight vector.

[0071] For example: Use 6 test data types (i.e., 6 functions of the motherboard), the test data matrix and the weight vector are:

[0072] , ;

[0073] The total score vector is: ;

[0074] Organize the test data of each layer of the motherboard into a matrix form for systematic comparison. Each row represents a layer of the motherboard (e.g., Layer1, Layer2…):

[0075]

[0076] Step b: Conduct comparative analysis on multiple groups of data; among them, adopt the differential comparative analysis method, that is, calculate the performance fluctuation of different batches of the same motherboard layer (the deviation from the specification center is the correlation between the key test nodes and the fault location):

[0077]

[0078] Step c: Generate a decision matrix; that is, formulate a priority improvement plan based on the analysis results:

[0079]

[0080] Step d: Establish a reliability analysis report;

[0081] Use a script (Python + Pandas + ReportLab) to output the decision matrix analysis results as a PDF / Excel report, including:

[0082] 1. Comparison table of key test points; such as: comparison information table of the correlation between key test points;

[0083] 2. Difference heat map and circuit diagram; The difference heat map is a visual chart that represents the degree of data difference through the depth of color. It usually maps data values to different colors. The darker the color, the greater the difference, and the lighter the color, the smaller the difference. The combination of the difference heat map and the circuit diagram reflects different colors on the circuit.

[0084] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope recorded in the present invention can easily think of changes or substitutions, which should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A multi-layer motherboard functional test strategy method based on reliability analysis, characterized in that: The steps include: Step 1: Build a functional parameter model of a multi-layer motherboard , where the functional parameter model of the multi-layer motherboard includes electrical performance parameters and thermal performance parameters ; Step 2: Construct a reliability model of a multi-layer motherboard. The reliability model is established based on a functional parameter model of the multi-layer motherboard. The reliability model takes into account the conductivity between each layer of the motherboard and the heat dissipation efficiency between each layer of the motherboard. In the step 2, one of the multi-layer motherboards comprises If the failure of each layer of the motherboard is independent of each other, and the failure of any layer of the motherboard leads to the failure of the entire multi-layer motherboard, then the total reliability of the multi-layer motherboard is the product of the reliability of each layer of the motherboard, specifically: , if the reliability of each layer of motherboard is the same, is the reliability value, then ; Step 3: According to the reliability model, determine the key test nodes of each layer of the multi-layer motherboard, where the key test nodes are the locations that have a greater impact on the motherboard function and are prone to failure in the reliability model; In the step 3, the correlation matrix method is used to determine the key test nodes of each layer of the multi-layer motherboard, specifically: construct a correlation matrix, the rows represent the fault locations, the columns represent the key test nodes, and the matrix elements Indicates The fault location and The degree of correlation between the test nodes is quantified based on experience or historical data. The value range of the correlation degree is -1~1, where -1 indicates a completely negative correlation, 0 indicates no correlation, and 1 indicates a strong correlation; When determining the key test nodes, calculate the sum of the correlations between each key test node and all fault locations ,in, is the number of fault locations, The larger the value, the higher the correlation between the test node and the fault location, and the more critical the test node is; Step 4: Test each layer of the multi-layer motherboard according to key test nodes, and record the test data of each layer of the motherboard; Step 5: Analyze the test data of each layer of the motherboard, compare and analyze the test data of each layer of the motherboard according to the reliability model, and determine whether the multi-layer motherboard meets the reliability requirements. If not, locate the location of the fault.

2. The multi-layer motherboard functional test strategy method based on reliability analysis according to claim 1 is characterized in that: In step 1, the electrical performance parameter Including signal transmission delay and crosstalk; Evaluating the signal transmission delay is evaluating the transmission signal distortion or the transmission signal timing delay; The crosstalk is the mutual interference of transmission signals between two adjacent lines, and the quantitative analysis of the crosstalk is estimated through electromagnetic simulation.

3. The multi-layer motherboard functional test strategy method based on reliability analysis according to claim 1 is characterized in that: In step 1, the thermal performance parameter Mainly thermal conductivity. The thermal conductivity of each layer of the multi-layer motherboard determines the heat conduction speed inside the entire multi-layer motherboard. The equivalent thermal conductivity of the multi-layer motherboard requires the thermal conductivity of each layer of the motherboard. For a multi-layer motherboard including Layer, the materials of each layer of the multi-layer motherboard are different, so the equivalent thermal conductivity The calculation formula is expressed as: ,in, is the total thickness of the multi-layer motherboard, and They are The thermal conductivity of the motherboard and The thickness of the motherboard.

4. The multi-layer motherboard functional test strategy method based on reliability analysis according to claim 1 is characterized in that: In step 2, if one of the multi-layer motherboards includes The reliability of each motherboard is , is the reliability value, For the reliability of the 1st layer motherboard, For the The reliability of the motherboard, For the The reliability of the motherboard layer. Specifically, the reliability of each motherboard layer is , is the reliability value, , then the total reliability of the multi-layer motherboard is, , if the reliability of all layers of motherboards is the same ,but: .

5. The multi-layer motherboard functional test strategy method based on reliability analysis according to claim 1 is characterized in that: In step 3, based on the reliability model, the key test nodes of each layer of the multi-layer motherboard are tested by using Coffin-Manson software to test the thermal fatigue life of the key test nodes of each layer of the motherboard. The thermal fatigue life is ,in, and is the material constant, is the temperature variation range.

6. The multi-layer motherboard functional test strategy method based on reliability analysis according to claim 1 is characterized in that: In the step 4, each layer of the multi-layer motherboard is tested according to key test nodes, wherein the electrical performance parameters are tested by through-hole array conductivity test, and the heat dissipation efficiency is tested by interlayer thermal resistance test; The through hole array conductivity test is: ;in, is the number of open holes on each layer of the motherboard, is the number of short-circuit holes on each layer of the motherboard, The total number of test holes for each layer of the motherboard; The total conductivity of the through holes of each layer of the mainboard; The interlayer thermal resistance test is: ;in, is the thickness of each layer of the main board; is the thermal conductivity of each layer of the motherboard, is the heat dissipation area of ​​each layer of the motherboard. is the interface thermal resistance of each layer of the motherboard, is the thermal resistance of each layer of the motherboard.

7. The multi-layer motherboard functional test strategy method based on reliability analysis according to claim 1 is characterized in that: In step 5, the steps of comparing and analyzing the test data of each layer of the motherboard are as follows: Step a: Construct a test data matrix; Step b: Comparative analysis of multiple groups of data; Step c: Generate a decision matrix, in which a priority improvement plan is developed based on the analysis results: Step d: Create a reliability analysis report.

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