Radio frequency modeling method of FDSOI device
By modeling the gate network, substrate effect and self-heating effect of FDSOI devices at a state higher than the separation frequency, the problem that traditional models cannot accurately model the entire frequency band is solved, and higher modeling accuracy is achieved.
Patent Information
- Application Number
- CN202411877556.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-05-16
AI Technical Summary
The traditional RF MOSFET model cannot accurately model the full frequency band of FDSOI devices, especially in small-sized devices, the self-heating effect, substrate effect and gate network effects cannot be carefully modeled.
By modeling the gate network, substrate effect and self-heating effect at a state higher than the separation frequency, the corresponding parameters are extracted to establish a radio frequency model in the full frequency band.
Accurate modeling of the full frequency band of FDSOI devices is achieved, the accuracy of the model is improved, and the behavior of the device can be effectively captured at different frequencies.
Smart Images
Figure CN120012687A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit design, and in particular to a radio frequency modeling method for a FDSOI device. Background Art
[0002] As the demand for FDSOI devices in RF, high-power and other application fields gradually increases, RF MOSFET models have become a hot topic in model research. However, as FDSOI devices develop towards smaller sizes, traditional RF models have no way to accurately model the full frequency band (1kHZ-40GHz) of the device, and for small-sized FDSOI devices, such as when the channel length of the device is less than 22nm, the existing methods do not model the self-heating effect (the self-heating effect is more serious in SOI devices) in the full frequency band, substrate effects, gate network effects, and other effects in detail. Summary of the invention
[0003] The technical problem to be solved by the present invention is to provide a full-band modeling method to improve the accuracy of the model.
[0004] In order to solve the above problems, the present invention provides a radio frequency modeling method for FDSOI devices, comprising the following steps: modeling the DC characteristics of the RF device; finding a separation frequency for dividing the self-heating effect and the substrate effect; modeling the gate network and extracting the gate parasitic network parameters when the frequency is higher than the separation frequency; modeling the substrate effect and extracting the substrate network parameters when the frequency is higher than the separation frequency; modeling the self-heating effect and extracting the self-heating parameters when the frequency is higher than the separation frequency.
[0005] Optionally, the separation frequency is 160 MHz.
[0006] Optionally, the substrate effect is further modeled by modeling the substrate effect of the device in the 160MHz-5GHz frequency band, using a small signal equivalent circuit diagram for modeling, and the substrate part is modeled in series with a capacitor and a resistor to extract parameters of substrate capacitance and substrate resistance.
[0007] Optionally, the modeling of the self-heating effect further includes modeling an RC network for characterizing the self-heating effect.
[0008] The present invention first obtains the separation frequency of the self-heating effect, substrate effect and grid network effect in the full frequency band, and then performs high-frequency modeling according to the separation frequency, so that a full-band model can be established, thereby improving the accuracy of modeling. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Attached Figure 1 Shown is a schematic diagram of simulation results of an intrinsic model adopted in a specific embodiment of the present invention.
[0010] Attached Figure 2 Shown is a frequency response diagram of the normalized output conductance of the FDSOI nMOSFET (Lg=32nm, Normalwell) used in a specific embodiment of the present invention.
[0011] Attached Figure 3 Shown is a frequency response diagram of (a) normalized output conductance and (b) drain capacitance under different gate voltages used in a specific embodiment of the present invention.
[0012] Attached Figure 4 Shown is a diagram of a gate network structure including a gate resistor and a gate capacitor used in a specific embodiment of the present invention.
[0013] Attached Figure 5 Shown is a small signal equivalent circuit diagram of an FDSOI MOSFET including a substrate and a back gate network used in a specific embodiment of the present invention.
[0014] Attached Figure 6 Shown is a schematic diagram of modeling and fitting of the device GDS using the above-mentioned gate network and substrate network adopted in a specific embodiment of the present invention.
[0015] Attached Figure 7 Shown is a first-order RC network circuit diagram used in a specific embodiment of the present invention to characterize the self-heating effect.
[0016] Attached Figure 8 Shown is a circuit diagram of an RC network modeling for characterizing the self-heating effect adopted in a specific embodiment of the present invention.
[0017] Attached Fig. 9 Shown is a frequency response diagram of gds using different network simulation fittings adopted in a specific embodiment of the present invention, showing the modeling results of the above-mentioned self-heating effect.
[0018] Attached Fig.10 This is a modeling result verification diagram for a specific implementation of the present invention, using a model simulation and measured data comparison diagram of FDSOInMOSFET with a gate length of 32nm (a) Cgg (b) |H21| (c) fT and fmax (d) real (H11).
[0019] Attached Fig.11 This is a modeling result verification diagram of a specific embodiment of the present invention, which is a data comparison diagram of the measured S parameters and the model simulated S parameters of FDSOI nMOSFET (with Lg = 32nm) under different biases.
[0020] Attached Fig.12This is a modeling result verification diagram for a specific embodiment of the present invention, using a model simulation and measured data comparison diagram of FDSOI nMOSFETs with gate lengths of 32nm and 500nm (a) Cgg (b) |H21| (c) real(H11) (d) real(Y22).
[0021] Attached Fig.13 This is a diagram for verifying the modeling results of a specific embodiment of the present invention, and is a data comparison diagram of the measured S parameters and the model-simulated S parameters of FDSOI nMOSFETs with gate lengths of 32nm and 500nm.
[0022] Attached Fig.14 Shown is a schematic diagram of the implementation steps of a specific implementation method of the RF modeling method of the FDSOI device described in the present invention. DETAILED DESCRIPTION
[0023] The specific implementation of the RF modeling method for FDSOI devices provided by the present invention is described in detail below with reference to the accompanying drawings.
[0024] Attached Fig.14 The figure shows a schematic diagram of the implementation steps of a specific implementation method of the RF modeling method of the FDSOI device described in the present invention, including: step S11, modeling the DC characteristics of the RF device; step S12, finding the separation frequency for dividing the self-heating effect and the substrate effect; step S13, modeling the gate network and extracting the gate parasitic network parameters under a state higher than the separation frequency; step S14, modeling the substrate effect and extracting the substrate network parameters under a state higher than the separation frequency; step S15, modeling the self-heating effect and extracting the self-heating parameters under a state higher than the separation frequency.
[0025] Step S11, model the DC characteristics of the RF device and establish an intrinsic model. For details of this step, see the BSIM-IMG model manual. Figure 1 The figure shows the simulation results of the intrinsic model, which lists the comparison between the simulation results and the measurement results of the IV characteristic curve model of the 22nm FDSOI process NMOS RF device. The results show that the model meets the simulation accuracy requirements.
[0026] Attached Figure 2 The figure shows the frequency response of the normalized output conductance of the FDSOI nMOSFET (Lg = 32nm, Normal well). The FDSOI nMOSFET with a gate length of 32nm is biased at V g =V d =Vdd, its output conductance increases to varying degrees in the frequency range of 1kHz to 50GHz, corresponding to different influencing factors, including dynamic self-heating effect, substrate effect and the influence of gate parasitic network.
[0027] Step S12, finding the separation frequency f that divides the self-heating effect and the substrate effect iso (isothermalfrequency). Figure 3 Frequency response diagrams of (a) normalized output conductance and (b) drain capacitance at different gate voltages. Figure 3 (a) Analysis, when V g <V ZTC From the output characteristic curve of the device, we can see that low gate voltage corresponds to larger g ds As the frequency increases, dynamic self-heating occurs, causing g ds Decreases, and then due to the influence of substrate effect g ds This part of the change can be seen in C dd It is observed in the frequency response diagram of the capacitor that Figure 3 (b) The peak of the curve indicates that the capacitance value changes from negative to positive. The frequency corresponding to the peak is the frequency point at which the dynamic self-heating effect "disappears". The temperature of the device does not change with the increase of frequency, which is called the isothermal frequency, f iso (isothermal frequency), above which the substrate effect is the influence. Figure 3 (b) C under different gate voltages dd The frequency value f corresponding to the peak of the curve iso . In V g <V ZTC Under the bias voltage, the corresponding f iso Changes such as Figure 3 As shown by the dotted arrow in (a), the extracted separation frequency is about 160 MHZ.
[0028] Step S13, when the frequency is higher than the separation frequency, the gate network is modeled at a high frequency to extract the gate parasitic network parameters Rg, Covs, Covd, Cfrs, and Cfrd.
[0029] At higher frequencies, parasitic resistance and capacitance begin to play an important role and affect the high-frequency performance of the device. Therefore, considering the important influence of gate resistance on device and circuit performance, it needs to be accurately characterized. Experiments have found that the gate network has a greater impact in the 5G-40G frequency band, so the gate network modeling is performed first. Figure 4 It is a gate network structure diagram including gate resistance and gate capacitance. The extracted parameter Rg is the gate resistance, and the extracted parameter is the overlap capacitance C between the gate to the source and drain. ovs and C ovd and the fringe capacitance C frs and C frd .
[0030] Step S14, under a condition higher than the separation frequency, the substrate effect is modeled and the substrate network parameters Csub, Rsub are extracted.
[0031] The substrate effect of the device is modeled in the 160MHz-5GHz frequency band. The following small signal equivalent circuit diagram is used for modeling. The substrate part is modeled by a capacitor and a resistor in series, and the parameters of substrate capacitance Csub and substrate resistance Rsub are extracted. Figure 5 The blue box shown is the small signal equivalent circuit diagram of FDSOI MOSFET including the substrate. The other parts in the figure are: Rg is the gate resistance, Cgb is the gate to body capacitance, Cgd is the gate to drain capacitance, Cgs is the gate to source capacitance, gd is the output admittance, gmiVg's' is the gate conductance, Cds is the drain to source capacitance, Cdb is the drain to body capacitance, Csb is the source to body capacitance, Rs is the source resistance, Rb is the body resistance, and C is the source to substrate capacitance.
[0032] Attached Figure 6 The figure shows the gds measured data and small signal equivalent circuit simulation results of FDSOI nMOSFET. Figure 6 , the device gds is modeled and fitted using the above gate network and substrate network. When Vg=0.85V, the blue curve is the simulation result, and the red dotted line data is the measured data. It can be seen that the fitting is good above 160M.
[0033] Step S15, under a state higher than the separation frequency, the self-heating effect is modeled, and the self-heating parameters are extracted: self-heating primary capacitor C1, self-heating secondary capacitor C2, self-heating primary resistor R1, and self-heating secondary resistor R2.
[0034] Below 160MHz is the stage of self-heating effect, which needs to be modeled. Figure 6 As shown, it can be seen that for g below these frequencies ds The substrate network cannot be fitted to the curve because this part is affected by the self-heating effect. The BSIM-IMG model has its own self-heating model. Figure 7 The figure shows a first-order RC network circuit diagram for characterizing the self-heating effect. Rth is the thermal resistance and Cth is the thermal capacitance. The first-order RC network is used to characterize the self-heating effect. However, it is found that the simulation cannot be done accurately in the actual modeling process. Therefore, this specific implementation adopts the attached Figure 8 Modeling of the RC network shown to characterize the self-heating effect. Extraction of parameters C1, C2, R1, R2.
[0035] Attached Fig. 9 Shown is the frequency response diagram of GDS using different network simulation fits, showing the modeling results of the above self-heating effect.
[0036] The final fitting verification results of the complete model are as follows Figure 10-13 As shown in the figure, the dots are measured data and the solid lines are model simulation results. The errors are all less than 10%, which is in line with industry standards.
[0037] This process can be implemented using commercial software such as Agilent's ADS and ICCAP, and the simulator can be HSPICE. Fig.10 Comparison of model simulation and measured data for FDSOI nMOSFET with a gate length of 32nm (a)C gg (b) | H 21 |(c)f T and f max (d)real(H 11 ). Fig.11 For FDSOI nMOSFET (with L g =32nm) under different bias conditions, the measured S parameters and the model-simulated S parameters are compared. Fig.12 Comparison of model simulation and measured data for FDSOInMOSFETs with gate lengths of 32nm and 500nm (a) gg (b)|H 21 |(c)real(H 11 )(d)real(Y 22 ). Fig.13 The figure is a data comparison chart of the measured S parameters and model-simulated S parameters of FDSOI nMOSFETs with gate lengths of 32nm and 500nm.
[0038] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A radio frequency modeling method for a FDSOI device, characterized in that: The steps include: Model the DC characteristics of RF devices; Find the separation frequency that divides the self-heating effect and the substrate effect; Under the condition of higher than separation frequency, the gate network is modeled and the gate parasitic network parameters are extracted; At frequencies above the separation frequency, the substrate effect is modeled and the substrate network parameters are extracted; In the regime above the separation frequency, the self-heating effect is modeled and the self-heating parameters are extracted.
2. The method according to claim 1, characterized in that The separation frequency is 160 MHz.
3. The method according to claim 1, characterized in that The substrate effect is further modeled in the 160MHz-5GHz frequency band. The small signal equivalent circuit diagram is used for modeling. The substrate part is modeled in series with a capacitor and a resistor, and the parameters of substrate capacitance and substrate resistance are extracted.
4. The method according to claim 1, characterized in that: The self-heating effect is modeled, and further includes modeling an RC network for characterizing the self-heating effect.