Heterogeneous architecture electronics control system and control method controlled by atomic quantum computing

Abstract

The invention discloses a heterogeneous architecture electronics control system and control method controlled by atomic quantum computing, and relates to the technical field of quantum information. The heterogeneous architecture electronics control system comprises a control core module, a resource scheduling module and a signal generation module. The control core module determines a calculation task of atomic quantum bits, determines a configuration instruction set, a scheduling instruction and a control instruction, and configures a resource scheduling module and a signal generation module; the resource scheduling module calls a processor of a calculation task; the signal generation module determines a signal generation instruction of the calculation task, so that the processor completes the calculation task. According to the heterogeneous architecture electronics control system, multivariate computing resources can be integrated, and accurate scheduling in the computing task process is achieved.

Description

Technical Field

[0001] The present application relates to the field of quantum information technology, and in particular to a heterogeneous architecture electronic control system and control method for atomic quantum computing control. Background Art

[0002] The calculation of atomic quantum bits requires precise electronic control systems and efficient processing feedback capabilities. This feedback capability specifically involves data transmission efficiency, data real-time, data processing capabilities and dynamic adjustment capabilities.

[0003] At present, there are some solutions that can solve specific problems in the process of neutral atom quantum computing through field-programmable gate arrays (FPGA), such as collecting scientific camera images, performing image recognition, sorting algorithms and other tasks, and generating radio frequency driven acousto-optic deflectors (AODs) to sort atoms.

[0004] However, the electronic control system of atomic quantum computing designed for specific links in atomic quantum bit experiments is not capable of handling the entire experimental process. For example, the design of atomic quantum computing experiments with fault-tolerant design requires the flexible scheduling of peripheral resources such as RF, analog, and digital interfaces. For another example, the experimental design that uses atomic quantum bits to process image data online, generates decisions based on the processing results, and executes decisions, only has specific links to be optimized, and still cannot meet the requirements of the full process experiment.

[0005] The contents of the background technology are merely technologies known to the public and do not necessarily represent the existing technologies in the field. Summary of the invention

[0006] The present application aims to provide a heterogeneous architecture electronic control system and control method for atomic quantum computing control to solve the above-mentioned technical problem of being unable to meet the full-process experimental requirements.

[0007] According to an embodiment of one aspect of the present application, the present application provides a heterogeneous architecture electronic control system for atomic quantum computing control. The heterogeneous architecture electronic control system includes a control core module, a resource scheduling module, and a signal generation module. The control core module responds to user instructions to determine the computing task of the atomic quantum bit. The control core module determines the configuration instruction set, scheduling instructions, and control instructions according to the computing task. The control core module configures the resource scheduling module, the signal generation module, and the data processing module according to the configuration instruction set; the resource scheduling module calls the processor of the computing task according to the scheduling instruction; the signal generation module determines the signal generation instruction of the computing task according to the control instruction, so that the processor completes the computing task.

[0008] According to some embodiments of the present application, the processor includes a central processing unit, a graphics processing unit and a field programmable gate array; the resource scheduling module also calls at least one of the central processing unit, the graphics processing unit and the field programmable gate array according to the scheduling instruction.

[0009] According to some embodiments of the present application, a heterogeneous architecture electronic control system also includes a data processing module; a control core module configures the data processing module according to a configuration instruction set; a signal generation module determines a signal generation instruction for a computing task according to the control instruction; the signal generation module, the data processing module and the control core module execute a feedback control instruction determination step at least once, including: the data processing module executes atomic cooling and collects a first atomic fluorescence image according to the signal generation instruction; the data processing module determines the existence state data of the atomic quantum bit according to the first atomic fluorescence graph; the signal generation module determines and executes quantum gate manipulation of the atomic quantum bit according to the signal generation instruction; after executing the quantum gate manipulation, the data processing module collects a second atomic fluorescence image; the data processing module determines the quantum state data of the atomic quantum bit according to the second atomic fluorescence image; the control core module also determines the feedback control instruction according to the existence state data of the atomic quantum bit, so that the processor completes the computing task.

[0010] According to some embodiments of the present application, the control core module also generates feedback control instructions based on a preset atomic sorting strategy and the existence status data of the atomic quantum bits.

[0011] According to some embodiments of the present application, the heterogeneous architecture electronic control system also includes a quantum error correction module; the control core module configures the quantum error correction module according to the configuration instruction set; the quantum error correction module generates error correction control instructions based on the existence status data of the atomic quantum bit and the quantum state data of the atomic quantum bit.

[0012] According to an embodiment of one aspect of the present application, the present application provides a control method for a heterogeneous architecture electronic control system for atomic quantum computing control. The control method includes: determining the computing task of the atomic quantum bit in response to a user instruction; generating a configuration instruction set, a scheduling instruction, and a control instruction according to the computing task; configuring the heterogeneous architecture electronic control system according to the configuration instruction set; calling a processor that performs the computing task according to the scheduling instruction; generating a signal generation instruction for the computing task according to the control instruction, so that the processor completes the computing task.

[0013] According to some embodiments of the present application, the processor includes a central processing unit, a graphics processing unit and a field programmable gate array; the above-mentioned step of calling the processor to execute the computing task according to the scheduling instruction may include: calling at least one of the central processing unit, the graphics processing unit and the field programmable gate array according to the scheduling instruction.

[0014] According to some embodiments of the present application, the above-mentioned step of generating a signal generation instruction of a computing task according to a control instruction so that the processor completes the computing task includes: determining the signal generation instruction of the computing task according to the control instruction; and executing the feedback control instruction determination step at least once. The above-mentioned feedback control instruction determination step includes: performing atomic cooling and collecting a first atomic fluorescence image according to the signal generation instruction; determining the existence state data of the atomic quantum bit according to the first atomic fluorescence image; determining and executing the quantum gate manipulation of the atomic quantum bit according to the signal generation instruction; collecting a second atomic fluorescence image after executing the quantum gate manipulation; determining the quantum state data of the atomic quantum bit according to the second atomic fluorescence image; and determining the feedback control instruction according to the existence state data of the atomic quantum bit so that the processor completes the computing task.

[0015] According to some embodiments of the present application, the step of determining the feedback control instruction based on the existence status data of the atomic quantum bit may include: generating the feedback control instruction based on a preset atomic sorting strategy and the existence status data of the atomic quantum bit.

[0016] According to some embodiments of the present application, after the above-mentioned feedback control instruction determination step is executed at least once, the control method further includes: generating an error correction control instruction based on the existence status data of the atomic quantum bit and the quantum state data of the atomic quantum bit.

[0017] According to an embodiment of one aspect of the present application, the present application also provides a non-volatile computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the control method of the heterogeneous architecture electronic control system controlled by atomic quantum computing as described above.

[0018] According to an embodiment of one aspect of the present application, the present application also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, which, when the one or more programs are executed by one or more processors, enables the one or more processors to implement the control method of the heterogeneous architecture electronic control system controlled by atomic quantum computing as described above.

[0019] According to an embodiment of one aspect of the present application, the present application also provides a computer program product, including: a computer program stored on a computer-readable storage medium; the computer program includes program instructions, and when the program instructions are executed by a computer, the computer executes the control method of the heterogeneous architecture electronic control system controlled by atomic quantum computing as described above.

[0020] Beneficial Effects This application can build a multi-level heterogeneous architecture electronic control system by integrating CPU, GPU, and FPGA. This application effectively integrates multiple computing resources through heterogeneous architecture to achieve accurate scheduling during computing tasks. This application can ensure efficient and flexible execution of computing tasks through collaborative work between modules. This application can implement a dynamic resource scheduling mechanism by configuring instruction sets, control instructions, and feedback control instructions, thereby achieving optimized allocation of hardware resources for different tasks, supporting multi-task parallel processing and providing efficient operation support, and significantly improving system flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A schematic diagram showing a flow chart of a control method 1000 according to an embodiment of the present application is shown; Figure 2 A schematic diagram showing a process of step S150 of an embodiment of the present application is shown; Figure 3 A schematic diagram showing a process of step S152 of an embodiment of the present application; Figure 4 Another flowchart of a control method 1000 according to an embodiment of the present application is shown; Figure 5 A schematic diagram showing the structure of a heterogeneous architecture electronic control system according to an embodiment of the present application; Figure 6 Another structural schematic diagram of a heterogeneous architecture electronic control system according to an embodiment of the present application is shown.

[0023] Reference numerals Heterogeneous architecture electronics control system 200; control core module 210; resource scheduling module 220; signal generation module 230; data processing module 240; quantum error correction module 250. DETAILED DESCRIPTION

[0024] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0025] The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of these specific details, or other modes, components, materials, devices, etc. may be adopted. In these cases, known structures, methods, devices, implementations, materials or operations will not be shown or described in detail.

[0026] In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0027] The terms "first", "second" and the like in the specification and claims of this application and the above drawings are used to distinguish different objects rather than to describe a specific order.

[0028] The following is a clear and complete description of the technical solution of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0029] See also Figure 5 The present application provides a heterogeneous architecture electronic control system 200 for atomic quantum computing control. The heterogeneous architecture electronic control system 200 includes a control core module 210, a resource scheduling module 220 and a signal generation module 230.

[0030] The processor of the heterogeneous architecture electronic control system 200 may include a central processing unit (CPU), a graphics processing unit (GPU), and a field-programmable gate array (FPGA). The processor of the heterogeneous architecture electronic control system 200 may also include an atomic quantum bit server, an application specific integrated circuit (ASIC), and a classical quantum hybrid computing server.

[0031] See also Figure 6The heterogeneous architecture electronic control system 200 also includes a data processing module 240 , a communication interface module (not shown in the figure) and a quantum error correction module 250 .

[0032] Combine the following Figure 5 and Figure 6 The present invention describes a control method for an atomic quantum bit heterogeneous architecture electronic control system based on a heterogeneous architecture.

[0033] See also Figure 1 , the control method 1000 may include steps S110 to S150.

[0034] In step S110 , the control core module 210 determines the computing task of the atomic quantum bit in response to the user instruction.

[0035] According to the example embodiment, the atomic qubit includes two types: neutral atomic bits and ion atomic bits. The atomic qubit is a qubit form that uses the energy level of atoms to encode and process information. The user instruction can be an atomic qubit calculation instruction issued by the user. The calculation task of the atomic qubit can be a calculation task of the atomic qubit parsed according to the user instruction.

[0036] For example, in step S110, the control core module 210 determines the computing task of the atomic quantum bit in response to the user instruction. The control core module 210 can run on the CPU. The control core module 210 can receive the user instruction through a graphical human-computer interaction interface, a quantum circuit description code, a quantum gate parameter description, etc.

[0037] The computing task of the atomic quantum bit may include task parameters. The task parameters may include task type, quantum gate sequence, quantum gate type, execution timing accuracy and number of repetitions. The execution timing accuracy may be in nanoseconds.

[0038] For example, after receiving the user instructions, the control core module 210 can parse the user instructions into task parameters through quantum compilation, physical parameter conversion, etc., so as to determine the computing task of the atomic quantum bit according to the task parameters.

[0039] In step S120 , the control core module 210 generates a configuration instruction set, a scheduling instruction, and a control instruction according to the computing task.

[0040] According to an example embodiment, the configuration instruction set may be a data set for configuring a heterogeneous architecture electronic control system generated according to a computing task, and the configuration instruction set includes configuration parameters.

[0041] For example, configuration parameters may include timing parameters, sampling rate, signal time sequence, and communication rate configuration, etc.

[0042] The scheduling instruction may be an instruction for scheduling a processor, and the scheduling instruction may include a scheduling parameter.

[0043] For example, the scheduling parameters may include task types, etc. For example, the control core module 210 may determine the processor that performs the computing task based on the task parameters of the computing task. FPGA performs high-speed, low-latency, and high-time precision tasks (e.g., quantum computing timing control, quantum gate manipulation process control, fluorescence acquisition exposure duration control, atomic fluorescence acquisition and real-time processing, etc.). CPU performs complex algorithm tasks (e.g., quantum compilation, data post-processing, quantum classical hybrid algorithm collaboration, etc.). GPU performs specific tasks such as AI reasoning (e.g., artificial intelligence algorithm processing of fluorescence images, real-time reasoning of spatial light modulator phase diagrams, etc.).

[0044] The control instruction may be instruction information generated according to the computing task for controlling the processor to execute the computing task, and the control instruction may include control parameters.

[0045] For example, the control parameters may include parameters such as the time requirement for executing the computing task, the atomic ordering strategy, and the atomic manipulation strategy.

[0046] As an embodiment, in step S120, the control core module 210 may generate a configuration instruction set, a scheduling instruction, and a control instruction according to a computing task by quantum compilation, physical parameter conversion, and the like.

[0047] In step S130 , the control core module 210 configures the heterogeneous architecture electronic control system 200 according to the configuration instruction set.

[0048] According to an example embodiment, the control core module 210 may send a configuration instruction set to the communication interface module. The control core module 210 may send a rate configuration in the configuration instruction set to the communication interface module so that the communication interface module is configured according to the rate configuration.

[0049] According to an example embodiment, the control core module 210 may be in communication connection with the resource scheduling module 220 and the signal generating module 230 through the communication interface module, and send the configuration instruction set to the resource scheduling module 220 and the signal generating module 230 .

[0050] The resource scheduling module 220 may run on an FPGA and / or a CPU. The signal generation module 230 may run on an FPGA. The communication interface module may run on an FPGA, a CPU, and a GPU.

[0051] For example, in step S130, the control core module 210 may send the timing parameters in the configuration instruction set to the resource scheduling module 220, so that the resource scheduling module 220 is configured according to the timing parameters. The control core module 210 may send the sampling rate or signal time sequence in the configuration instruction set to the signal generation module 230, so that the signal generation module 230 is configured according to the sampling rate or signal time sequence.

[0052] In step S140 , the resource scheduling module 220 calls the processor that executes the computing task according to the scheduling instruction.

[0053] According to an example embodiment, the control core module 210 may send a scheduling instruction to the resource scheduling module 220 through the communication interface module. The resource scheduling module 220 may call a processor that executes a computing task according to the scheduling instruction.

[0054] Optionally, step S140 may specifically include: the resource scheduling module 220 calls at least one of a central processing unit, a graphics processing unit, and a field programmable gate array according to the scheduling instruction.

[0055] For example, after receiving the scheduling instruction, the resource scheduling module 220 can trigger the CPU, GPU and FPGA according to the scheduling instruction, so that one or a combination of the CPU, GPU and FPGA executes the above task allocation content according to the specific time requirements in the scheduling instruction.

[0056] In step S150 , the signal generation module 230 generates a signal generation instruction for the computing task according to the control instruction, so that the processor completes the computing task.

[0057] According to an example embodiment, the signal generation instruction may be an instruction for generating a timing signal. The signal generation module 230 may generate the signal generation instruction according to the quantum gate manipulation requirements (eg, pulse duration, amplitude, frequency, phase, etc.) in the control instruction.

[0058] For example, the data processing module 240 performs atomic cooling and collects a first atomic fluorescence image according to the signal generation instruction. The data processing module 240 determines the existence state data of the atomic quantum bit according to the first atomic fluorescence image. The signal generation module 230 determines and performs quantum gate manipulation of the atomic quantum bit according to the signal generation instruction. After performing the quantum gate manipulation, the data processing module 240 collects a second atomic fluorescence image. The data processing module 240 determines the quantum state data of the atomic quantum bit according to the second atomic fluorescence image. The control core module 210 also determines the feedback control instruction according to the existence state data of the atomic quantum bit so that the processor completes the computing task.

[0059] Through the above-mentioned embodiments, the present application can determine the computing task of the atomic quantum bit by responding to the user instruction. The present application can generate a configuration instruction set, a scheduling instruction and a control instruction through the computing task. The present application can configure a heterogeneous architecture electronic control system according to the configuration instruction set. The present application can call the processor that performs the computing task through the scheduling instruction. The present application can generate a signal generation instruction for the computing task through the control instruction so that the processor completes the computing task.

[0060] This application can form a heterogeneous architecture by integrating CPU, GPU, and FPGA, and construct a multi-level heterogeneous architecture electronic control system. This application effectively integrates multiple computing resources through heterogeneous architecture to achieve accurate scheduling during computing tasks. This application can ensure efficient and flexible execution of computing tasks through collaborative work between modules. This application can implement a dynamic resource scheduling mechanism by configuring instruction sets, control instructions, and feedback control instructions, thereby achieving optimized allocation of hardware resources for different tasks, supporting multi-task parallel processing and providing efficient operation support, and significantly improving system flexibility.

[0061] Alternatively, see Figure 2 , step S150 may include step S151 and step S152.

[0062] In step S151 , the signal generation module 230 generates a signal generation instruction for the computing task according to the control instruction.

[0063] According to an example embodiment, the signal generation instruction may be an instruction for generating a timing signal. The signal generation module 230 may generate the signal generation instruction according to the quantum gate manipulation requirements (eg, pulse duration, amplitude, frequency, phase, etc.) in the control instruction.

[0064] After step S151 , the signal generating module 230 , the data processing module 240 and the control core module 210 perform step S152 at least once.

[0065] Step S152 is a step for determining the feedback control instruction. Figure 3 , step S152 may include steps S1521-S1526.

[0066] In step S1521 , the data processing module 240 performs atomic cooling and acquires a first atomic fluorescence image according to the signal generation instruction.

[0067] According to an example embodiment, the core control module may also be in communication with the data processing module 240 to send the configuration instruction set to the data processing module 240 .

[0068] The data processing module 240 may run on the FPGA, or may run in coordination with multiple resources such as the FPGA, CPU, and GPU.

[0069] The configuration parameters may also include a processing algorithm. The control core module 210 may send the processing algorithm configuration in the configuration instruction set to the data processing module 240, so that the data processing module 240 is configured according to the processing algorithm configuration.

[0070] According to an example embodiment, atomic cooling can be a process of reducing the thermal motion of atoms (i.e., reducing their kinetic energy) to achieve temperature reduction. The data processing module 240 can perform atomic cooling by Doppler cooling, Sisyphus cooling, optical friction (Optical Molasses), Zeeman Slower, and Magneto-Optical Trap (MOT). The data processing module 240 can calculate the changes in peripheral parameters such as laser, magnetic field, electric field, etc. during the cooling process over time according to the configuration of the control core module 210, and perform atomic cooling.

[0071] According to an example embodiment, the atomic fluorescence image may be a distribution of photon intensity of stimulated emission of atoms in a scientific camera. The data processing module 240 may read the atomic fluorescence image through the scientific camera.

[0072] The first atomic fluorescence image may be an atomic fluorescence image before quantum gate manipulation is performed on the atomic quantum bit. The data processing module 240 may read the first atomic fluorescence image through a scientific camera.

[0073] In step S1522 , the data processing module 240 determines the existence state data of the atomic quantum bit according to the first atomic fluorescence pattern.

[0074] According to an example embodiment, the existence state data of the atomic qubit may be data of the existence state of the atomic qubit. The existence state of the atomic qubit may include the existence of the atomic qubit and the absence of the atomic qubit. The data processing module 240 may perform image recognition on the first atomic fluorescence image by a linear threshold method to obtain the existence state data of the atomic qubit. Alternatively, the data processing module 240 may also perform image recognition on the first atomic fluorescence image by a convolutional neural network (CNN) classification method to obtain the existence state data of the atomic qubit.

[0075] In step S1523, the signal generation module 230 determines and executes quantum gate manipulation of the atomic quantum bit according to the signal generation instruction.

[0076] According to an example embodiment, quantum gate manipulation can be to operate on atomic quantum bits to achieve specific quantum state conversion. The signal generation module 230 can accurately generate timing signals according to the signal generation instruction. The generated timing signals may include TTL digital signals (Transistor-Transistor Logic Signal, transistor-transistor logic level signals), high-precision analog modulation waveforms, and radio frequency signals. The timing signals generated by the signal generation module 230 can be used to trigger the execution of hardware-level quantum gate manipulation (such as acousto-optic deflector (Acousto-Optic Deflector, AOD) / acousto-optic modulator (Acousto-Optic Modulator, AOM) to manipulate laser pulse generation) to complete the quantum gate manipulation of atomic quantum bits. The signal generation module 230 can perform quantum gate manipulation.

[0077] In step S1524 , after performing the quantum gate manipulation, the data processing module 240 collects a second atomic fluorescence image.

[0078] According to an example embodiment, the second atomic fluorescence image may be an atomic fluorescence image after quantum gate manipulation is performed on the atomic quantum bit. The data processing module 240 may read the second atomic fluorescence image through a scientific camera.

[0079] In step S1525, the data processing module 240 determines the quantum state data of the atomic quantum bit according to the second atomic fluorescence image.

[0080] According to example embodiments, the quantum state data of the atomic qubit may be data describing the quantum state of the atomic qubit. The quantum state data of the atomic qubit may include a 0 state and a 1 state. The quantum state data of the atomic qubit may be a binary array.

[0081] The data processing module 240 can perform image recognition on the second atomic fluorescence image by a linear threshold method to obtain the quantum state data of the atomic quantum bit. Alternatively, the data processing module 240 can also perform image recognition on the second atomic fluorescence image by a CNN classification method to obtain the quantum state data of the atomic quantum bit.

[0082] In step S1526, the control core module 210 also determines feedback control instructions based on the existence status data of the atomic quantum bit so that the processor completes the computing task.

[0083] According to an example embodiment, the feedback control instruction may be instruction information generated according to the existence state data of the atomic quantum bit to control the processor to perform the computing task.

[0084] For example, the control core module 210 can generate feedback control instructions according to the existence state data of the atomic quantum bit through quantum compilation, physical parameter conversion, etc.

[0085] The quantum state data of atomic quantum bits can be post-processed through the linear threshold method or the convolutional neural network (CNN) model to obtain the calculation results of the computing task.

[0086] Optionally, step S1526 may be specifically as follows: the control core module 210 further generates a feedback control instruction according to a preset atomic sorting strategy and the existence status data of the atomic quantum bit.

[0087] According to an example embodiment, the preset atomic sorting strategy may be a model for sorting and operating atomic qubits that is preset and configured in the control core module 210. For example, the preset atomic sorting strategy may be an algorithm such as the Hungarian algorithm, the Tetris algorithm, and the artificial intelligence algorithm.

[0088] For example, the core control module 210 can use the atomic quantum bit existence state data as the input of the preset atomic sorting strategy, and the preset atomic sorting strategy performs algorithmic processing on the atomic quantum bit existence state data. The preset atomic sorting strategy outputs feedback control instructions, so that the processor completes the computing task according to the feedback control instructions.

[0089] Alternatively, see Figure 4 , the control method 1000 may further include step S160.

[0090] In step S160, the quantum error correction module 250 generates an error correction control instruction according to the existence status data of the atomic quantum bit and the quantum state data of the atomic quantum bit.

[0091] According to an example embodiment, the control core module 210 configures the quantum error correction module 250 according to a configuration instruction set.

[0092] For example, the configuration parameters may also include an error correction strategy. The control core module 210 may send the error correction strategy to the quantum error correction module 250 through the communication interface module, so that the quantum error correction module 250 is configured according to the error correction strategy.

[0093] Exemplarily, the quantum error correction module 250 may run on an FPGA.

[0094] The data processing module 240 can also be connected to the quantum error correction module 250 through the communication interface module. The data processing module 240 sends the existence state data of the atomic quantum bit and the quantum state data of the atomic quantum bit to the quantum error correction module 250 after error correction configuration. The quantum error correction module 250 generates an error correction control instruction according to the existence state data of the atomic quantum bit and the quantum state data of the atomic quantum bit.

[0095] According to an example embodiment, the quantum error correction module 250 may generate an error correction control instruction according to the existence state data of the atomic quantum bit and the quantum state data of the atomic quantum bit through quantum error correction (QEC).

[0096] For example, the quantum error correction module 250 can analyze the existence state data of the atomic quantum bit and the quantum state data of the atomic quantum bit output by the data processing module 240 in real time according to the error correction strategy (e.g., error correction requirements and error correction algorithms) of the control core module 210. The quantum error correction module 250 can use a real-time error correction algorithm (such as a surface code algorithm and a stabilizer code algorithm) to determine the error of the existence state data of the atomic quantum bit, thereby identifying and correcting the error of the existence state data of the atomic quantum bit. The quantum error correction module 250 can use a real-time error correction algorithm to determine the error of the quantum state data of the atomic quantum bit, thereby identifying and correcting the error of the quantum state data of the atomic quantum bit.

[0097] Exemplarily, the existence state data error of the atomic quantum bit may be quantum state flip, atomic loss, phase error, etc. The quantum state data error of the atomic quantum bit may be quantum state flip, atomic loss, phase error, etc.

[0098] Afterwards, the quantum error correction module 250 can generate an error correction control instruction according to the existence state data error of the atomic quantum bit and the quantum state data error of the atomic quantum bit, and the quantum error correction module 250 can send the error correction control instruction to the resource scheduling module 220 and the signal generation module 230 through the communication interface module. The resource scheduling module 220, the signal generation module 230 and the quantum error correction module 250 can systematically execute the error correction control instruction and execute the error correction algorithm, so that the errors in the computing task can be corrected in real time.

[0099] As an embodiment, the computing task of the atomic quantum bit can be the computing task of the neutral atomic quantum bit or the computing task of the ion atomic quantum bit. The processor that performs the computing task is an FPGA. The control core module 210 can formulate feedback control instructions (feedback strategy) according to the state data (real-time measurement data) of the atomic quantum bit. The control core module 210 can also dynamically generate FPGA configuration parameters to manipulate the quantum bit in real time. The signal generation module 230 can generate precise timing signals based on the FPGA configuration parameters to perform quantum state reading and manipulation. The data processing module 240 can process quantum state measurement data in real time, and the quantum error correction module 250 performs instant error correction to ensure the stability and accuracy of the computing task.

[0100] As another embodiment, the computing task of the atomic quantum bit can also be an intermediate circuit measurement feedback experiment: the control core module 210 generates a configuration instruction set based on the computing task (measurement feedback requirement). The resource scheduling module 220 quickly allocates FPGA resources to execute the configuration instruction set. The data processing module 240 can process the intermediate measurement data (i.e., the state data of the atomic quantum bit) in the computing task in real time. The quantum error correction module 250 can quickly identify and correct errors to ensure accurate synchronization between the intermediate circuit measurement and subsequent operations.

[0101] As another embodiment, the computing task of the atomic quantum bit can also be a digital quantum simulation task (such as quantum chemical simulation). The control core module 210 can parse the computing task definition parameters and generate the timing and waveform modulation parameters of the FPGA according to the specific quantum simulation task requirements, thereby controlling the quantum bit execution required quantum gate sequence in real time. The signal generation module 230 accurately implements the quantum manipulation signal, the data processing module 240 analyzes the output state information, and the quantum error correction module 250 performs real-time error correction to ensure simulation accuracy and improve experimental efficiency.

[0102] Through the above-mentioned embodiments, the present application generates error correction control instructions through the state data of atomic quantum bits, thereby improving the computational accuracy and efficiency of atomic quantum bit computing tasks.

[0103] Optionally, the communication interface module can support peripheral interfaces required for atomic quantum bit experiments, such as arbitrary waveform generator (AWG), CXP high-speed image transmission protocol (CoaXPress), digital input / output (Digital Input / Output, digital IO), analog input / output (Analog Input / Output, analog IO), and can support the expansion of interface types and quantities.

[0104] This application can significantly improve the scalability of heterogeneous electronic control systems through heterogeneous architectures, support the manipulation of large-scale quantum bits, and meet the needs of the gradual expansion of quantum heterogeneous electronic control systems in the future.

[0105] According to an embodiment of one aspect of the present application, the present application also provides a non-volatile computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the control method of the heterogeneous architecture electronic control system controlled by atomic quantum computing as described above.

[0106] According to an embodiment of one aspect of the present application, the present application also provides an electronic device, comprising: one or more processors; a storage device for storing one or more programs, which, when the one or more programs are executed by one or more processors, enables the one or more processors to implement the control method of the heterogeneous architecture electronic control system controlled by atomic quantum computing as described above.

[0107] According to an embodiment of one aspect of the present application, the present application also provides a computer program product, including: a computer program stored on a computer-readable storage medium; the computer program includes program instructions, and when the program instructions are executed by a computer, the computer executes the control method of the heterogeneous architecture electronic control system controlled by atomic quantum computing as described above.

[0108] Finally, it should be noted that the above is only a preferred embodiment of the present application and is not intended to limit the present application. Although the present application is described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions of the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A heterogeneous electronic control system for atomic quantum computing control, characterized in that: The heterogeneous architecture electronics control system includes a control core module, a resource scheduling module and a signal generation module; The control core module determines the computing task of the atomic quantum bit in response to the user instruction, and the control core module determines the configuration instruction set, the scheduling instruction and the control instruction according to the computing task, and the control core module configures the resource scheduling module and the signal generation module according to the configuration instruction set; The resource scheduling module calls the processor of the computing task according to the scheduling instruction; The signal generation module generates a signal generation instruction for the computing task according to the control instruction, so that the processor completes the computing task.

2. The heterogeneous architecture electronic control system according to claim 1, characterized in that: The processor includes a central processing unit, a graphics processing unit and a field programmable gate array; The resource scheduling module also calls at least one of the central processing unit, the graphics processing unit and the field programmable gate array according to the scheduling instruction.

3. The heterogeneous architecture electronic control system according to claim 1, characterized in that: The heterogeneous architecture electronics control system further includes a data processing module; The control core module configures the data processing module according to the configuration instruction set; The signal generation module determines the signal generation instruction of the computing task according to the control instruction; The signal generation module, the data processing module and the control core module perform the feedback control instruction determination step at least once, including: The data processing module generates instructions according to the signal, performs atomic cooling and collects a first atomic fluorescence image; The data processing module determines the existence state data of the atomic quantum bit according to the first atomic fluorescence pattern; The signal generation module determines and executes the quantum gate manipulation of the atomic quantum bit according to the signal generation instruction; After executing the quantum gate manipulation, the data processing module collects a second atomic fluorescence image; The data processing module determines the quantum state data of the atomic quantum bit according to the second atomic fluorescence image; The control core module also determines feedback control instructions based on the existence status data of the atomic quantum bit so that the processor completes the computing task.

4. The heterogeneous architecture electronic control system according to claim 3, characterized in that: The control core module also generates the feedback control instruction according to a preset atomic sorting strategy and the existence status data of the atomic quantum bits.

5. The heterogeneous architecture electronic control system according to claim 3, characterized in that: The heterogeneous architecture electronics control system further includes a quantum error correction module; The control core module configures the quantum error correction module according to the configuration instruction set; The configured quantum error correction module generates an error correction control instruction according to the existence state data of the atomic quantum bit and the quantum state data of the atomic quantum bit.

6. A control method for a heterogeneous electronic control system controlled by atomic quantum computing, characterized in that: The control method is executed by the heterogeneous architecture electronic control system according to any one of claims 1 to 5, and the control method includes: In response to a user instruction, determining a computing task for the atomic quantum bit; According to the computing task, generating a configuration instruction set, a scheduling instruction and a control instruction; According to the configuration instruction set, configuring the heterogeneous architecture electronic control system; Invoke a processor for executing the computing task according to the scheduling instruction; According to the control instruction, a signal generation instruction for the computing task is generated to enable the processor to complete the computing task.

7. The control method according to claim 6, characterized in that: The processor includes a central processing unit, a graphics processing unit and a field programmable gate array; The step of calling the processor that executes the computing task according to the scheduling instruction includes: At least one of the central processing unit, the graphics processing unit and the field programmable gate array is called according to the scheduling instruction.

8. The control method according to claim 6, characterized in that: The step of generating a signal generation instruction for the computing task according to the control instruction so that the processor completes the computing task includes: Determining the signal generation instruction of the computing task according to the control instruction; The step of determining a feedback control instruction is performed at least once, wherein the step of determining a feedback control instruction comprises: According to the signal generation instruction, performing atomic cooling and acquiring a first atomic fluorescence image; Determining the existence state data of the atomic quantum bit according to the first atomic fluorescence pattern; Determine and execute quantum gate manipulation of the atomic quantum bit according to the signal generation instruction; After performing the quantum gate manipulation, collecting a second atomic fluorescence image; Determining quantum state data of the atomic quantum bit according to the second atomic fluorescence image; Based on the existence status data of the atomic quantum bit, a feedback control instruction is determined to enable the processor to complete the computing task.

9. The control method according to claim 6, characterized in that: The step of determining the feedback control instruction according to the existence state data of the atomic quantum bit comprises: The feedback control instruction is generated according to a preset atomic sorting strategy and the existence status data of the atomic quantum bit.

10. The control method according to claim 8, characterized in that: After the step of determining the feedback control instruction is performed at least once, the control method further includes: An error correction control instruction is generated according to the existence status data of the atomic quantum bit and the quantum state data of the atomic quantum bit.

Images