Chip system, parameter processing method and electronic equipment

Abstract

The invention provides a chip system, a parameter processing method and electronic equipment, relates to the technical field of graphic rendering, and is used for improving the efficiency of a central processing unit. The chip system comprises a memory and a graphic processing circuit, the graphic processing circuit comprises a graphic processor and a command processor, the command processor is used for reading and analyzing a first instruction from the memory to obtain first parameter packet information, the first instruction is an instruction corresponding to a first rendering task, and the first parameter packet information is a second parameter packet information; the first parameter packet information comprises storage addresses of a plurality of first parameter packets corresponding to execution of the first rendering task in a memory, the types of a plurality of parameters included in each first parameter packet are the same, and the types of the plurality of parameters included in any two first parameter packets are different; the command processor is also used for reading a plurality of first parameter packets from the memory according to the first parameter packet information; and the command processor is also used for compiling the plurality of first parameter packets according to the descriptor template to obtain a first target descriptor which can be identified by the graphics processor.

Description

Technical Field

[0001] The present application relates to the field of graphics rendering technology, and in particular to a chip system, a parameter processing method and an electronic device. Background Art

[0002] In the field of graphics rendering, the central processing unit (CPU) and the graphics processing unit (GPU) work together to complete the graphics rendering work. Specifically, on the CPU side: the application (app) issues rendering requirements, the engine executes the drawing task according to the rendering requirements to generate multiple task parameters, and calls the application programming interface (API) to issue multiple task parameters, the compiler completes the shader program compilation according to the rendering requirements to generate multiple shading parameters, the business layer logic of the driver program stores multiple task parameters and multiple shading parameters, and compiles the multiple task parameters and multiple shading parameters into GPU-defined descriptors and sends them to the GPU side. However, the driver program is executed in a single thread (that is, the driver program runs on one CPU core), which causes the CPU load to be too large, reducing the efficiency of the CPU. Therefore, there is an urgent need for a method to improve the efficiency of the CPU.

[0003] In the prior art, the driver is usually designed to be executed in multiple threads to improve the efficiency of the CPU. Figure 1 As shown, the chip system includes a CPU and a GPU, wherein the CPU includes multiple cores, multiple sets of virtual command caches, serialized threads and processing components, and the GPU includes a cache. Specifically, a multi-threaded design is implemented for the driver program, so that the driver program is executed in parallel to generate multiple sets of virtual commands on multiple cores of the CPU, and the multiple sets of virtual command caches are used to store the multiple sets of virtual commands. The serialized threads sort the multiple sets of virtual commands according to the inheritance order of the parameters carried by the multiple sets of virtual commands, and the processing component compiles the parameters carried by the sorted multiple sets of virtual commands into descriptors defined by the GPU and writes them into the cache of the GPU.

[0004] However, implementing a multi-threaded design for the driver program has high design complexity, high maintenance costs, and difficulty in managing multiple sets of virtual commands; in addition, it is necessary to consume hardware resources in the CPU to compile parameters, which reduces the efficiency of the CPU. Summary of the invention

[0005] The present application provides a chip system, a parameter processing method and an electronic device for reducing the load of a central processing unit and improving the efficiency of the central processing unit.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, a chip system is provided, the chip system includes a memory and a graphics processing circuit, the graphics processing circuit includes a graphics processor and a command processor, the memory is used to store instructions and data, and the graphics processor is used to perform a rendering task according to a target descriptor. The command processor is used to read and parse a first instruction from the memory to obtain first parameter package information, the first instruction is an instruction corresponding to a first rendering task, the first parameter package information includes the storage addresses of multiple first parameter packages corresponding to the first rendering task in the memory, each first parameter package includes multiple parameters of the same type, and any two first parameter packages include multiple parameters of different types; the command processor is also used to read multiple first parameter packages from the memory according to the first parameter package information; the command processor is also used to compile multiple first parameter packages according to a descriptor template to obtain a first target descriptor that can be recognized by the graphics processor.

[0008] In the technical solution provided by the present application, a command processor in a graphics processing circuit is used to compile multiple first parameter packages corresponding to a first rendering task to obtain a first target descriptor that can be recognized by the graphics processor, so that the graphics processor can execute the first rendering task, that is, the compilation of multiple first parameter packages is completed by the command processor in the graphics processing circuit, and the command processor completes the compilation task originally performed by the central processing unit. Compared with the prior art in which parameter compilation is completed by the central processing unit, the load of the central processing unit is reduced and the efficiency of the central processing unit is improved; on the other hand, the multiple first parameters included in the first parameter package are of the same type, and are compiled in parameter packages, which improves the efficiency of compilation.

[0009] In a possible implementation of the first aspect, the command processor includes a scheduling unit and a processing unit, the scheduling unit is used to read and parse the first instruction from the memory to obtain the first parameter package information; the scheduling unit is also used to read multiple first parameter packages from the memory according to the first parameter package information; the processing unit is used to compile the multiple first parameter packages according to the descriptor template to obtain the first target descriptor. In the above implementation, the scheduling unit is used to read the multiple first parameter packages, and the processing unit is used to compile the multiple first parameter packages to obtain the first target descriptor, so that the graphics processor that subsequently executes the first rendering task can recognize the first target descriptor and execute the first rendering task in sequence, thereby ensuring the normal execution of the first rendering task.

[0010] In a possible implementation of the first aspect, the first target descriptor includes a first sub-target descriptor and a second sub-target descriptor, and the processing unit includes a plurality of operator units and a plurality of micro-processing units, each of the operator units is used to compile a first parameter package that meets a first characteristic among a plurality of first parameter packages according to a descriptor template to obtain a first sub-target descriptor, the first characteristic being that the number of changes of a mapping rule in the first parameter package is zero, or the number of times participating in a logical judgment is less than or equal to a first threshold, and the mapping rule is used to characterize a mapping relationship between the first parameter package and the descriptor; each micro-processing unit is used to compile a first parameter package that meets a second characteristic among a plurality of first parameter packages according to the descriptor template to obtain a second sub-target descriptor, the second characteristic being that the number of changes of the mapping rule of the first parameter package is greater than zero, and the number of times participating in a logical judgment is greater than the first threshold. In the above possible implementation, a plurality of operator units are used to compile a first parameter package that meets the first characteristic among a plurality of first parameter packages in parallel, a plurality of micro-processing units are used to compile a first parameter package that meets the second characteristic among a plurality of first parameter packages in parallel, and different units are used to compile first parameter packages with different characteristics, thereby improving the speed of compilation and the efficiency of compilation.

[0011] In a possible implementation of the first aspect, the command processor further includes an on-chip memory, and the on-chip memory is used to store the target descriptor and the descriptor template. For example, the target descriptor may include a first target descriptor. In the above possible implementation, each unit in the command processor can directly access the on-chip memory, and the rate at which each unit accesses the on-chip memory is higher than the efficiency of each unit accessing the memory, thereby improving the processing efficiency of each unit and improving the compilation efficiency of the command processor.

[0012] In a possible implementation of the first aspect, the command processor further includes direct memory access, and the direct memory access is used to write the target descriptor into the memory. In the above possible implementation, direct memory access is used to realize bidirectional transmission between the on-chip memory and the memory, thereby improving the performance of the command processor.

[0013] In a possible implementation of the first aspect, before reading the first instruction from the memory, direct memory access is also used to read the descriptor template from the memory and write the descriptor template to the on-chip memory. In the above possible implementation, the processing unit can directly read the descriptor template from the on-chip memory to compile multiple first parameter packages, and the rate at which the processing unit reads the descriptor template from the on-chip memory is higher than the rate at which the processing unit reads the descriptor template from the memory, thereby improving the efficiency of the processing unit in reading the descriptor template and further improving the compilation efficiency of the processing unit.

[0014] In a possible implementation manner of the first aspect, before reading the first instruction from the memory, the scheduling unit is further used to receive first indication information, where the first indication information is used to instruct the graphics processor to execute the first rendering task.

[0015] In a possible implementation of the first aspect, the scheduling unit is further used to read and parse the second instruction from the memory to obtain second parameter package information, the second instruction is an instruction corresponding to the second rendering task, the second parameter package information includes storage addresses of multiple second parameter packages in the memory, and the multiple second parameter packages are second parameter packages different from the multiple first parameter packages in the second parameter package corresponding to the second rendering task; the scheduling unit is further used to read multiple second parameter packages from the memory according to the second parameter package information; the processing unit is further used to compile multiple second parameter packages according to the descriptor template to obtain a second target descriptor. In the above possible implementation, the memory only stores multiple second parameter packages different from the first parameter package in the second parameter package corresponding to the second rendering task, thereby reducing the storage pressure of the memory; on the other hand, only multiple second parameter packages different from the first parameter package in the second parameter package corresponding to the second rendering task need to be compiled, thereby improving compilation efficiency and reducing compilation power consumption.

[0016] In a second aspect, a parameter processing method is provided, which is applied to a chip system, wherein the chip system includes a memory and a graphics processing circuit, the graphics processing circuit includes a graphics processor and a command processor, the memory is used to store instructions and data, and the image processor is used to perform a rendering task according to a target descriptor. The method includes: the command processor reads and parses a first instruction from the memory to obtain first parameter package information, the first instruction is an instruction corresponding to a first rendering task, and the first parameter package information includes storage addresses of multiple first parameter packages corresponding to the first rendering task in the memory; the command processor reads multiple first parameter packages from the memory according to the first parameter package information; the command processor compiles multiple first parameter packages according to a descriptor template to obtain a first target descriptor that can be recognized by the graphics processor.

[0017] In a possible implementation of the second aspect, the command processor includes a scheduling unit and a processing unit, the command processor reads and parses the first instruction from the memory to obtain first parameter package information, and reads multiple first parameter packages from the memory according to the first parameter package information, including: the scheduling unit reads and parses the first instruction from the memory to obtain the first parameter package information; the scheduling unit reads multiple first parameter packages from the memory according to the first parameter package information; the command processor compiles multiple first parameter packages according to the descriptor template to obtain a first target descriptor, including: the processing unit compiles multiple first parameter packages according to the descriptor template to obtain the first target descriptor.

[0018] In a possible implementation of the second aspect, the first target descriptor includes a first sub-target descriptor and a second sub-target descriptor, the processing unit includes multiple operator units and multiple micro-processing units, and the processing unit compiles multiple first parameter packages to obtain the first target descriptor, including: each operator unit compiles a first parameter package that meets a first characteristic among the multiple first parameter packages according to a descriptor template to obtain a first sub-target descriptor, the first characteristic being that the number of changes in the mapping rule of the first parameter package is zero, or the number of times participating in logical judgment is less than or equal to a first threshold, and the mapping rule is used to characterize the mapping relationship between the first parameter package and the descriptor; each micro-processing unit compiles a first parameter package that meets a second characteristic among the multiple first parameter packages according to the descriptor template to obtain a second sub-target descriptor, the second characteristic being that the number of changes in the mapping rule of the first parameter package is greater than zero, and the number of times participating in logical judgment is greater than the first threshold.

[0019] In a possible implementation manner of the second aspect, the command processor further includes an on-chip memory, and the method further includes: the on-chip memory stores the target descriptor and the descriptor template.

[0020] In a possible implementation manner of the second aspect, the command processor further includes direct memory access, and the method further includes: directly accessing the memory to write the target descriptor into the memory, for example, the target descriptor may include a first target descriptor.

[0021] In a possible implementation manner of the second aspect, before reading the first instruction from the memory, the method further includes: reading a descriptor template from the memory by direct memory access, and writing the descriptor template to an on-chip memory.

[0022] In a possible implementation manner of the second aspect, before the scheduling unit reads the first instruction from the memory, the method further includes: the scheduling unit receives first indication information, where the first indication information is used to instruct the graphics processor to execute the first rendering task.

[0023] In a possible implementation of the second aspect, the method also includes: the scheduling unit reads and parses the second instruction from the memory to obtain second parameter package information, the second instruction is an instruction corresponding to the second rendering task, the second parameter package information includes storage addresses of multiple second parameter packages in the memory, and the multiple second parameter packages are second parameter packages in the second parameter packages corresponding to the second rendering task that are different from the multiple first parameter packages; the scheduling unit reads the multiple second parameter packages from the memory according to the second parameter package information; the processing unit compiles the multiple second parameter packages according to the descriptor template to obtain the second target descriptor.

[0024] According to a third aspect, an electronic device is provided. The electronic device includes a circuit board and a chip system as provided in the first aspect or any possible implementation of the first aspect, wherein the chip system is arranged on the circuit board.

[0025] In another aspect of the present application, a computer-readable storage medium is provided, which includes computer instructions. When the computer instructions are executed on a chip system, the chip system executes a parameter processing method provided by the above-mentioned second aspect or any possible implementation of the second aspect.

[0026] In another aspect of the present application, a computer program product comprising instructions is provided. When the computer program product is run on a computer device, the computer device executes the parameter processing method provided in the above-mentioned second aspect or any possible implementation of the second aspect.

[0027] It can be understood that the parameter processing method, electronic device, computer-readable storage medium and computer program product provided above all include the corresponding features of the chip system provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the corresponding chip system provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the structure of a chip system;

[0029] Figure 2 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0030] Figure 3 A schematic diagram of the structure of a chip system provided in an embodiment of the present application;

[0031] Figure 4 A schematic diagram of the structure of another chip system provided in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of the structure of a command processor provided in an embodiment of the present application;

[0033] Figure 6 A flow chart of a parameter processing method provided in an embodiment of the present application;

[0034] Figure 7 A flowchart of another parameter processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In this application, "at least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or its similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple. In addition, the embodiments of the present application use words such as "first" and "second" to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0036] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0037] The embodiment of the present application provides a chip system, which includes a memory and a graphics processing circuit, the graphics processing circuit includes a graphics processor and a command processor, the memory is used to store instructions and data, and the graphics processor is used to perform rendering tasks according to target descriptors. The command processor is used to read and parse the first instruction from the memory to obtain first parameter package information, the first instruction is the instruction corresponding to the first rendering task, the first parameter package information includes the storage addresses of multiple first parameter packages corresponding to the first rendering task in the memory, each first parameter package includes multiple parameters of the same type, and any two first parameter packages include multiple parameters of different types; the command processor is also used to read multiple first parameter packages from the memory according to the first parameter package information; the command processor is also used to compile multiple first parameter packages according to the descriptor template to obtain a first target descriptor that can be recognized by the graphics processor. In this process, the command processor in the graphics processing circuit is used to compile multiple first parameter packages corresponding to the first rendering task to obtain a first target descriptor that can be recognized by the graphics processor, that is, the compilation of multiple first parameter packages is completed by the command processor in the graphics processing circuit, and the command processor completes the compilation task originally performed by the central processing unit. Compared with the prior art in which the compilation of parameters is completed by the central processing unit, the load of the central processing unit is reduced and the efficiency of the central processing unit is improved. On the other hand, the multiple first parameters included in the first parameter package are of the same type and are compiled in parameter packages, which improves the efficiency of compilation.

[0038] The chip system provided in the embodiment of the present application is applied to electronic devices, which include terminal devices, which may include but are not limited to personal computers, server computers, routers, switches, mobile devices (such as mobile phones, tablet computers, media players, etc.), wearable devices, vehicle-mounted devices, consumer terminal devices, mobile robots and drones, etc. Figure 2 The specific structure of the electronic device provided in the embodiment of the present application is introduced and explained.

[0039] Figure 2 The electronic device 20 is a schematic diagram of a structure of an electronic device provided in an embodiment of the present application. The electronic device 20 may include: a chip system 21, a bus 22 and a communication interface 23. The chip system 21 and the communication interface 23 are connected via the bus 22.

[0040] The bus 22 may include a path for transmitting information between the above components. In addition to the data bus, the bus 22 may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are labeled as bus 22 in the figure. The bus 22 may be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 22 can be divided into an address bus, a data bus, a control bus, etc.

[0041] The communication interface 23 is used to implement communication between the electronic device 20 and external devices or components.

[0042] Combine the following Figure 3 The specific structure of the chip system 21 provided in the embodiment of the present application is described.

[0043] Figure 3 A schematic diagram of the structure of a chip system 21 provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the chip system 21 includes a memory 210 and a graphics processing circuit 220, and the graphics processing circuit 220 includes a graphics processing unit (GPU) 230 and a command processor 240. The memory 210 and the graphics processing circuit 220 communicate via a bus 22.

[0044] The memory 210 may be a volatile memory pool or a non-volatile memory pool, or may include both volatile and non-volatile memories. The non-volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct rambus RAM (DR RAM). In one possible implementation, memory 210 may include double data rate synchronous dynamic random access memory (DDR). Memory 210 may be used to store instructions and data, for example, memory 210 may be used to store instructions and parameter packets corresponding to rendering tasks pre-executed by GPU 230.

[0045] The GPU 230 may be used to perform rendering tasks according to the target descriptor to complete corresponding graphics processing. Optionally, the GPU 230 may also include a microprocessor, an ASIC, or one or more integrated circuits for performing rendering tasks.

[0046] Optional, such as Figure 4 As shown, the chip system 21 may also include a central processing unit (CPU) 250. The CPU 250, the memory 210, and the graphics processing circuit 220 are connected via a bus 22. The CPU 250 may send instruction information to the graphics processing circuit 220 via the bus 22, and the instruction information is used to instruct the GPU 230 in the graphics processing circuit 220 to perform a corresponding rendering task. The CPU 250 may also send a parameter package and an instruction corresponding to the rendering task to the memory 210 via the bus 22.

[0047] The command processor 240 can be used to read and parse the first instruction from the memory 210 to obtain first parameter package information, where the first instruction is an instruction corresponding to the first rendering task, and the first parameter package information includes the storage addresses of multiple first parameter packages corresponding to the first rendering task in the memory 210, and the types of the multiple parameters included in each first parameter package are the same, and the types of the multiple parameters included in any two first parameter packages are different; the command processor 240 is also used to read multiple first parameter packages from the memory 210 according to the first parameter package information; the command processor 240 is also used to compile the multiple first parameter packages according to the descriptor template to obtain a first target descriptor that can be recognized by the GPU 230.

[0048] The command processor 240 may also be referred to as a state bundle based command processor (SBCP). In practical applications, the multiple first parameter packages stored in the memory 210 by the CPU 250 cannot be directly recognized by the GPU 230, resulting in the GPU 230 being unable to perform the first rendering task. Therefore, it is necessary to compile the multiple first parameter packages stored in the memory 210 into first target descriptors that can be recognized by the GPU 230, so that the GPU 230 can perform the first rendering task according to the first target descriptors.

[0049] In actual applications, the multiple first parameter packages are written into the memory 210 by the CPU 250. Specifically, the CPU 250 executes the drawing task and the shader program compilation, obtains the task parameters and the shader parameters corresponding to the first rendering task, and divides the task parameters and the shader parameters into multiple first parameter packages according to the parameter types of the task parameters and the shader parameters, and the CPU 250 writes the multiple first parameter packages into the memory 210.

[0050] Combine the following Figure 5 The specific structure of the command processor 240 provided in the embodiment of the present application is introduced and explained.

[0051] Figure 5 A schematic diagram of the structure of a command processor 240 provided in an embodiment of the present application, the command processor 240 includes a scheduling unit 241 and a processing unit 242. The scheduling unit 241 can be used to read and parse the first instruction from the memory 210 to obtain the first parameter package information; the scheduling unit 241 is also used to read multiple first parameter packages from the memory 210 according to the first parameter package information; the processing unit 242 can be used to compile multiple first parameter packages according to the descriptor template to obtain the first target descriptor that the GPU 230 can recognize.

[0052] Further, before the scheduling unit 241 reads the first instruction from the memory 210, the scheduling unit 241 is also used to receive first indication information, and the first indication information is used to instruct the GPU 230 to perform the first rendering task. After receiving the first indication information, the scheduling unit 241 reads the first instruction corresponding to the first rendering task from the memory 210.

[0053] The first rendering task may include multiple first parameter packages. Each of the multiple first parameter packages includes multiple parameters, and the types of the multiple parameters included in each first parameter package are the same. The types of parameters included in any two first parameter packages are different, and the parameter types may include: constant parameters, variable parameters, etc. The number of multiple parameters included in any two first parameter packages may be the same or different, and this application does not make specific restrictions on this.

[0054] Exemplarily, the first rendering task includes 10 first parameter packages and their identification information can be respectively represented as SB10 to SB19, the identification information of each first parameter package is used to uniquely identify the first parameter package, the first parameter package SB10 includes 10 parameters and their identification information can be respectively represented as S00 to S09, the first parameter package SB11 includes 10 parameters and their identification information can be respectively represented as S10 to S19, parameters S00 to S09 are constant parameters, and parameters S10 to S19 are variable parameters.

[0055] In actual applications, the GPU 230 may be able to identify more than 50 types of descriptors. Generally, a rendering task may include 50 types of descriptors.

[0056] Further, the first target descriptor includes a first sub-target descriptor and a second sub-target descriptor, and the processing unit 242 may include multiple operator units 243 and multiple micro-processing units 244. Each of the multiple operator units 243 can be used to compile a first parameter package that meets a first characteristic among multiple first parameter packages according to a descriptor template to obtain a first sub-target descriptor, wherein the first characteristic is that the number of changes in the mapping rule of the first parameter package is zero, and the mapping rule is used to characterize the mapping relationship between the first parameter package and the descriptor, or the number of times participating in logical judgment is less than or equal to a first threshold. Each of the multiple micro-processing units 244 can be used to compile a first parameter package that meets a second characteristic among multiple first parameter packages according to a descriptor template to obtain a second sub-target descriptor, wherein the second characteristic is that the number of changes in the mapping rule of the first parameter package is greater than zero, and the number of times participating in logical judgment is greater than the first threshold.

[0057] In practical applications, the first threshold value may be set according to actual needs or the experience of relevant technical personnel. For example, the first threshold value may be 3, and the embodiment of the present application does not make any specific limitation thereto.

[0058] In addition, the specific compilation process of the multiple operator units 243 and the multiple micro-processing units 244 is similar to the existing parameter compilation process, which will not be repeated here.

[0059] The microprocessor unit 244 may include a microcontroller unit (MCU) or a digital signal processor (DSP) or other programmable processors. The present application embodiment does not make specific limitations. For ease of understanding, Figure 5 The microprocessing unit 244 including the MCU is taken as an example for description.

[0060] Furthermore, the command processor 240 may also include an on-chip memory 245 and a direct memory access (DMA) 246. Before the scheduling unit 241 reads the first instruction from the memory 210, the DMA 246 may be used to read the descriptor template from the memory 210 and write the descriptor template into the on-chip memory 245. During the process of the operator unit 243 and the microprocessing unit 244 compiling the first parameter package, the operator unit 243 and the microprocessing unit 244 may both obtain the descriptor template from the on-chip memory 245 through the bus 22, and complete the compilation of the first parameter package according to the descriptor template. The on-chip memory 245 may be used to store the descriptor template and the target descriptor compiled by the processing unit 242. For example, the on-chip memory 245 may be used to store the first target descriptor. The DMA 246 is also used to write the first target descriptor obtained by the processing unit 242 compiling multiple first parameter packages into the memory 210.

[0061] In a possible embodiment, multiple operator units 243 may be used to compile first parameter packages that meet the first characteristic in multiple first parameter packages in parallel. In this embodiment, multiple operator units 243 are used to compile multiple first parameter packages that meet the first characteristic in parallel, thereby improving compilation efficiency and reducing compilation power consumption.

[0062] In a possible embodiment, multiple micro-processing units 244 can be used to compile in parallel the first parameter packages that meet the second characteristic among the multiple first parameter packages. In this embodiment, multiple micro-processing units 244 compile in parallel the multiple first parameter packages that meet the second characteristic, thereby improving compilation efficiency and reducing compilation power consumption.

[0063] In a possible embodiment, the scheduling unit 241 is further used to read and parse the second instruction from the memory to obtain the second parameter package information, the second instruction is the instruction corresponding to the second rendering task, the second parameter package information includes the storage addresses of multiple second parameter packages in the memory 210, and the multiple second parameter packages are second parameter packages different from the multiple first parameter packages in the second parameter packages corresponding to the second rendering task. The scheduling unit 241 is further used to read the second parameter package from the memory 210 according to the second parameter package information; the processing unit 242 is further used to compile the second parameter package according to the descriptor template to obtain the second target descriptor.

[0064] In actual applications, after obtaining the multiple second parameter packages corresponding to the second rendering task, the CPU 250 writes the second parameter package that is different from the multiple first parameter packages in the second parameter package corresponding to the second rendering task into the memory 210 .

[0065] Exemplarily, the first rendering task includes 10 first parameter packages and their identification information can be represented as SB10 to SB19, respectively, and the second rendering task includes 5 second parameter packages and their identification information can be represented as SB20 to SB24, respectively, wherein the second parameter packages SB20 to SB22 in the second rendering task are the same as the first parameter packages SB10 to SB12 included in the first rendering task, and at this time, only the second parameter package SB23 and the second parameter package SB24 are stored in the memory 210. Specifically, the scheduling unit 241 is also used to read and parse the second instruction from the memory to obtain the storage address of the second parameter package SB23 and the second parameter package SB24 in the memory 210; the scheduling unit 241 is also used to read the second parameter package SB23 and the second parameter package SB24 from the memory 210 according to the storage address of the second parameter package SB23 and the second parameter package SB24 in the memory 210, and the processing unit 242 is also used to compile the second parameter package SB23 and the second parameter package SB24 according to the descriptor template to obtain the second target descriptor.

[0066] The process of the processing unit 242 compiling the second parameter package according to the descriptor template is similar to the process of the processing unit 242 compiling the first parameter package, which will not be repeated here.

[0067] In this embodiment, the command processor only needs to compile the second parameter package that is different from the multiple first parameter packages in the second parameter package corresponding to the second rendering task, which improves the compilation efficiency and reduces the power consumption of compilation. On the other hand, the memory only stores multiple second parameter packages that are different from the multiple first parameter packages, which reduces the storage pressure of the memory.

[0068] In the chip system provided by the embodiment of the present application, the command processor receives the first indication information sent by the CPU, the first indication information is used to instruct the GPU to execute the first rendering task, the command processor reads and parses the first instruction from the memory to obtain the first parameter package information, the first parameter package information includes the storage addresses of multiple first parameter packages corresponding to the GPU executing the first rendering task in the memory, the command processor reads multiple first parameter packages from the memory according to the first parameter package information, and compiles multiple first parameter packages according to the descriptor template to obtain the first target descriptor that the GPU can recognize, the command processor writes the first target description into the memory, and the GPU reads the first target descriptor from the memory and executes the first rendering task. In this process, the command processor executes the compilation task originally executed by the central processing unit, which reduces the load of the central processing unit and improves the efficiency of the central processing unit compared with the prior art in which the compilation of parameters is completed by the central processing unit; on the other hand, the multiple first parameters included in the first parameter package are of the same type, and are compiled in parameter packages, which improves the efficiency of compilation.

[0069] Figure 6 A flow chart of a parameter processing method provided in an embodiment of the present application, the parameter processing method is applied to the above Figure 3 and Figure 4 In the chip system 21 shown, the parameter processing method includes the following steps.

[0070] S601, the command processor 240 reads and parses the first instruction from the memory 210 to obtain first parameter package information, where the first instruction is an instruction corresponding to the first rendering task, and the first parameter package information includes storage addresses of multiple first parameter packages corresponding to the first rendering task in the memory 210.

[0071] The command processor 240 may also be referred to as a state bundle based command processor (SBCP). In practical applications, the multiple first parameter packages stored in the memory 210 by the CPU 250 cannot be directly recognized by the GPU 230, resulting in the GPU 230 being unable to perform the first rendering task. Therefore, it is necessary to compile the multiple first parameter packages stored in the memory 210 into first target descriptors that can be recognized by the GPU 230, so that the GPU 230 can perform the first rendering task.

[0072] In actual applications, the multiple first parameter packages are written into the memory 210 by the CPU 250. Specifically, the CPU 250 executes the drawing task and the shader program compilation, obtains the task parameters and the shader parameters corresponding to the first rendering task, and divides the task parameters and the shader parameters into multiple first parameter packages according to the parameter types of the task parameters and the shader parameters, and the CPU 250 writes the multiple first parameter packages into the memory 210.

[0073] Furthermore, the command processor 240 includes a scheduling unit 241. Step S601 specifically includes: the scheduling unit 241 reads and parses the first instruction from the memory 210 to obtain first parameter package information.

[0074] Before step S601, the scheduling unit 241 receives first instruction information, and the first instruction information is used to instruct the GPU 230 to perform the first rendering task. After receiving the first instruction information, the scheduling unit 241 performs step S601. Figure 7 As shown, the method provided in the embodiment of the present application also includes:

[0075] S604: The scheduling unit 241 receives first indication information, where the first indication information is used to instruct the GPU 230 to execute a first rendering task.

[0076] S602: The command processor 240 reads a plurality of first parameter packages from the memory according to the first parameter package information.

[0077] Step S602 specifically includes: the scheduling unit 241 reads a plurality of first parameter packages from the memory 210 according to the first parameter package information.

[0078] The first rendering task may include multiple first parameter packages. Each of the multiple first parameter packages includes multiple parameters, and the types of the multiple parameters included in each first parameter package are the same. The types of parameters included in any two first parameter packages are different, and the parameter types may include: constant parameters, variable parameters, etc. The number of multiple parameters included in any two first parameter packages may be the same or different, and this application does not make specific restrictions on this.

[0079] Exemplarily, the first rendering task includes 10 first parameter packages and their identification information can be respectively represented as SB0 to SB9, the identification information of each first parameter package is used to uniquely identify the first parameter package, the first parameter package SB0 includes 10 parameters and their identification information can be respectively represented as S00 to S09, the first parameter package SB1 includes 10 parameters and their identification information can be respectively represented as S10 to S19, parameters S00 to S09 are constant parameters, and parameters S10 to S19 are variable parameters.

[0080] In actual applications, the GPU 230 may be able to identify more than 50 types of descriptors. Generally, a rendering task may include 50 types of descriptors.

[0081] S603 : The command processor 240 compiles a plurality of first parameter packets according to the descriptor template to obtain a first target descriptor that can be recognized by the GPU 230 .

[0082] Further, the first target descriptor includes a first sub-target descriptor and a second sub-target descriptor, and the processing unit 242 may include multiple operator units 243 and multiple micro-processing units 244. Step S603 specifically includes: each of the multiple operator units 243 compiles a first parameter package that meets a first characteristic among multiple first parameter packages according to a descriptor template to obtain a first sub-target descriptor, and the first characteristic is that the number of changes in the mapping rule of the first parameter package is zero, or the number of times participating in logical judgment is less than or equal to a first threshold. Each of the multiple micro-processing units 244 compiles a first parameter package that meets a second characteristic among multiple first parameter packages according to a descriptor template to obtain a second sub-target descriptor, and the second characteristic is that the number of changes in the mapping rule of the first parameter package is greater than zero, and the number of times participating in logical judgment is greater than the first threshold.

[0083] In a possible embodiment, multiple operator units 243 may be used to compile first parameter packages satisfying the first characteristic in parallel among multiple first parameter packages. In this embodiment, multiple operator units 243 are used to compile multiple first parameter packages satisfying the first characteristic in parallel, thereby improving the compilation speed.

[0084] In a possible embodiment, multiple micro-processing units 244 can be used to compile first parameter packages that meet the second characteristic in parallel among multiple first parameter packages. In this embodiment, multiple micro-processing units 244 compile multiple first parameter packages that meet the second characteristic in parallel, thereby improving the compilation speed.

[0085] In practical applications, the first threshold value may be set according to actual needs or the experience of relevant technical personnel. For example, the first threshold value may be 3, and the embodiment of the present application does not make any specific limitation thereto.

[0086] Furthermore, the command processor 240 may further include an on-chip memory 245. The method provided in the embodiment of the present application further includes S605: the on-chip memory 245 stores the target descriptor and the descriptor template. For example, the on-chip memory 245 may be used to store the first target descriptor and the second target descriptor.

[0087] Furthermore, the command processor 240 may also include a DMA 246 , and the method provided in the embodiment of the present application further includes: the DMA 246 writes the target descriptor into the memory 210 .

[0088] Before step S601, DMA 246 reads the descriptor template from memory 210 and writes the descriptor template into on-chip memory 245, so that in the process of compiling the first parameter package, operator unit 243 and microprocessor unit 244 can obtain the descriptor template from on-chip memory 245 through bus 22, and complete the compilation of the first parameter package according to the descriptor template. Therefore, the method provided in the embodiment of the present application also includes S606.

[0089] S606 : DMA 246 reads the descriptor template from the memory 210 , and writes the descriptor template into the on-chip memory 245 .

[0090] In a possible embodiment, the method provided by the embodiment of the present application also includes: the scheduling unit 241 reads and parses the second instruction from the memory 210 to obtain second parameter package information, the second instruction is an instruction corresponding to the second rendering task, the second parameter package information includes storage addresses of multiple second parameter packages in the memory 210, and the multiple second parameter packages are second parameter packages in the second parameter packages corresponding to the second rendering task that are different from the multiple first parameter packages; the scheduling unit 241 reads multiple second parameter packages from the memory 210 according to the second parameter package information; the processing unit 242 compiles multiple second parameter packages according to the descriptor template to obtain a second target descriptor.

[0091] In actual applications, after obtaining the multiple second parameter packets corresponding to the second rendering task, the CPU 250 writes the second parameter packets that are different from the multiple first parameter packets among the multiple second parameter packets corresponding to the second rendering task into the memory.

[0092] Exemplarily, the first rendering task includes 10 first parameter packages and their identification information can be represented as SB10 to SB19, respectively, and the second rendering task includes 5 second parameter packages and their identification information can be represented as SB20 to SB24, respectively, wherein the second parameter packages SB20 to SB22 in the second rendering task are the same as the first parameter packages SB10 to SB12 included in the first rendering task, and at this time, only the second parameter package SB23 and the second parameter package SB24 are stored in the memory 210. Specifically, the scheduling unit 241 reads and parses the second instruction from the memory to obtain the storage address of the second parameter package SB23 and the second parameter package SB24 in the memory 210; the scheduling unit 241 reads the second parameter package SB23 and the second parameter package SB24 from the memory 210 according to the storage address of the second parameter package SB23 and the second parameter package SB24 in the memory 210, and the processing unit 242 compiles the second parameter package SB23 and the second parameter package SB24 according to the descriptor template to obtain the second target descriptor.

[0093] The process of the processing unit 242 compiling the second parameter package according to the descriptor template is similar to the process of the processing unit 242 compiling the first parameter package, which will not be repeated here.

[0094] In this embodiment, the command processor only needs to compile the second parameter package that is different from the multiple first parameter packages in the second parameter package corresponding to the second rendering task, which improves the compilation efficiency and reduces the power consumption of compilation. On the other hand, the memory only stores multiple second parameter packages that are different from the multiple first parameter packages, which reduces the storage pressure of the memory.

[0095] In the chip system provided by the embodiment of the present application, the command processor receives the first indication information sent by the CPU, the first indication information is used to instruct the GPU to execute the first rendering task, the command processor reads and parses the first instruction from the memory to obtain the first parameter package information, the first parameter package information includes the storage addresses of multiple first parameter packages corresponding to the GPU executing the first rendering task in the memory, the command processor reads multiple first parameter packages from the memory according to the first parameter package information, and compiles multiple first parameter packages according to the descriptor template to obtain the first target descriptor that the GPU can recognize, the command processor writes the first target description into the memory, and the GPU reads the first target descriptor from the memory and executes the first rendering task. In this process, the command processor executes the compilation task originally executed by the central processing unit, which reduces the load of the central processing unit and improves the efficiency of the central processing unit compared with the prior art in which the compilation of parameters is completed by the central processing unit; on the other hand, the multiple first parameters included in the first parameter package are of the same type, and are compiled in parameter packages, which improves the efficiency of compilation.

[0096] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0097] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0098] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for the device to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks or optical disks.

[0099] In another aspect of the present application, an electronic device is provided. The electronic device may include a circuit board and a chip system. The chip system is arranged on the circuit board. The chip system may be the above-mentioned Figure 3 and Figure 4 The chip system shown.

[0100] In another aspect of the present application, a computer-readable storage medium is provided, which includes computer instructions. When the computer instructions are executed on a chip system, the chip system executes relevant steps in the above method embodiments.

[0101] In yet another aspect of the present application, a computer program product comprising instructions is provided. When the computer program product is run on a computer device, the computer device is enabled to execute relevant steps in the above method embodiments.

[0102] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip system, characterized in that: The chip system includes a memory and a graphics processing circuit, wherein the graphics processing circuit includes a graphics processor and a command processor, wherein the memory is used to store instructions and data, and the graphics processor is used to perform rendering tasks according to a target descriptor. The command processor is configured to read and parse a first instruction from the memory to obtain first parameter package information, wherein the first instruction is an instruction corresponding to a first rendering task, and the first parameter package information includes storage addresses of multiple first parameter packages corresponding to the first rendering task in the memory, wherein the types of the multiple parameters included in each first parameter package are the same, and the types of the multiple parameters included in any two first parameter packages are different; The command processor is further configured to read the plurality of first parameter packages from the memory according to the first parameter package information; The command processor is further used to compile the multiple first parameter packets according to the descriptor template to obtain a first target descriptor that can be recognized by the graphics processor.

2. The system according to claim 1, characterized in that The command processor includes a scheduling unit and a processing unit. The scheduling unit is used to read and parse the first instruction from the memory to obtain the first parameter package information; The scheduling unit is further configured to read the plurality of first parameter packages from the memory according to the first parameter package information; The processing unit is used to compile the multiple first parameter packets according to the descriptor template to obtain the first target descriptor.

3. The system according to claim 2, characterized in that The first target descriptor includes a first sub-target descriptor and a second sub-target descriptor, the processing unit includes a plurality of operator units and a plurality of micro-processing units, Each operator unit is used to compile a first parameter package that satisfies a first characteristic among the multiple first parameter packages according to the descriptor template to obtain the first sub-target descriptor, wherein the first characteristic is that the number of changes of the mapping rule of the first parameter package is zero, or the number of times participating in logical judgment is less than or equal to a first threshold, and the mapping rule is used to characterize the mapping relationship between the first parameter package and the descriptor; Each micro-processing unit is used to compile a first parameter package that satisfies a second characteristic among the multiple first parameter packages according to the descriptor template to obtain the second sub-target descriptor, wherein the second characteristic is that the number of changes in the mapping rule of the first parameter package is greater than zero, and the number of times it participates in logical judgment is greater than a first threshold.

4. The system according to claim 2 or 3, characterized in that: The command processor also includes on-chip memory, The on-chip memory is used to store the target descriptor and the descriptor template.

5. The system according to claim 4, characterized in that The command processor also includes a direct memory access, The direct memory access is used to write the target descriptor into the memory.

6. The system according to claim 5, characterized in that Before reading the first instruction from the memory, The direct memory access is further used to read the descriptor template from the memory and write the descriptor template into the on-chip memory.

7. The system according to any one of claims 2 to 6, characterized in that: Before reading the first instruction from the memory, The scheduling unit is further used to receive first indication information, where the first indication information is used to instruct the graphics processor to execute the first rendering task.

8. The system according to any one of claims 2 to 7, characterized in that: The scheduling unit is further configured to read and parse a second instruction from the memory to obtain second parameter package information, where the second instruction is an instruction corresponding to the second rendering task, and the second parameter package information includes storage addresses of multiple second parameter packages in the memory, where the multiple second parameter packages are second parameter packages in the second parameter packages corresponding to the second rendering task that are different from the multiple first parameter packages; The scheduling unit is further configured to read the plurality of second parameter packages from the memory according to the second parameter package information; The processing unit is further configured to compile the plurality of second parameter packets according to the descriptor template to obtain a second target descriptor.

9. A parameter processing method, characterized in that: Applied to a chip system, the chip system includes a memory and a graphics processing circuit, the graphics processing circuit includes a graphics processor and a command processor, the memory is used to store instructions and data, the graphics processor is used to perform rendering tasks according to a target descriptor, and the method includes: The command processor reads and parses a first instruction from the memory to obtain first parameter package information, where the first instruction is an instruction corresponding to a first rendering task, and the first parameter package information includes storage addresses of multiple first parameter packages corresponding to the first rendering task in the memory, where the types of the multiple parameters included in each first parameter package are the same, and the types of the multiple parameters included in any two first parameter packages are different; The command processor reads the plurality of first parameter packets from the memory according to the first parameter packet information; The command processor compiles the plurality of first parameter packets according to a descriptor template to obtain a first target descriptor that can be recognized by the graphics processor.

10. The method according to claim 9, characterized in that The command processor includes a scheduling unit and a processing unit, and the command processor reads and parses a first instruction from the memory to obtain first parameter package information, and reads the plurality of first parameter packages from the memory according to the first parameter package information, including: The scheduling unit reads and parses the first instruction from the memory to obtain first parameter package information; The scheduling unit reads the plurality of first parameter packages from the memory according to the first parameter package information; The command processor compiles the plurality of first parameter packets according to the descriptor template to obtain the first target descriptor, including: The processing unit compiles the multiple first parameter packets according to a descriptor template to obtain the first target descriptor.

11. The method according to claim 10, characterized in that The first target descriptor includes a first sub-target descriptor and a second sub-target descriptor, the processing unit includes a plurality of operator units and a plurality of micro-processing units, and the processing unit compiles the plurality of first parameter packets to obtain the first target descriptor, including: Each operator unit compiles a first parameter package satisfying a first characteristic among the multiple first parameter packages according to the descriptor template to obtain the first sub-target descriptor, wherein the first characteristic is that the number of changes of the mapping rule of the first parameter package is zero, or the number of times participating in logical judgment is less than or equal to a first threshold, and the mapping rule is used to characterize the mapping relationship between the first parameter package and the descriptor; Each microprocessing unit compiles a first parameter package among the multiple first parameter packages that meets a second characteristic according to the descriptor template to obtain the second sub-target descriptor, wherein the second characteristic is that the number of changes in the mapping rule of the first parameter package is greater than zero, and the number of times it participates in logical judgment is greater than a first threshold.

12. The method according to claim 10 or 11, characterized in that: The command processor also includes an on-chip memory, and the method further includes: The on-chip memory stores the target descriptor and the descriptor template.

13. The method according to claim 12, characterized in that The command processor also includes direct memory access, and the method further includes: The direct memory access writes the target descriptor into the memory.

14. The method according to claim 13, characterized in that Before reading the first instruction from the memory, the method further includes: The direct memory access reads the descriptor template from the memory and writes the descriptor template to the on-chip memory.

15. The method according to any one of claims 10 to 14, characterized in that: Before the scheduling unit reads the first instruction from the memory, the method further includes: The scheduling unit receives first indication information, where the first indication information is used to instruct the graphics processor to execute the first rendering task.

16. The method according to any one of claims 10 to 15, characterized in that: The method further comprises: The scheduling unit reads and parses a second instruction from the memory to obtain second parameter package information, where the second instruction is an instruction corresponding to the second rendering task, and the second parameter package information includes storage addresses of multiple second parameter packages in the memory, where the multiple second parameter packages are second parameter packages in the second parameter packages corresponding to the second rendering task that are different from the multiple first parameter packages; The scheduling unit reads the plurality of second parameter packages from the memory according to the second parameter package information; The processing unit compiles the plurality of second parameter packets according to the descriptor template to obtain a second target descriptor.

17. An electronic device, characterized in that: The electronic device comprises a circuit board and a chip system as described in any one of claims 1 to 8, wherein the chip system is arranged on the circuit board.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes computer instructions, and when the computer instructions are executed on the chip system, the chip system executes the parameter processing method according to any one of claims 9 to 16.

19. A computer program product comprising instructions, characterized in that When the computer program product is run on a computer device, the computer device is enabled to execute the parameter processing method according to any one of claims 9 to 16.

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