Driving circuit, driving chip, display panel and display device

Abstract

The application is suitable for the technical field of driving display, and provides a driving circuit, a driving chip, a display panel and a display device. The driving circuit comprises an operational amplifier module and a current generating module. The current generating module is electrically connected with the operational amplifier module. When the operational amplifier module is started, the current generating module is used for outputting a first current to a first tail current end of the operational amplifier module and a second current to a second tail current end of the operational amplifier module according to a first voltage and a third voltage, and outputting a third current to a third tail current end of the operational amplifier module and a fourth current to a fourth tail current end of the operational amplifier module according to a second voltage and the third voltage. When the operational amplifier module enters a normal working state, the current generating module stops outputting the first current, the second current, the third current and the fourth current. The application shortens the establishment time of the operational amplifier module without increasing power consumption, and meets the demand of the field of driving display for low power consumption.

Description

Technical Field

[0001] This application belongs to the field of display driving technology, and particularly relates to a driving circuit, a driving chip, a display panel, and a display device. Background Technology

[0002] Currently, in display fields such as LCD (Liquid Crystal Display), AMOLED (Active Matrix Organic Light Emitting Diode), and AMLED (Active Matrix Light Emitting Diode), in order to enhance the driving capability of the driver chip, a drive buffer is usually set at the channel output. When the grayscale voltage is above 11 bits, a dual-input operational amplifier with an interpolation DAC (Digital to Analog Converter) is mostly used as the drive buffer. Furthermore, since the display array of the display panel has a capacitive load, the drive buffer is required to have a certain load-carrying capacity.

[0003] However, due to the stringent power consumption requirements in the display field, a smaller operational amplifier quiescent current is designed when power consumption needs to be controlled. This increases the setup time of the drive buffer (the time from startup to normal operation), affecting the normal display. To shorten the setup time, the slew rate needs to be increased, but this increases the quiescent current of the entire operational amplifier, thereby increasing power consumption, which contradicts the requirement for low power consumption. Summary of the Invention

[0004] This application provides a driving circuit, a driving chip, a display panel, and a display device, which can solve the problem of the contradiction between the setup time and power consumption of existing driving buffers.

[0005] In a first aspect, embodiments of this application provide a driving circuit, including:

[0006] Operational amplifier module;

[0007] A current generating module, which is electrically connected to the operational amplifier module;

[0008] When the operational amplifier module is started, the current generation module is used to output a first current to the first tail current terminal of the operational amplifier module according to the first voltage and the third voltage, output a second current to the second tail current terminal of the operational amplifier module, output a third current to the third tail current terminal of the operational amplifier module according to the second voltage and the third voltage, and output a fourth current to the fourth tail current terminal of the operational amplifier module; wherein, the first voltage is the voltage on the first positive input terminal of the operational amplifier module, the second voltage is the voltage on the second positive input terminal of the operational amplifier module, the third voltage is the voltage on the feedback node of the operational amplifier module, and the feedback node is the node where the first inverting input terminal, the second inverting input terminal, and the output terminal of the operational amplifier module are connected together;

[0009] When the operational amplifier module enters normal working state, the current generation module stops outputting the first current, the second current, the third current, and the fourth current.

[0010] Specifically, when the operational amplifier module starts up, the current generation module utilizes the fact that the voltage at the inverting input terminal of the operational amplifier module is 0, and the voltage at the non-inverting input terminal is greater than the voltage at the inverting input terminal, to output a dynamic peak current to the tail current terminal of the operational amplifier module, thereby increasing the tail current of the operational amplifier module. Since the slew rate of the operational amplifier module is proportional to the tail current, the slew rate of the operational amplifier module will also increase after the tail current of the operational amplifier module increases, thus shortening the settling time of the operational amplifier module. When the operational amplifier module enters the normal operating state, the current generation module stops outputting current to the tail current terminal of the operational amplifier module, that is, it does not increase the static current of the operational amplifier module when it is in the normal state. Therefore, the driving circuit provided in this application shortens the settling time of the operational amplifier module without increasing power consumption, meeting the low power consumption requirements of the display driving field.

[0011] Secondly, embodiments of this application provide a driver chip, including the driver circuit described in any one of the first aspects.

[0012] Thirdly, embodiments of this application provide a display panel including a plurality of pixel circuits and at least one driving chip as described in the second aspect, wherein each driving chip is electrically connected to the plurality of pixel circuits.

[0013] Fourthly, embodiments of this application provide a display device including the display panel described in the third aspect.

[0014] The beneficial effects of the embodiments in this application compared with the prior art are:

[0015] This application provides a driving circuit including an operational amplifier module and a current generation module, which are electrically connected to the operational amplifier module. When the operational amplifier module is started, the current generation module outputs a first current to the first tail current terminal of the operational amplifier module based on a first voltage and a third voltage, outputs a second current to the second tail current terminal of the operational amplifier module, outputs a third current to the third tail current terminal of the operational amplifier module based on the second voltage and the third voltage, and outputs a fourth current to the fourth tail current terminal of the operational amplifier module; wherein, the first voltage is the voltage on the first positive input terminal of the operational amplifier module, the second voltage is the voltage on the second positive input terminal of the operational amplifier module, the third voltage is the voltage on the feedback node of the operational amplifier module, and the feedback node is a node where the first inverting input terminal, the second inverting input terminal, and the output terminal of the operational amplifier module are connected together.

[0016] When the operational amplifier module enters normal operating mode, the current generation module stops outputting the first current, the second current, the third current, and the fourth current.

[0017] In this application, when the operational amplifier module starts up, the current generation module utilizes the fact that the voltage at the inverting input terminal of the operational amplifier module is 0, and the voltage at the non-inverting input terminal is greater than the voltage at the inverting input terminal, to output a dynamic peak current to the tail current terminal of the operational amplifier module, thereby increasing the tail current of the operational amplifier module. Since the slew rate of the operational amplifier module is proportional to the tail current, the slew rate of the operational amplifier module will also increase after the tail current of the operational amplifier module increases, thus shortening the settling time of the operational amplifier module. When the operational amplifier module enters the normal operating state, the current generation module stops outputting current to the tail current terminal of the operational amplifier module, that is, it does not increase the static current of the operational amplifier module when it is in the normal operating state. Therefore, the driving circuit provided in this application shortens the settling time of the operational amplifier module without increasing power consumption, meeting the low power consumption requirements of the display driving field.

[0018] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic block diagram of an existing dual-input operational amplifier;

[0021] Figure 2 This is a schematic block diagram of a driving circuit provided in one embodiment of this application;

[0022] Figure 3 This is a schematic block diagram of a driving circuit provided in another embodiment of this application;

[0023] Figure 4 This is a schematic block diagram of a driving circuit provided in another embodiment of this application;

[0024] Figure 5 yes Figure 3 The circuit connection diagram of the first current generating unit in the driving circuit shown is shown.

[0025] Figure 6 yes Figure 3 The circuit connection diagram of the second current generating unit in the driving circuit shown is shown.

[0026] Figure 7 This is a simulation diagram of a driving circuit provided in one embodiment of this application.

[0027] In the diagram: 10. Operational amplifier module; 11. First current mirror; 12. Second current mirror; 13. First current difference adjustment unit; 14. Second current difference adjustment unit; 15. First transconducting linear loop; 16. Second transconducting linear loop; 20. Current generation module; 21. First current generation unit; 211. First current mirror unit; 212. First enable subunit; 213. First switch subunit; 214. Second current mirror unit; 215. Second enable subunit; 22. Second current generation unit; 221. Third enable subunit; 222. Third current mirror unit; 223. Second switch subunit; 224. Fourth enable subunit; 225. Fourth current mirror unit. Detailed Implementation

[0028] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0029] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0030] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0031] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."

[0032] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0033] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0034] In the display fields of LCD, AMOLED, and AMLED, multiple driver chips are typically used to drive the display array, enabling it to display images and content. The number of driver chips is usually related to the size of the display array and its own number of channels. Driver chips can have 16, 48, 64, or 96 channels, etc., and the appropriate number of channels can be selected based on actual needs. The following explanation uses one channel of a driver chip as an example to illustrate its working principle.

[0035] The driver chip includes timing control circuits, data latches, level conversion circuits, and DAC (Digital-to-Analog Converter) circuits. To improve the driving capability of the driver chip, a drive buffer is also included. The timing control circuit generates timing signals and control signals, including row scan signals and column scan signals. The row scan signal controls the refresh order of pixels in each row of the display array, and the column scan signal selects the column of pixels to be refreshed. The data latch stores and holds the pixel data to be displayed, so that it can be passed to the next-level circuit at the appropriate time. The level conversion circuit converts the digital signal into a level or voltage suitable for the drive buffer. The DAC circuit converts the digital pixel data processed by the data latch and level conversion circuit into an analog voltage signal suitable for controlling the display array. The drive buffer improves the driving capability of the analog voltage signal.

[0036] When the grayscale voltage of the display array is above 11 bits, a dual-input operational amplifier with a differential DAC is usually used as the drive buffer. Figure 1 A schematic block diagram of a dual-input operational amplifier is shown. (e.g.) Figure 1 As shown, the dual-input operational amplifier mainly includes a bias current generation circuit, a differential input circuit, an output circuit, a first current difference adjustment unit 13, a second current difference adjustment unit 14, a first current mirror 11, a second current mirror 12, a first transconducting linear loop 15, and a second transconducting linear loop 16.

[0037] The bias current generation circuit includes a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a sixth NMOS transistor MN6, and a fifth NMOS transistor MN5. The differential input circuit includes two pairs of PMOS transistors and two pairs of NMOS transistors. One pair of PMOS transistors includes a first PMOS transistor MP1 and a second PMOS transistor MP2. The source of the first PMOS transistor MP1 is electrically connected to the source of the second PMOS transistor MP2, the drain of the sixth PMOS transistor MP6, and the first current difference adjustment unit 13, respectively. Their common connection terminal is the first tail current terminal of the operational amplifier, denoted as PS_H. The other pair of PMOS transistors includes a third PMOS transistor MP3 and a fourth PMOS transistor MP4. The source of the third PMOS transistor MP3 is electrically connected to the source of the fourth PMOS transistor MP4 and the first current difference adjustment unit 13, respectively. Their common connection terminal is the third tail current terminal of the operational amplifier, denoted as PS_L. One pair of NMOS transistors includes a first NMOS transistor MN1 and a second NMOS transistor MN2. The source of the first NMOS transistor MN1 is electrically connected to the source of the second NMOS transistor MN2, the drain of the sixth NMOS transistor MN6, and the second current difference adjustment unit 14. Their common connection terminal is the second tail current terminal of the operational amplifier, denoted as NS_H. The other pair of NMOS transistors includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4. The source of the third NMOS transistor MN3 is electrically connected to the source of the fourth NMOS transistor MN4 and the second current difference adjustment unit 14. Their common connection terminal is the fourth tail current terminal of the operational amplifier, denoted as NS_L. The output circuit adopts a class AB structure, including a seventh PMOS transistor MP7 and a seventh NMOS transistor MN7. The drain of the seventh PMOS transistor MP7 is electrically connected to the drain of the seventh NMOS transistor MN7. Their common connection terminal is the output terminal of the operational amplifier.

[0038] The gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 serve as the first inverting input of the operational amplifier. The gates of the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 serve as the second inverting input of the operational amplifier. The first inverting input, the second inverting input, and the output of the operational amplifier are electrically connected. The node where they are connected serves as the feedback node, and the voltage at the feedback node is the third voltage VN. The gates of the second PMOS transistor MP2 and the second NMOS transistor MN2 serve as the first non-inverting input of the operational amplifier, and the voltage at the first non-inverting input is the first voltage VH. The gates of the third PMOS transistor MP3 and the third NMOS transistor MN3 serve as the second non-inverting input of the operational amplifier, and the voltage at the second non-inverting input is the second voltage VL.

[0039] The first current mirror 11 and the second current mirror 12 adopt a common source, common gate structure. The number of bits of the first current difference adjustment unit 13 and the second current difference adjustment unit 14 is related to the number of bits of the DAC circuit connected to the front stage of the operational amplifier. The number of bits of the first current difference adjustment unit 13 and the second current difference adjustment unit 14 can be set according to the actual situation during use.

[0040] The circuit structure of the drive buffer has been described above. From its structure, we can determine that the function of the drive buffer is to improve the driving capability of the driver chip. To improve the driving capability of the driver chip, the drive buffer needs to have a certain load-carrying capacity. However, due to the strict power consumption requirements in the display field, a smaller operational amplifier quiescent current is designed when power consumption is to be controlled. This increases the settling time of the drive buffer, affecting the normal display. Conversely, to shorten the settling time, the slew rate needs to be increased, which increases the quiescent current of the entire operational amplifier, thus increasing power consumption. This contradicts the requirement for low power consumption.

[0041] To address the aforementioned problems, embodiments of this application provide a driving circuit, such as... Figure 2 As shown, the drive circuit includes an operational amplifier module 10 and a current generation module 20. The current generation module 20 is electrically connected to the operational amplifier module 10. According to... Figure 2 It can be seen that the input terminals of the current generation module 20 are electrically connected to the first positive input terminal, the second positive input terminal, and the feedback node FB of the operational amplifier module 10, respectively. The output terminals of the current generation module 20 are connected to the first tail current terminal PS_H, the second tail current terminal NS_H, the third tail current terminal PS_L, and the fourth tail current terminal NS_L of the operational amplifier module 10, respectively. The circuit structure of the operational amplifier module 10 is exactly the same as that of a dual-input operational amplifier, and will not be described again here.

[0042] In this embodiment, when the operational amplifier module 10 is started, the current generation module 20 outputs a first current to the first tail current terminal PS_H of the operational amplifier module 10 based on the first voltage VH and the third voltage VN, and outputs a second current to the second tail current terminal NS_H of the operational amplifier module 10. The first current is equal to the second current, and both the first and second currents are dynamic peak currents. It also outputs a third current to the third tail current terminal PS_L of the operational amplifier module 10 based on the second voltage VL and the third voltage VN, and outputs a fourth current to the fourth tail current terminal NS_L of the operational amplifier module 10. The third current is equal to the fourth current, and both the third and fourth currents are dynamic peak currents. Here, the first voltage VH is the voltage at the first positive input terminal of the operational amplifier module 10, the second voltage VL is the voltage at the second positive input terminal of the operational amplifier module 10, and the third voltage VN is the voltage at the feedback node FB of the operational amplifier module 10. The feedback node FB is a node where the first inverting input terminal, the second inverting input terminal, and the output terminal of the operational amplifier module 10 are connected together.

[0043] When the operational amplifier module 10 enters normal working state, the current generation module 20 stops outputting the first current, the second current, the third current, and the fourth current.

[0044] When the operational amplifier module 10 starts up, the current generating module 20 utilizes the fact that the voltage VN at the inverting input terminal of the operational amplifier module 10 is 0, and the voltages VH and VL at the non-inverting input terminal are both greater than the voltage VN at the inverting input terminal, to output a dynamic peak current to the tail current terminal of the operational amplifier module 10, thereby increasing the tail current of the operational amplifier module 10. Since the slew rate of the operational amplifier module 10 is proportional to the tail current, the slew rate of the operational amplifier module 10 will also increase after the tail current of the operational amplifier module 10 increases, thus shortening the setup time of the operational amplifier module 10. When the operational amplifier module 10 enters the normal operating state, the current generating module 20 stops outputting current to the tail current terminal of the operational amplifier module 10, that is, it does not increase the static current of the operational amplifier module 10 when it is in the normal operating state. Therefore, the driving circuit provided in this application shortens the setup time of the operational amplifier module 10 without increasing power consumption, meeting the low power consumption requirements of the display driving field.

[0045] like Figure 3 As shown, the current generation module 20 includes a first current generation unit 21 and a second current generation unit 22. The first current generation unit 21 is electrically connected to the feedback node FB, the first positive input terminal, the first tail current terminal PS_H, and the second tail current terminal NS_H of the operational amplifier module 10, respectively. The second current generation unit 22 is electrically connected to the feedback node FB, the second positive input terminal, the third tail current terminal PS_L, and the fourth tail current terminal NS_L of the operational amplifier module 10, respectively. Figure 3 It can be seen that the input terminal of the first current generating unit 21 is electrically connected to the first positive input terminal and the feedback node FB of the operational amplifier module 10, respectively, and the output terminal of the first current generating unit 21 is electrically connected to the first tail current terminal PS_H and the second tail current terminal NS_H of the operational amplifier module 10, respectively. The input terminal of the second current generating unit 22 is electrically connected to the second positive input terminal and the feedback node FB of the operational amplifier module 10, respectively, and the output terminal of the second current generating unit 22 is electrically connected to the third tail current terminal PS_L and the fourth tail current terminal NS_L of the operational amplifier module 10, respectively.

[0046] In this embodiment, when the operational amplifier module 10 is started, the first current generating unit 21 is used to output a first current to the first tail current terminal PS_H of the operational amplifier module 10 according to the first voltage VH and the third voltage VN, and to output a second current to the second tail current terminal NS_H of the operational amplifier module 10, wherein the first current is equal to the second current. The second current generating unit 22 is used to output a third current to the third tail current terminal PS_L of the operational amplifier module 10 according to the second voltage VL and the third voltage VN, and to output a fourth current to the fourth tail current terminal NS_L of the operational amplifier module 10.

[0047] When the operational amplifier module 10 enters normal operating mode, the first current generating unit 21 stops outputting the first and second currents. The second current generating unit 22 stops outputting the third and fourth currents.

[0048] When the operational amplifier module 10 starts up, the first current generating unit 21 utilizes the fact that the voltage VN on the inverting input terminal of the operational amplifier module 10 is 0, and the voltage VH on the first non-inverting input terminal is greater than the voltage VN on the inverting input terminal, to output a dynamic peak current to the first tail current terminal PS_H and the second tail current terminal NS_H of the operational amplifier module 10; the second current generating unit 22 utilizes the fact that the voltage VN on the inverting input terminal of the operational amplifier module 10 is 0, and the voltage VL on the second non-inverting input terminal is greater than the voltage VN on the inverting input terminal, to output a dynamic peak current to the third tail current terminal PS_L and the fourth tail current terminal NS_L of the operational amplifier module 10, so as to increase the tail current of the operational amplifier module 10. Since the slew rate of the operational amplifier module 10 is proportional to the tail current, the slew rate of the operational amplifier module 10 will also increase after the tail current of the operational amplifier module 10 is increased, thus shortening the setup time of the operational amplifier module 10.

[0049] When the operational amplifier module 10 enters normal operating state, the first current generating unit 21 stops outputting the first current to the first tail current terminal PS_H and the second current to the second tail current terminal NS_H of the operational amplifier module 10. The second current generating unit 22 stops outputting the third current to the third tail current terminal PS_L and the fourth current to the fourth tail current terminal NS_L of the operational amplifier module 10. This means that the static current of the operational amplifier module 10 in normal operating state is not increased. Therefore, the driving circuit provided in this embodiment shortens the setup time of the operational amplifier module 10 without increasing power consumption, meeting the low-power requirements of the display driving field.

[0050] It should be noted that when the operational amplifier module 10 is started, the first current generating unit 21 and the second current generating unit 22 simultaneously output current to the operational amplifier module 10. When the operational amplifier module 10 enters the normal working state, the first current generating unit 21 and the second current generating unit 22 simultaneously stop outputting current to the operational amplifier module 10.

[0051] like Figure 4 As shown, the first current generating unit 21 includes a first current mirror unit 211, a first enable subunit 212, a second current mirror unit 214, a first switch subunit 213, and a second enable subunit 215. The first switch subunit 213 is electrically connected to the feedback node FB, the first positive input terminal, the first current mirror unit 211, the first enable subunit 212, the second current mirror unit 214, and the second enable subunit 215 of the operational amplifier module 10, respectively. The first current mirror unit 211 is electrically connected to the first tail current terminal PS_H of the operational amplifier module 10, and the second current mirror unit 214 is electrically connected to the second tail current terminal NS_H of the operational amplifier module 10. The first current mirror unit 211 and the first enable subunit 212 are both used to be electrically connected to the first power supply AVDD, and the second current mirror unit 214 and the second enable subunit 215 are both used to be grounded.

[0052] In this embodiment, when the operational amplifier module 10 is not started, the first enable subunit 212 is used to turn on according to the first enable signal and output a first clamping voltage to the first current mirror unit 211, so that the first current mirror unit 211 does not work. The second enable subunit 215 is used to turn on according to the second enable signal and output a second clamping voltage to the second current mirror unit 214, so that the second current mirror unit 214 does not work. The function of the first enable subunit 212 and the second enable subunit 215 is to ensure that the first current mirror unit 211 and the second current mirror unit 214 do not work when the operational amplifier module 10 is not started, so that the first current generating unit 21 does not consume current. It should be noted that the first enable signal is a low-level signal and the second enable signal is a high-level signal.

[0053] When the operational amplifier module 10 is started, the first enable subunit 212 is used to disconnect according to the first enable signal, so that the first current mirror unit 211 can start working. The second enable subunit 215 is used to disconnect according to the second enable signal, so that the second current mirror unit 214 can start working. The first switch subunit 213 is used to turn on according to the first voltage VH and the third voltage VN, so that the first current mirror unit 211 outputs a first current to the first tail current terminal PS_H of the operational amplifier module 10, and the second current mirror unit 214 outputs a second current to the second tail current terminal NS_H of the operational amplifier module 10.

[0054] When the operational amplifier module 10 enters normal working state, the third voltage VN is no longer equal to 0, but becomes larger than 0 and tends to stabilize. The first switch subunit 213 is used to disconnect according to the first voltage VH and the third voltage VN, so that the first current mirror unit 211 stops outputting the first current and the second current mirror unit 214 stops outputting the second current.

[0055] like Figure 5 As shown, the first current mirror unit 211 includes a first MOS transistor M1 and a second MOS transistor M2. The source of the first MOS transistor M1 and the source of the second MOS transistor M2 are both used to be electrically connected to the first power supply AVVDD. The gate of the first MOS transistor M1 is electrically connected to the drain of the first MOS transistor M1, the gate of the second MOS transistor M2, the first enable subunit 212 and the first switch subunit 213, respectively. The drain of the second MOS transistor M2 is electrically connected to the first tail current terminal PS_H of the operational amplifier module 10.

[0056] In this embodiment, when the first enable subunit 212 is turned on, a first clamping voltage is output to the gate of the first MOSFET M1. Since the connection of the first MOSFET M1 is equivalent to that of a diode, the first MOSFET M1 is turned off, causing the first current mirror unit 211 to stop working. When the first enable subunit 212 is turned off, it indicates that the operational amplifier module 10 has started. At this time, the first switch subunit 213 is turned on. Since the connection of the first MOSFET M1 is equivalent to that of a diode, current is generated on the first MOSFET M1. Through the mirroring effect of the current mirror, current is also generated on the second MOSFET M2, i.e., the first current. When the operational amplifier module 10 enters the normal operating state, the first switch subunit 213 is turned off, and there is no longer any current on the first MOSFET M1, i.e., the first current is stopped being output.

[0057] For example, the first MOS transistor M1 and the second MOS transistor M2 are both PMOS (positive channel metal oxide semiconductor) transistors.

[0058] It should be noted that the first current mirror unit 211 can also be replaced by other units that perform its function, and is not limited to this.

[0059] like Figure 5 As shown, the first enable subunit 212 includes a third MOSFET M3. The gate of the third MOSFET M3 is used to receive the first enable signal EN. The source of the third MOSFET M3 is electrically connected to the first power supply AVDD. The drain of the third MOSFET M3 is electrically connected to the first current mirror unit 211 and the first switch subunit 213, respectively. The first enable signal EN is a low-level signal when the operational amplifier module 10 is not turned on, and the first enable signal EN becomes a high-level signal after the operational amplifier module 10 is turned on. Figure 5 It can be seen that the drain of the third MOS transistor M3 is electrically connected to the gate of the first MOS transistor M1, the drain of the first MOS transistor M1, the gate of the second MOS transistor M2, and the first switch subunit 213, respectively.

[0060] For example, the third MOS transistor M3 is a PMOS transistor.

[0061] In this embodiment, when the operational amplifier module 10 is not turned on, the first enable signal EN is a low-level signal, the third MOSFET M3 is turned on, and the first clamping voltage AVDD is output to the first current mirror unit 211. When the operational amplifier module 10 is turned on, the first enable signal EN becomes a high-level signal, and the third MOSFET M3 is turned off.

[0062] It should be noted that the first enabling subunit 212 can also be replaced by other units that implement its function, and is not limited to this.

[0063] like Figure 5 As shown, the first switching subunit 213 includes a fourth MOSFET M4 and a fifth MOSFET M5. The gate of the fourth MOSFET M4 is used to receive a first voltage VH, and the gate of the fifth MOSFET M5 is used to receive a third voltage VN. The drain of the fourth MOSFET M4 is electrically connected to the first current mirror unit 211 and the first enable subunit 212, respectively. The source of the fourth MOSFET M4 is electrically connected to the source of the fifth MOSFET M5, and the drain of the fifth MOSFET M5 is electrically connected to the second current mirror unit 214 and the second enable subunit 215, respectively. Figure 5 It can be seen that the drain of the fourth MOSFET M4 is electrically connected to the gate of the first MOSFET M1, the drain of the first MOSFET M1, the gate of the second MOSFET M2, and the drain of the third MOSFET.

[0064] For example, the fourth MOS transistor M4 is an NMOS (N-Metal-Oxide-Semiconductor) transistor, and the fifth MOS transistor M5 is a PMOS transistor.

[0065] In this embodiment, when the operational amplifier module 10 is first turned on, the third voltage VN is equal to 0, so the fifth MOSFET M5 is turned on. The first voltage VH is greater than 0, so the fourth MOSFET M4 is turned on. Then, the branch containing the fourth MOSFET M4 and the fifth MOSFET M5 will generate current. Through the mirroring effect of the first current mirror unit 211 and the second current mirror unit 214, the first current will be output to the first tail current terminal PS_H of the operational amplifier module 10, and the second current will be output to the second tail current terminal NS_H of the operational amplifier module 10, thereby increasing the tail current of the operational amplifier module 10 and shortening the setup time of the operational amplifier module 10.

[0066] When the operational amplifier module 10 enters normal operating state, the third voltage VN becomes greater than 0, and the fifth MOSFET M5 turns off. This stops the output of the first current to the first tail current terminal PS_H and the second current to the second tail current terminal NS_H of the operational amplifier module 10, thus preventing an increase in the quiescent current required for the operational amplifier module 10 to enter normal operating state. This application shortens the setup time of the operational amplifier module 10 without increasing power consumption.

[0067] It should be noted that the first switch subunit 213 can also be replaced by other units that perform its function, and is not limited to this.

[0068] like Figure 5As shown, the second current mirror unit 214 includes a sixth MOSFET M6 and a seventh MOSFET M7. The gate of the sixth MOSFET M6 is electrically connected to the drain of the sixth MOSFET M6, the gate of the seventh MOSFET M7, the first switching subunit 213, and the second enabling subunit 215, respectively. The sources of the sixth MOSFET M6 and the seventh MOSFET M7 are both grounded. The drain of the seventh MOSFET M7 is electrically connected to the second tail current terminal NS_H of the operational amplifier module 10. According to Figure 5 It can be seen that the gate of the sixth MOS transistor M6 is electrically connected to the drain of the sixth MOS transistor M6, the gate of the seventh MOS transistor M7, the drain of the fifth MOS transistor M5, and the second enable sub-unit 215.

[0069] In this embodiment, when the second enable subunit 215 is turned on, a second clamping voltage is output to the gate of the sixth MOSFET M6. Since the connection of the sixth MOSFET M6 is equivalent to that of a diode, the sixth MOSFET M6 is turned off, causing the second current mirror unit 214 to not work. When the second enable subunit 215 is turned off, it indicates that the operational amplifier module 10 has started. At this time, the first switch subunit 213 is turned on. Since the connection of the sixth MOSFET M6 is equivalent to that of a diode, a current will be generated on the sixth MOSFET M6. Through the mirroring effect of the current mirror, a current will also be generated on the seventh MOSFET M7, i.e., the second current. When the operational amplifier module 10 enters the normal operating state, the first switch subunit 213 is turned off, and there is no longer any current on the sixth MOSFET M6, i.e., the output of the second current stops.

[0070] For example, the sixth MOSFET M6 and the seventh MOSFET M7 are both NMOS transistors.

[0071] It should be noted that the second current mirror unit 214 can also be replaced by other units that perform its function, and is not limited to this.

[0072] like Figure 5 As shown, the second enable subunit 215 includes an eighth MOS transistor M8. The gate of the eighth MOS transistor M8 is used to receive the second enable signal ENB, the source of the eighth MOS transistor M8 is used to ground AGND, and the drain of the eighth MOS transistor M8 is electrically connected to the second current mirror unit 214 and the first switch subunit 213, respectively. The second enable signal ENB is a high-level signal when the operational amplifier module 10 is not turned on, and becomes a low-level signal after the operational amplifier module 10 is turned on. Figure 5 It can be seen that the drain of the eighth MOSFET M8 is electrically connected to the gate of the sixth MOSFET M6, the drain of the sixth MOSFET, the gate of the seventh MOSFET M7, and the drain of the fifth MOSFET M5, respectively.

[0073] For example, the eighth MOS transistor M8 is an NMOS transistor.

[0074] In this implementation, when the operational amplifier module 10 is not turned on, the second enable signal ENB is a high-level signal, the eighth MOSFET M8 is turned on, and the second clamping voltage AGND is output to the second current mirror unit 214. When the operational amplifier module 10 is turned on, the second enable signal ENB becomes a low-level signal, and the eighth MOSFET M8 is turned off.

[0075] It should be noted that the second enabling subunit 215 can also be replaced by other units that perform its function, and is not limited to this.

[0076] like Figure 4 As shown, the second current generating unit 22 includes a third enabling subunit 221, a third current mirror unit 222, a second switching subunit 223, a fourth enabling subunit 224, and a fourth current mirror unit 225. The second switching subunit 223 is electrically connected to the feedback node FB, the second positive input terminal, the third enabling subunit 221, the third current mirror unit 222, the fourth current mirror unit 225, and the fourth enabling subunit 224 of the operational amplifier module 10, respectively. The third current mirror unit 222 is connected to the third tail current terminal PS_L of the operational amplifier module 10. The fourth current mirror unit 225 is electrically connected to the fourth tail current terminal NS_L of the operational amplifier module 10. The third enabling subunit 221 and the third current mirror unit 222 are both used to be electrically connected to the first power supply AVDD. The fourth enabling subunit 224 and the fourth current mirror unit 225 are both used to ground AGND.

[0077] In this embodiment, when the operational amplifier module 10 is not started, the third enable subunit 221 is turned on according to the first enable signal and outputs a third clamping voltage to the third current mirror unit 222, so that the third current mirror unit 222 does not work. The fourth enable subunit 224 is turned on according to the second enable signal and outputs a fourth clamping voltage to the fourth current mirror unit 225, so that the fourth current mirror unit 225 does not work. The function of the third enable subunit 221 and the fourth enable subunit 224 is to ensure that the third current mirror unit 222 and the fourth current mirror unit 225 do not work when the operational amplifier module 10 is not started, so that the second current generating unit 22 does not consume current.

[0078] When the operational amplifier module 10 is started, the third enable subunit 221 is used to disconnect according to the first enable signal, so that the third current mirror unit 222 can be turned on. The fourth enable subunit 224 is used to disconnect according to the second enable signal, so that the fourth current mirror unit 225 can be turned on. The second switch subunit 223 is used to turn on according to the second voltage VL and the third voltage VN, so that the third current mirror unit 222 outputs the third current to the third tail current terminal PS_L of the operational amplifier module 10, and the fourth current mirror unit 225 outputs the fourth current to the fourth tail current terminal NS_L of the operational amplifier module 10.

[0079] When the operational amplifier module 10 enters normal operation, the third voltage VN is no longer equal to 0, but becomes larger than 0 and tends to stabilize. The second switch subunit 223 is used to disconnect according to the second voltage VL and the third voltage VN, so that the third current mirror unit 222 stops outputting the third current and the fourth current mirror unit 225 stops outputting the fourth current.

[0080] like Figure 6 As shown, the third enable subunit 221 includes a ninth MOS transistor M9. The gate of the ninth MOS transistor M9 is used to receive the first enable signal EN. The source of the ninth MOS transistor M9 is used to be electrically connected to the first power supply AVDD. The drain of the ninth MOS transistor M9 is electrically connected to the third current mirror unit 222 and the second switch subunit 223, respectively.

[0081] For example, the ninth MOS transistor M9 is a PMOS transistor.

[0082] In this embodiment, when the operational amplifier module 10 is not enabled, the first enable signal EN is a low-level signal, the ninth MOSFET M9 is turned on, and the third clamping voltage AVDD is output to the third current mirror unit 222. When the operational amplifier module 10 is enabled, the first enable signal EN becomes a high-level signal, and the ninth MOSFET M9 is turned off.

[0083] It should be noted that the third enabling subunit 221 can also be replaced by other units that implement its function, and is not limited to this.

[0084] like Figure 6 As shown, the third current mirror unit 222 includes a tenth MOSFET M10 and an eleventh MOSFET M11. The gate of the tenth MOSFET M10 is electrically connected to the drain of the tenth MOSFET M10, the gate of the eleventh MOSFET M11, the third enable subunit 221, and the second switch subunit 223, respectively. The sources of the tenth MOSFET M10 and the eleventh MOSFET M11 are both electrically connected to the first power supply AVDD. The drain of the eleventh MOSFET M11 is electrically connected to the third tail current terminal PS_L of the operational amplifier module 10. Figure 6It can be seen that the gate of the tenth MOS transistor M10 is electrically connected to the drain of the tenth MOS transistor M10, the gate of the eleventh MOS transistor M11, the drain of the ninth MOS transistor M9, and the second switch subunit 223.

[0085] In this embodiment, when the third enable subunit 221 is turned on (i.e., the ninth MOSFET M9 is turned on), a third clamping voltage AVDD is output to the gate of the tenth MOSFET M10. Since the connection of the tenth MOSFET M10 is equivalent to that of a diode, the tenth MOSFET M10 is turned off, causing the third current mirror unit 222 to not work. When the third enable subunit 221 is turned off (i.e., the ninth MOSFET M9 is turned off), it indicates that the operational amplifier module 10 starts up. At this time, the second switch subunit 223 is turned on. Since the connection of the tenth MOSFET M10 is equivalent to that of a diode, a current will be generated on the tenth MOSFET M10. Through the mirroring effect of the current mirror, a current will also be generated on the eleventh MOSFET M11, i.e., the third current. When the operational amplifier module 10 enters the normal operating state, the second switch subunit 223 is turned off, and there is no longer a current on the tenth MOSFET M10, i.e., the output of the third current stops.

[0086] For example, the tenth MOSFET M10 and the eleventh MOSFET M11 are both PMOS transistors.

[0087] It should be noted that the third current mirror unit 222 can also be replaced by other units that perform its function, and is not limited to this.

[0088] like Figure 6 As shown, the second switching subunit 223 includes a twelfth MOSFET M12 and a thirteenth MOSFET M13. The gate of the twelfth MOSFET M12 is used to receive a third voltage VN, and the gate of the thirteenth MOSFET M13 is used to receive a second voltage VL. The drain of the twelfth MOSFET M12 is electrically connected to the third enable subunit 221 and the third current mirror unit 222, respectively. The source of the twelfth MOSFET M12 is electrically connected to the source of the thirteenth MOSFET M13, and the drain of the thirteenth MOSFET M13 is electrically connected to the fourth enable subunit 224 and the fourth current mirror unit 225, respectively. According to... Figure 6 It can be seen that the drain of the twelfth MOSFET M12 is electrically connected to the drain of the ninth MOSFET M9, the drain of the tenth MOSFET M10, the gate of the tenth MOSFET M10, and the gate of the eleventh MOSFET M11.

[0089] For example, the twelfth MOSFET M12 is an NMOS transistor, and the thirteenth MOSFET M13 is a PMOS transistor.

[0090] In this embodiment, when the operational amplifier module 10 is first turned on, the third voltage VN is equal to 0, so the thirteenth MOSFET M13 is turned on. The second voltage VL is greater than 0, so the twelfth MOSFET M12 is turned on. Then, the branch containing the twelfth MOSFET M12 and the thirteenth MOSFET M13 will generate current. Through the mirroring effect of the third current mirror unit 222 and the fourth current mirror unit 225, the third current will be output to the third tail current terminal PS_L of the operational amplifier module 10, and the fourth current will be output to the second tail current terminal NS_L of the operational amplifier module 10. This increases the tail current of the operational amplifier module 10, thus shortening the setup time of the operational amplifier module 10.

[0091] When the operational amplifier module 10 enters normal operating state, the third voltage VN becomes greater than 0, and the thirteenth MOSFET M13 turns off. This stops the output of the third current to the third tail current terminal PS_L and the fourth current to the fourth tail current terminal NS_L of the operational amplifier module 10, thus preventing an increase in the quiescent current required for the operational amplifier module 10 to enter normal operating state. This application shortens the setup time of the operational amplifier module 10 without increasing power consumption.

[0092] It should be noted that the second switch subunit 223 can also be replaced by other units that perform its function, and is not limited to this.

[0093] like Figure 6 As shown, the fourth enable subunit 224 includes a fourteenth MOS transistor M14. The gate of the fourteenth MOS transistor M14 is used to receive the second enable signal ENB, the source of the fourteenth MOS transistor M14 is used to ground AGND, and the drain of the fourteenth MOS transistor M14 is electrically connected to the second switch subunit 223 and the fourth current mirror unit 225, respectively. According to Figure 6 It can be seen that the drain of the fourteenth MOSFET M14 is electrically connected to the drain of the thirteenth MOSFET M13 and the fourth current mirror unit 225, respectively.

[0094] For example, the fourteenth MOS transistor M14 is an NMOS transistor.

[0095] In this embodiment, when the operational amplifier module 10 is not enabled, the second enable signal ENB is a high-level signal, the fourteenth MOSFET M14 is turned on, and outputs the fourth clamping voltage AGND to the fourth current mirror unit 225. When the operational amplifier module 10 is enabled, the second enable signal ENB becomes a low-level signal, and the fourteenth MOSFET M14 is turned off.

[0096] It should be noted that the fourth enabling subunit 224 can also be replaced by other units that implement its function, and is not limited to this.

[0097] like Figure 6As shown, the fourth current mirror unit 225 includes a fifteenth MOSFET M15 and a sixteenth MOSFET M16. The gate of the fifteenth MOSFET M15 is electrically connected to the drain of the fifteenth MOSFET M15, the gate of the sixteenth MOSFET M16, the fourth enable subunit 224, and the second switch subunit 223, respectively. The sources of the fifteenth MOSFET M15 and the sixteenth MOSFET M16 are both used to ground AGND. The drain of the sixteenth MOSFET M16 is connected to the fourth tail current terminal NS_L of the operational amplifier module 10. According to Figure 6 It can be seen that the gate of the fifteenth MOSFET M15 is electrically connected to the drain of the fifteenth MOSFET M15, the gate of the sixteenth MOSFET M16, the drain of the fourteenth MOSFET M14, and the drain of the thirteenth MOSFET M13, respectively.

[0098] In this embodiment, when the fourth enable subunit 224 is turned on (i.e., the fourteenth MOSFET M14 is turned on), a fourth clamping voltage AGND is output to the gate of the fifteenth MOSFET M15. Since the connection of the fifteenth MOSFET M15 is equivalent to that of a diode, the fifteenth MOSFET M15 is turned off, causing the fourth current mirror unit 225 to not work. When the fourth enable subunit 224 is turned off (i.e., the fourteenth MOSFET M14 is turned off), it indicates that the operational amplifier module 10 starts up. At this time, the second switch subunit 223 is turned on. Since the connection of the fifteenth MOSFET M15 is equivalent to that of a diode, a current will be generated on the fifteenth MOSFET M15. Through the mirroring effect of the current mirror, a current will also be generated on the seventeenth MOSFET M17, i.e., the fourth current. When the operational amplifier module 10 enters the normal operating state, the second switch subunit 223 is turned off, and there is no longer a current on the fifteenth MOSFET M15, i.e., the output of the fourth current stops.

[0099] For example, the fifteenth MOSFET M15 and the sixteenth MOSFET M16 are both NMOS transistors.

[0100] It should be noted that the fourth current mirror unit 225 can also be replaced by other units that perform its function, and is not limited to this.

[0101] The following is combined Figure 1 , Figure 5 and Figure 6 The working principle of the driving circuit provided in the embodiments of this application will be described.

[0102] like Figure 1As shown, the voltages at the first inverting input terminal, the second inverting input terminal, and the output terminal of the operational amplifier module 10 are the third voltage VN, the first voltage VH at the first non-inverting input terminal, and the second voltage VL at the second non-inverting input terminal. When the operational amplifier module 10 starts up, the third voltage VN is 0V, and both the first voltage VH and the second voltage VN are greater than 0V. Utilizing this characteristic, the first voltage VH and the third voltage VN are used as control signals for the first current generating unit 21, combined with... Figure 5 It can be seen that the fourth MOSFET M4 in the first current generation unit 21 is turned on under the control of the first voltage VH, and the fifth MOSFET M5 in the first current generation unit 21 is turned on under the control of the third voltage VN. Since the connection of the first MOSFET M1 and the sixth MOSFET M6 is equivalent to that of a diode, a current will be generated in the branch where the first MOSFET M1 is located when the fourth MOSFET M4 and the fifth MOSFET are turned on. Then, through the mirroring effect of the current mirror, a current will also be generated in the second MOSFET M2 and the seventh MOSFET M7, thereby outputting the first current to the first tail current terminal PS_H of the operational amplifier module 10 and the second current to the second tail current terminal NS_H of the operational amplifier module 10.

[0103] Simultaneously, the second voltage VL and the third voltage VN are used as control signals for the second current generating unit 22, combined with Figure 6 It can be seen that the twelfth MOSFET M12 in the second current generation unit 22 is turned on under the control of the second voltage VN, and the thirteenth MOSFET M13 in the second current generation unit 22 is turned on under the control of the third voltage VN. Since the connection of the tenth MOSFET M10 and the fifteenth MOSFET M15 is equivalent to a diode, a current will be generated in the branch where the tenth MOSFET M10 is located when the twelfth MOSFET M12 and the thirteenth MOSFET M13 are turned on. Then, through the mirror effect of the current mirror, a current will also be generated in the eleventh MOSFET M11 and the sixteenth MOSFET M16, and then the third current will be output to the third tail current terminal PS_L of the operational amplifier module 10, and the fourth current will be output to the fourth tail current terminal NS_L of the operational amplifier module 10. During the startup process of the operational amplifier module 10, the current output by the first current generating unit 21 and the second current generating unit 22 to the tail current terminal of the operational amplifier module 10 is a dynamic peak current, which will increase the tail current of the operational amplifier module 10. Since the slew rate of the operational amplifier module 10 is proportional to the tail current, the slew rate of the operational amplifier module 10 will also increase after the tail current of the operational amplifier module 10 increases, thus shortening the setup time of the operational amplifier module 10.

[0104] When the operational amplifier module 10 enters normal operating mode, the third voltage VN is greater than 0V and tends to stabilize. Therefore, the fifth MOSFET in the first current generation unit 21 will turn off, and the thirteenth MOSFET in the second current generation unit 22 will turn off. Consequently, the first current generation unit 21 stops outputting the first and second currents, and the second current generation unit 22 stops outputting the third and fourth currents. When the operational amplifier module 10 enters normal operating mode, the first and second current generation units 21 and 22 stop outputting current to the tail current terminal of the operational amplifier module 10, thus not increasing the static current of the operational amplifier module 10 during normal operating mode. Therefore, the driving circuit provided in this embodiment shortens the setup time of the operational amplifier module 10 without increasing power consumption, meeting the low-power requirements of the display driving field.

[0105] Figure 7 A simulation schematic diagram of the driving circuit provided in an embodiment of this application is shown. From Figure 7 It can be seen that the driving circuit provided in this application embodiment shortens the voltage settling time by 867ns after adding the current generation module 20, which is particularly important for driving the display field.

[0106] This application also provides a driver chip, including a timing control circuit, a data latch, a level conversion circuit, a DAC circuit, and multiple driver circuits described above. The data latch is electrically connected to both the timing control circuit and the level conversion circuit. The DAC circuit is electrically connected to both the level conversion circuit and the multiple driver circuits described above. Specifically, the output of the timing control circuit is connected to the input of the data latch, the output of the data latch is connected to the input of the level conversion circuit, the output of the level conversion circuit is connected to the input of the DAC circuit, and the output of the DAC circuit is connected to the operational amplifier module in the driver circuit of the aforementioned embodiment. It should be noted that the number of channels in the driver chip in this embodiment is related to the operational amplifier module in the aforementioned driver circuit; that is, the channel terminals of the driver chip are correspondingly connected to the input terminals of the operational amplifier modules in the driver circuit. For the working principles of each module in the driver chip, please refer to the above description, which will not be repeated here.

[0107] The driver chip provided in this application embodiment can shorten its setup time while meeting the low power consumption requirement. For the specific working principle, please refer to the description of the working principle of the driver circuit described above, which will not be repeated here.

[0108] This application also provides a display panel, including multiple pixel circuits and at least one of the aforementioned driving chips. Each driving chip is electrically connected to the multiple pixel circuits and is used to drive the light-emitting diodes in the multiple pixel circuits to emit light.

[0109] This application also provides a display device, including the display panel described above.

[0110] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0111] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A drive circuit characterized by comprising: The application relates to an operational amplifier module and a current generating module. The application relates to an operational amplifier module and a current generating module. When the operational amplifier module is started, the current generating module is used for outputting a first current to a first tail current end of the operational amplifier module and a second current to a second tail current end of the operational amplifier module according to a first voltage and a third voltage, and outputting a third current to a third tail current end of the operational amplifier module and a fourth current to a fourth tail current end of the operational amplifier module according to a second voltage and the third voltage; wherein the first voltage is a voltage on a first positive input end of the operational amplifier module, the second voltage is a voltage on a second positive input end of the operational amplifier module, and the third voltage is a voltage on a feedback node of the operational amplifier module, the feedback node being a node where a first negative input end, a second negative input end and an output end of the operational amplifier module are connected together. When the operational amplifier module enters a normal working state, the current generating module stops outputting the first current, the second current, the third current and the fourth current. The current generating module comprises:

2. The drive circuit according to claim 1, characterized in that, A first current generating unit, which is electrically connected with the feedback node, the first positive input end, the first tail current end and the second tail current end of the operational amplifier module respectively. A second current generating unit, which is electrically connected with the feedback node, the second positive input end, the third tail current end and the fourth tail current end of the operational amplifier module respectively. When the operational amplifier module is started, the first current generating unit is used for outputting the first current to the first tail current end of the operational amplifier module and the second current to the second tail current end of the operational amplifier module according to the first voltage and the third voltage, and the second current generating unit is used for outputting the third current to the third tail current end of the operational amplifier module and the fourth current to the fourth tail current end of the operational amplifier module according to the second voltage and the third voltage. When the operational amplifier module enters the normal working state, the first current generating unit stops outputting the first current and the second current, and the second current generating unit stops outputting the third current and the fourth current. The first current generating unit comprises a first current mirror unit, a first enabling subunit, a second current mirror unit, a first switch subunit and a second enabling subunit, the first switch subunit is electrically connected with the feedback node, the first positive input end, the first current mirror unit, the first enabling subunit, the second current mirror unit and the second enabling subunit of the operational amplifier module respectively, the first current mirror unit is electrically connected with the first tail current end of the operational amplifier module, the second current mirror unit is electrically connected with the second tail current end of the operational amplifier module, the first current mirror unit and the first enabling subunit are used for being electrically connected with a first power supply, and the second current mirror unit and the second enabling subunit are grounded.

3. The drive circuit according to claim 2, characterized in that, ​ When the operational amplifier module is not started, the first enabling subunit is used for being turned on according to a first enabling signal and outputting a first clamping voltage to the first current mirror subunit, so that the first current mirror subunit is not worked, and the second enabling subunit is used for being turned on according to a second enabling signal and outputting a second clamping voltage to the second current mirror subunit, so that the second current mirror subunit is not worked; When the operational amplifier module is started, the first enabling subunit is used for being turned off according to the first enabling signal, so that the first current mirror subunit is started to work, the second enabling subunit is used for being turned off according to the second enabling signal, so that the second current mirror subunit is started to work, and the first switch subunit is used for being turned on according to the first voltage and the third voltage, so that the first current mirror subunit outputs the first current to a first tail current end of the operational amplifier module, and the second current mirror subunit outputs the second current to a second tail current end of the operational amplifier module; When the operational amplifier module enters a normal working state, the first switch subunit is used for being turned off according to the first voltage and the third voltage, so that the first current mirror subunit stops outputting the first current, and the second current mirror subunit stops outputting the second current.

4. The drive circuit according to claim 3, characterized in that, The first current mirror subunit comprises a first MOS tube and a second MOS tube, the source of the first MOS tube and the source of the second MOS tube are used for being electrically connected with the first power supply, the gate of the first MOS tube is electrically connected with the drain of the first MOS tube, the gate of the second MOS tube, the first enabling subunit and the first switch subunit respectively, and the drain of the second MOS tube is electrically connected with the first tail current end of the operational amplifier module.

5. The drive circuit according to claim 3, characterized by The first enabling subunit comprises a third MOS tube, the gate of the third MOS tube is used for receiving the first enabling signal, the source of the third MOS tube is used for being electrically connected with the first power supply, and the drain of the third MOS tube is electrically connected with the first current mirror subunit and the first switch subunit respectively.

6. The drive circuit according to claim 3, characterized by The first switch subunit comprises a fourth MOS tube and a fifth MOS tube, the gate of the fourth MOS tube is used for receiving the first voltage, the gate of the fifth MOS tube is used for receiving the third voltage, the drain of the fourth MOS tube is electrically connected with the first current mirror subunit and the first enabling subunit respectively, the source of the fourth MOS tube is electrically connected with the source of the fifth MOS tube, and the drain of the fifth MOS tube is electrically connected with the second current mirror subunit and the second enabling subunit respectively.

7. The drive circuit according to claim 3, characterized by The second current mirror subunit comprises a sixth MOS tube and a seventh MOS tube, the gate of the sixth MOS tube is electrically connected with the drain of the sixth MOS tube, the gate of the seventh MOS tube, the first switch subunit and the second enabling subunit respectively, the source of the sixth MOS tube and the source of the seventh MOS tube are used for being grounded, and the drain of the seventh MOS tube is electrically connected with the second tail current end of the operational amplifier module.

8. The drive circuit according to claim 3, characterized by The second enabling subunit comprises an eighth MOS tube, a gate of the eighth MOS tube is configured to receive the second enabling signal, a source of the eighth MOS tube is configured to be grounded, and a drain of the eighth MOS tube is electrically connected with the second current mirror subunit and the first switch subunit respectively.

9. The drive circuit of claim 2, wherein, The second current generating unit comprises a third enabling subunit, a third current mirror subunit, a second switch subunit, a fourth enabling subunit and a fourth current mirror subunit, the second switch subunit is electrically connected with a feedback node of the operational amplifier module, a second positive input end, the third enabling subunit, the third current mirror subunit, the fourth current mirror subunit and the fourth enabling subunit respectively, the third current mirror subunit is electrically connected with a third tail current end of the operational amplifier module, the fourth current mirror subunit is electrically connected with a fourth tail current end of the operational amplifier module, the third enabling subunit and the third current mirror subunit are configured to be electrically connected with a first power supply, and the fourth enabling subunit and the fourth current mirror subunit are configured to be grounded; When the operational amplifier module is not started, the third enabling subunit is configured to be turned on according to a first enabling signal, and output a third clamping voltage to the third current mirror subunit, so that the third current mirror subunit does not work, and the fourth enabling subunit is configured to be turned on according to a second enabling signal, and output a fourth clamping voltage to the fourth current mirror subunit, so that the fourth current mirror subunit does not work; When the operational amplifier module is started, the third enabling subunit is configured to be turned off according to the first enabling signal, so that the third current mirror subunit starts to work, the fourth enabling subunit is configured to be turned off according to the second enabling signal, so that the fourth current mirror subunit starts to work, and the second switch subunit is configured to be turned on according to the second voltage and the third voltage, so that the third current mirror subunit outputs the third current to the third tail current end of the operational amplifier module, and the fourth current mirror subunit outputs the fourth current to the fourth tail current end of the operational amplifier module; When the operational amplifier module enters a normal working state, the second switch subunit is configured to be turned off according to the second voltage and the third voltage, so that the third current mirror subunit stops outputting the third current, and the fourth current mirror subunit stops outputting the fourth current.

10. A driving chip, characterized in that, The driving circuit of any one of claims 1-9.

11. A display panel, characterized by, The display panel of claim 11.

12. A display device, characterized by comprising: ​

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