GDL circuit, driving method and gate driving circuit

Abstract

The invention belongs to the technical field of display driving, and particularly relates to a GDL circuit, a driving method and a gate driving circuit, and the GDL circuit comprises a frequency overturning module which is used for outputting a first level signal in a DC power supply end when a display panel is in low-frequency driving, the level transmission module is also used for outputting a second level signal in the level transmission connecting end when the display panel is in high-frequency driving; the control module is used for outputting a first level signal or a second level signal under the action of the cascade transmission signal; the output module is used for outputting a gate driving signal under the action of the first level signal or the second level signal; an overturning signal is added to the input end of the control module, so that the display panel is connected with direct-current voltage at low frequency; and the cascade transmission connecting end is accessed at high frequency, so that the falling edge trailing phenomenon of a gate driving signal is reduced while the electric leakage difference between high and low frequencies is compatible, pixel error punching is prevented, and the picture display effect is improved.

Description

Technical Field

[0001] The present disclosure belongs to the field of display driving technology, and in particular relates to a GDL circuit, a driving method and a gate driving circuit. Background Art

[0002] As people's understanding of liquid crystal display technology and the requirements for display quality continue to increase, the requirements for the image quality of liquid crystal display screens are also gradually increasing; however, it is found in related technologies that due to the leakage current of transistor devices in the GDL (Gate Driver less) circuit, the falling edge of the output gate drive signal (Gout) waveform has a tailing phenomenon, causing mischarging between pixels and affecting the display effect. Summary of the invention

[0003] The present application provides a GDL circuit, a driving method and a gate driving circuit, which solve the problem of tailing of the falling edge of the gate driving signal waveform. The present application adds a flip signal at the input end of the control module, so that the display panel is connected to the DC voltage at low frequency; and connected to the stage transmission connection end at high frequency. While being compatible with the leakage difference between high and low frequencies, the tailing phenomenon of the falling edge of the gate driving signal is reduced, pixel misshooting is prevented, and the picture display effect is improved.

[0004] In a first aspect, the present application provides a GDL circuit, which includes: a frequency flip module, a first input end of the frequency flip module is connected to a DC power supply end, a second input end of the frequency flip module is connected to a level transmission connection end, and is used to output a first level signal in the DC power supply end when the display panel is in a low-frequency drive, and is also used to output a second level signal in the level transmission connection end when the display panel is in a high-frequency drive; a control module, a control end of the control module is connected to the level transmission connection end, a first end of the control module is connected to an output end of the frequency flip module, and is used to output a first level signal or a second level signal under the action of the level transmission signal; an output module, a control end of the output module is connected to a second end of the control module, a first end of the output module is connected to a clock signal end, and the second end of the output module is used as a drive signal output end of the GDL circuit, and is used to output a gate drive signal under the action of the first level signal or the second level signal.

[0005] Optionally, the frequency flip module includes: a low-frequency unit, the input end of the low-frequency unit is connected to the DC power supply end, the first output end of the low-frequency unit is connected to the first end of the control module, and is used to output a first level signal when the DC power supply end outputs a high level; a high-frequency unit, the first input end of the high-frequency unit is connected to the stage transmission connection end, the second input end of the high-frequency unit is connected to the second output end of the low-frequency unit, and the output end of the high-frequency unit is connected to the first end of the control module, and is used to output a second level signal when the DC power supply end outputs a low level; wherein the DC power supply end outputs a high level when the display panel is in low-frequency driving, and outputs a low level when the display panel is in high-frequency driving.

[0006] Optionally, the low-frequency unit includes: a first transistor, the control end of the first transistor is connected to the DC power supply end, the first end of the first transistor is connected to the second input end of the high-frequency unit, and the second end of the first transistor is connected to the low voltage end; a second transistor, the control end of the second transistor is connected to the control end of the first transistor, the first end of the second transistor is connected to the control end of the second transistor, and the second end of the second transistor is connected to the first end of the control module.

[0007] Optionally, the high-frequency unit includes: a third transistor, the control end of the third transistor is connected to the stage transfer connection end, the first end of the third transistor is connected to the control end of the third transistor, and the second end of the third transistor is connected to the first end of the first transistor; a fourth transistor, the control end of the fourth transistor is connected to the second end of the third transistor, the first end of the fourth transistor is connected to the first end of the third transistor, and the second end of the fourth transistor is connected to the first end of the control module.

[0008] Optionally, the control module includes: a fifth transistor, the control end of the fifth transistor is connected to the stage transfer connection end, the first end of the fifth transistor is connected to the output end of the frequency flip module, and the second end of the fifth transistor serves as the second end of the control module.

[0009] Optionally, the output module includes: a sixth transistor, the control end of the sixth transistor is connected to the second end of the fifth transistor, the first end of the sixth transistor is connected to the clock signal end, and the second end of the sixth transistor serves as the drive signal output end of the GDL circuit.

[0010] Optionally, the output module also includes: a seventh transistor, the control end of the seventh transistor is connected to the drive signal output end of the next level GDL circuit, the first end of the seventh transistor is connected to the control end of the seventh transistor, and the second end of the seventh transistor is connected to the control end of the sixth transistor.

[0011] Optionally, the output module further includes: a bootstrap capacitor, a first end of the bootstrap capacitor is connected to the control end of the sixth transistor, and a second end of the bootstrap capacitor is connected to the second end of the sixth transistor.

[0012] In the second aspect, the present application provides a driving method, which is applied to the GDL circuit, and the driving method includes: obtaining the current driving frequency of the display panel; if the current driving frequency is a low frequency, controlling the DC power supply end to output a high level so that the frequency flipping module outputs a first level signal; if the current driving frequency is a high frequency, controlling the DC power supply end to output a low level so that the frequency flipping module outputs a second level signal in the stage transmission connection end; the control module controls the output module to output a gate drive signal according to the first level signal or the second level signal.

[0013] In the second aspect, the present application provides a gate drive circuit, which includes: a frequency detection circuit for detecting the current driving frequency of the display panel; a power supply circuit connected to the frequency detection circuit, and used to output a high level or a low level according to a control signal output by the frequency detection circuit; N cascaded GDL circuits, each GDL circuit is respectively connected to the power supply circuit and the corresponding scan line in the display panel, and is used to output a corresponding gate drive signal under the action of the power supply circuit output signal.

[0014] The technical solution provided by this application has at least the following beneficial effects:

[0015] In the present application, when it is detected that the display panel is in low-frequency driving, the frequency flip module outputs a first level signal in the DC power supply end, and the control module controls the output module to output a gate drive signal under the action of the first level signal and the level transmission signal in the level transmission connection end; when it is detected that the display panel is in high-frequency driving, the frequency flip module outputs a second level signal in the level transmission connection end, and the control module controls the output module to output a gate drive signal under the action of the second level signal and the level transmission signal in the level transmission connection end; the present application adds a flip signal to the input end of the control module, so that the display panel is connected to the DC voltage at low frequency; and connected to the level transmission connection end at high frequency, while being compatible with the leakage difference between high and low frequencies, reducing the trailing phenomenon of the falling edge of the gate drive signal, preventing pixel misshooting, and improving the picture display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0017] Figure 1 Shown is a schematic diagram of a screen abnormality provided in an embodiment of the present application.

[0018] Figure 2 The figure is a schematic diagram comparing the falling edge time of the Gout waveforms of a normal product and an abnormal product provided in an embodiment of the present application.

[0019] Figure 3 Shown is a schematic diagram of a GDL circuit provided in an embodiment of the present application.

[0020] Figure 4 Shown is a schematic diagram of a Gout waveform under different conditions provided in an embodiment of the present application.

[0021] Figure 5 Shown is a schematic diagram of current flow during low-frequency driving provided in an embodiment of the present application.

[0022] Figure 6 Shown is a schematic diagram of current flow during high-frequency driving provided by an embodiment of the present application.

[0023] Figure 7 Shown is a waveform diagram of a fifth transistor provided in an embodiment of the present application when connected to different input terminals.

[0024] Figure 8 The figure is a flow chart of a driving method provided in an embodiment of the present application.

[0025] Fig. 9 The figure shows a schematic diagram of the level transmission relationship of a GDL circuit provided in an embodiment of the present application.

[0026] Description of reference numerals:

[0027] 100, GDL circuit; 110, frequency flip module; 111, low frequency unit; 112, high frequency unit; 120, control module; 130, output module;

[0028] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; C, bootstrap capacitor.

[0029] VDD, DC power supply terminal; VF, stage transfer connection terminal; CLK, clock signal terminal; VGL, low voltage terminal; Gn, drive signal output terminal of GDL circuit; Gn+1, drive signal output terminal of next stage GDL circuit. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0031] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0032] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0033] As people's understanding of LCD technology and the requirements for display quality continue to improve, the requirements for LCD screen image quality are also gradually increasing. In the production process of LCD panels, some unpredictable poor image quality often occurs. For example, MNT (Monitor) products have such Figure 1 The image distortion phenomenon shown in the figure; among them, 1a represents the white horizontal stripes seen by the human eye, and 1b represents the pixel display seen in the eyepiece.

[0034] By comparing the GDL circuit design of MNT products, it is found that the Mura of the frequency reduction level band of T1 connected to VGH is reduced, and the frequency reduction level band of T1 connected to Cn-3 / Gn-3 is deteriorated; the cause analysis process is as follows:

[0035] 1. Electrical debugging: The electrical VGH / VGL / HZ confirmation is as follows. The Vcom adjustment phenomenon has no change, and the Duty upward adjustment phenomenon is serious. The specific debugging results are shown in Table 1:

[0036] Table 1. Debugging results

[0037]

[0038] 2. Confirmation of Gout output waveform: Figure 2 As shown, the falling edge time (Falling Time) of the abnormal (NG) piece has a tail compared to the normal (OK) piece, and the electrical Falling Time of the NG piece changes.

[0039] After the above cause analysis, it is confirmed that the abnormality is caused by device leakage, which leads to Gout Falling Time tailing, causing wrong charging and affecting the quality. In order to solve the above problem, the present application provides a GDL circuit, which specifically includes the following embodiments:

[0040] Figure 3 FIG. 1 is a schematic diagram of a GDL circuit provided in an embodiment of the present application; Figure 3 As shown, the GDL circuit 100 includes a frequency flip module 110, a control module 120 and an output module 130; the first input end of the frequency flip module 110 is connected to the DC power supply end VDD, and the second input end of the frequency flip module 110 is connected to the level transfer connection end VF, which is used to output the first level signal in the DC power supply end VDD when the display panel is in low-frequency driving, and is also used to output the second level signal in the level transfer connection end VF when the display panel is in high-frequency driving.

[0041] In this embodiment, the control end of the control module 120 is connected to the level transmission connection end VF, and the first end of the control module 120 is connected to the output end of the frequency flip module 110, for outputting a first level signal or a second level signal under the action of the level transmission signal.

[0042] In this embodiment, the control end of the output module 130 is connected to the second end of the control module 120, the first end of the output module 130 is connected to the clock signal end CLK, and the second end of the output module 130 is used as the drive signal output end Gn of the GDL circuit, which is used to output the gate drive signal under the action of the first level signal or the second level signal.

[0043] It should be noted that the gate drive circuit (GOA circuit) includes multiple cascaded GOA units, each GOA unit includes at least one GDL circuit, and the gate drive signal output by the GDL circuit is used to open the scan line in the display panel; however, the display panel has a high-frequency drive with a higher refresh frequency and a low-frequency drive with a lower refresh frequency; when the driver chip detects different refresh frequencies of the display panel, it controls the DC power supply terminal VDD to output different DC voltages, that is, the DC power supply terminal VDD outputs a high level when the display panel is in low-frequency drive, and outputs a low level when the display panel is in high-frequency drive; wherein the first level signal corresponds to a high level, and the second level signal corresponds to a low level.

[0044] In this embodiment, the level transmission connection terminal VF can be the level transmission terminal of the upper GDL circuit, or the drive signal output terminal of the upper GDL circuit, and the level transmission signal output by the level transmission terminal of the GDL circuit is the same as the gate drive signal output by the output terminal. If the nth level is defined by the GDL circuit, the level transmission connection terminal VF of the upper GDL circuit corresponds to the nx level, and x is any value such as 1, 2, 3, 4, etc., and this embodiment takes x equal to 3 as an example, Figure 3 Gn-3 in the figure represents the driving signal output terminal of the upper three-stage GDL circuit, and Cn-3 represents the level transmission terminal of the upper three-stage GDL circuit.

[0045] In this embodiment, when it is detected that the display panel is in low-frequency driving, the frequency flip module 110 outputs a first level signal in the DC power supply terminal VDD, and the control module 120 controls the output module 130 to output a gate drive signal under the action of the first level signal and the level transmission signal in the level transmission connection terminal VF; when it is detected that the display panel is in high-frequency driving, the frequency flip module 110 outputs a second level signal in the level transmission connection terminal VF, and the control module 120 controls the output module 130 to output a gate drive signal under the action of the second level signal and the level transmission signal in the level transmission connection terminal VF.

[0046] The GDL circuit provided in this embodiment is simulated, and the gate drive signal (Gout) waveform obtained is as follows: Figure 4 As shown, 4a represents the Gout waveform of the first level signal output by the frequency flip module 110 at a refresh frequency of 100 Hz; 4b represents the Gout waveform of the second level signal output by the frequency flip module 110 at a refresh frequency of 100 Hz; 4c represents the Gout waveform of the first level signal output by the frequency flip module 110 at a refresh frequency of 48 Hz; 4d represents the Gout waveform of the second level signal output by the frequency flip module 110 at a refresh frequency of 48 Hz. By comparison, it can be seen that through the analysis of the above simulation and Gout measured waveforms, it is concluded that the tailing phenomenon of the falling edge can be reduced when the frequency flip module 110 outputs the first level signal in the DC power supply terminal VDD at low frequency.

[0047] The reason why the first level signal in the DC power supply terminal VDD output by the frequency flip module 110 can reduce the tailing phenomenon compared with the second level signal in the output stage transfer connection terminal VF at low frequency is that: the input of the control module 120 is connected to VGH (the first level signal at this time) and the input to the stage transfer connection terminal VF (the second level signal at this time), and the leakage difference of the Q point in the Gout pull-down VGL stage is relatively large. The main reason is that the signal input to the stage transfer connection terminal VF is the output signal of the first three-stage GDL circuit, and the transistor device in the GDL circuit itself has leakage. After the frequency is reduced, the time for the picture to display one frame becomes longer, and the leakage phenomenon is more serious. When the DC power supply terminal VDD is input, a DC signal is input, and there is no leakage phenomenon itself, resulting in a large difference in Gout falling time.

[0048] In one embodiment, if Figure 3 As shown, the frequency flip module 110 includes: a low-frequency unit 111 and a high-frequency unit 112; wherein, the input end of the low-frequency unit 111 is connected to the DC power supply end VDD, and the first output end of the low-frequency unit 111 is connected to the first end of the control module 120, and is used to output a first level signal when the DC power supply end VDD outputs a high level; the first input end of the high-frequency unit 112 is connected to the stage transmission connection end VF, the second input end of the high-frequency unit 112 is connected to the second output end of the low-frequency unit 111, and the output end of the high-frequency unit 112 is connected to the first end of the control module 120, and is used to output a second level signal when the DC power supply end VDD outputs a low level.

[0049] like Figure 3 As shown, the low-frequency unit 111 includes: a first transistor T1, the control end of the first transistor T1 is connected to the DC power supply end VDD, the first end of the first transistor T1 is connected to the second input end of the high-frequency unit 112, and the second end of the first transistor T1 is connected to the low voltage end VGL; a second transistor T2, the control end of the second transistor T2 is connected to the control end of the first transistor T1, the first end of the second transistor T2 is connected to the control end of the second transistor T2, and the second end of the second transistor T2 is connected to the first end of the control module 120.

[0050] The high-frequency unit 112 includes: a third transistor T3, the control end of the third transistor T3 is connected to the stage transfer connection end VF, the first end of the third transistor T3 is connected to the control end of the third transistor T3, and the second end of the third transistor T3 is connected to the first end of the first transistor T1; a fourth transistor T4, the control end of the fourth transistor T4 is connected to the second end of the third transistor T3, the first end of the fourth transistor T4 is connected to the first end of the third transistor T3, and the second end of the fourth transistor T4 is connected to the first end of the control module 120.

[0051] In one embodiment, the control module 120 includes: a fifth transistor T5, the control end of the fifth transistor T5 is connected to the stage transfer connection end VF, the first end of the fifth transistor T5 is connected to the output end of the frequency flip module 110, and the second end of the fifth transistor T5 serves as the second end of the control module 120.

[0052] In one embodiment, the output module 130 includes: a sixth transistor T6, the control end of the sixth transistor T6 is connected to the second end of the fifth transistor T5, the first end of the sixth transistor T6 is connected to the clock signal end CLK, and the second end of the sixth transistor T6 serves as the drive signal output end Gn of the GDL circuit.

[0053] In one embodiment, the output module 130 also includes: a seventh transistor T7, the control end of the seventh transistor T7 is connected to the drive signal output end Gn+1 of the next level GDL circuit, the first end of the seventh transistor T7 is connected to the control end of the seventh transistor T7, and the second end of the seventh transistor T7 is connected to the control end of the sixth transistor T6.

[0054] In one embodiment, the output module 130 further includes: a bootstrap capacitor C, a first end of the bootstrap capacitor C is connected to the control end of the sixth transistor T6 , and a second end of the bootstrap capacitor C is connected to the second end of the sixth transistor T6 .

[0055] It should be noted that when the display panel is in low-frequency driving, the DC power supply terminal VDD outputs a high level. In the low-frequency unit 111, the control terminal of the first transistor T1 is connected to the DC power supply terminal VDD, the first transistor T1 is turned on, the source of the first transistor T1 is connected to the low voltage terminal VGL, and the fourth transistor T4 of the high-frequency unit 112 is turned off. The control terminal and the source of the second transistor T2 in the low-frequency unit 111 are connected to the DC power supply terminal VDD, the second transistor T2 is turned on, the drain of the second transistor T2 is connected to the source of the fifth transistor T5, the stage transfer connection terminal VF connected to the control terminal of the fifth transistor T5 is high, and the fifth transistor T5 is turned on, so the sixth transistor T6 can be controlled by the fifth transistor T5 to output a gate drive signal; wherein the current flows as shown in FIG. Figure 5 shown.

[0056] When the display panel is in high-frequency driving, the DC power supply terminal VDD outputs a low level, and the first transistor T1 and the second transistor T2 in the low-frequency unit 111 are in an off state; in the high-frequency unit 112, the stage transmission connection terminal VF outputs a high level, the control terminal and the source of the third transistor T3 are connected to the high level, and the third transistor T3 is turned on, so that the control terminal of the fourth transistor T4 is connected to the drain of the fourth transistor T4, the fourth transistor T4 is turned on, the source of the fourth transistor T4 is connected to the stage transmission connection terminal VF and the source of the third transistor T3, the drain of the fourth transistor T4 is connected to the source of the fifth transistor T5, the stage transmission connection terminal VF connected to the control terminal of the fifth transistor T5 is high, and the fifth transistor T5 is turned on, so the sixth transistor T6 can be controlled by the fifth transistor T5 to output a gate drive signal; wherein the current flows as shown in FIG. Figure 6 shown.

[0057] Figure 7 The waveform diagram of the fifth transistor T5 connected to the stage transmission connection terminal VF and the DC power supply terminal VDD, when a high level is input to the gate of T5, the T5 device is turned on and the Q point is pulled high, which shows stage one. After the Q point is pulled high, T6 is turned on, and the clock signal output by the clock signal terminal CLK is transmitted to the drive signal output terminal, and the Q point is pulled high again through the bootstrap capacitor C, so that T6 is opened more fully, which is stage two; the Q point is pulled down by the pull-down circuit in the circuit, which is stage three; when T5 is connected to the high level output by the DC power supply terminal VDD, the T5 of this stage is turned on by the high level, and then the clock signal output by the control clock signal terminal CLK is transmitted to the drive signal output terminal for output; when T5 is connected to the stage transmission connection terminal VF, the T5 of this stage is turned on by the stage transmission signal, and then the clock signal output by the control clock signal terminal CLK is transmitted to the drive signal output terminal for output, which is stage four. Among them, Figure 7 The main difference between the two waveforms is that the holding potential of point Q and the falling edge of the gate drive signal GN are quite different. The holding potential of point Q when T5 is connected to the DC power supply terminal VDD is more stable than that when T5 is connected to the stage transfer terminal VF. Similarly, the falling edge of the gate drive signal is better.

[0058] Furthermore, in this embodiment, by providing the seventh transistor T7 , the sixth transistor T6 can be turned on more completely, thereby reducing the falling edge time of the gate driving signal.

[0059] It can be seen that the present application adds a flip signal to the input terminal of T5, so that when the frequency is low, the input terminal of T5 is connected to the DC power supply terminal VDD; when the frequency is high, the input terminal of T5 is connected to the stage transfer connection terminal VF. Its advantage is that it can be compatible with the leakage difference between high and low frequencies, so that the Gout falling difference is smaller; in addition, a TFT device is added to the gate of T6, and the gate and source of the TFT are connected to the drive output terminal of the next level. Its advantage is that the gate voltage of T6 is increased, so that the output of the gate drive signal is better, so that the falling edge time of the gate drive signal can be effectively reduced, thereby shortening the GOE time, reducing mischarging, improving horizontal band Mura, and improving the taste of the product.

[0060] Figure 8 FIG. 1 is a flow chart of a driving method provided in an embodiment of the present application; Figure 8 As shown, the driving method applied to the GDL circuit in the above embodiment specifically includes the following steps:

[0061] Step S100, obtaining the current driving frequency of the display panel;

[0062] Step S200, determining whether the current driving frequency is a low frequency; if the current driving frequency is a low frequency, executing step S300, if the current driving frequency is a high frequency, executing step S400;

[0063] Step S300, controlling the DC power supply end to output a high level, so that the frequency flip module outputs a first level signal;

[0064] Step S400, controlling the DC power supply end to output a low level, so that the output stage of the frequency flip module transmits the second level signal in the connection end;

[0065] Step S500: The control module controls the output module to output a gate driving signal according to the first level signal or the second level signal.

[0066] It should be noted that the driving principle of this driving method is the same as the working principle of the above-mentioned GDL circuit, which will not be repeated here.

[0067] In one embodiment, the present application provides a gate drive circuit, the gate drive circuit comprising: a frequency detection circuit, a power supply circuit and N cascaded GDL circuits; the frequency detection circuit is used to detect the current drive frequency of the display panel; the power supply circuit is connected to the frequency detection circuit, and is used to output a high level or a low level according to the control signal output by the frequency detection circuit; each GDL circuit is respectively connected to the power supply circuit and the corresponding scan line in the display panel, and is used to output a corresponding gate drive signal under the action of the output signal of the power supply circuit; wherein the cascade relationship of the GDL circuit is as follows Fig. 9 shown.

[0068] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", "third" may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0069] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0070] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A GDL circuit, characterized in that: The GDL circuit comprises: A frequency flip module, wherein a first input end of the frequency flip module is connected to a DC power supply end, and a second input end of the frequency flip module is connected to a level transmission connection end, and is used to output a first level signal in the DC power supply end when the display panel is in low-frequency driving, and is also used to output a second level signal in the level transmission connection end when the display panel is in high-frequency driving; A control module, wherein a control end of the control module is connected to the level transmission connection end, and a first end of the control module is connected to an output end of the frequency flip module, and is used to output a first level signal or a second level signal under the action of a level transmission signal; An output module, wherein the control end of the output module is connected to the second end of the control module, the first end of the output module is connected to the clock signal end, and the second end of the output module is used as the drive signal output end of the GDL circuit, for outputting a gate drive signal under the action of the first level signal or the second level signal.

2. The GDL circuit according to claim 1, characterized in that: The frequency flip module comprises: A low-frequency unit, wherein the input end of the low-frequency unit is connected to the DC power supply end, and the first output end of the low-frequency unit is connected to the first end of the control module, and is used to output a first level signal when the DC power supply end outputs a high level; A high-frequency unit, wherein a first input end of the high-frequency unit is connected to the stage transmission connection end, a second input end of the high-frequency unit is connected to the second output end of the low-frequency unit, and an output end of the high-frequency unit is connected to the first end of the control module, and is used to output a second level signal when the DC power supply end outputs a low level; Wherein, the DC power supply terminal outputs a high level when the display panel is in low-frequency driving, and outputs a low level when the display panel is in high-frequency driving.

3. The GDL circuit according to claim 2, characterized in that: The low frequency unit comprises: a first transistor, wherein a control terminal of the first transistor is connected to the DC power supply terminal, a first terminal of the first transistor is connected to the second input terminal of the high-frequency unit, and a second terminal of the first transistor is connected to a low voltage terminal; A second transistor, wherein the control end of the second transistor is connected to the control end of the first transistor, the first end of the second transistor is connected to the control end of the second transistor, and the second end of the second transistor is connected to the first end of the control module.

4. The GDL circuit according to claim 3, characterized in that: The high frequency unit comprises: a third transistor, wherein the control terminal of the third transistor is connected to the stage transfer connection terminal, the first terminal of the third transistor is connected to the control terminal of the third transistor, and the second terminal of the third transistor is connected to the first terminal of the first transistor; A fourth transistor, wherein the control end of the fourth transistor is connected to the second end of the third transistor, the first end of the fourth transistor is connected to the first end of the third transistor, and the second end of the fourth transistor is connected to the first end of the control module.

5. The GDL circuit according to claim 1, characterized in that: The control module comprises: A fifth transistor, wherein the control end of the fifth transistor is connected to the stage transfer connection end, the first end of the fifth transistor is connected to the output end of the frequency flip module, and the second end of the fifth transistor serves as the second end of the control module.

6. The GDL circuit according to claim 5, characterized in that: The output module comprises: A sixth transistor, wherein the control end of the sixth transistor is connected to the second end of the fifth transistor, the first end of the sixth transistor is connected to the clock signal end, and the second end of the sixth transistor serves as the driving signal output end of the GDL circuit.

7. The GDL circuit according to claim 6, characterized in that: The output module also includes: A seventh transistor, wherein the control end of the seventh transistor is connected to the drive signal output end of the next-stage GDL circuit, the first end of the seventh transistor is connected to the control end of the seventh transistor, and the second end of the seventh transistor is connected to the control end of the sixth transistor.

8. The GDL circuit according to claim 6 or 7, characterized in that: The output module also includes: A bootstrap capacitor, wherein a first end of the bootstrap capacitor is connected to the control end of the sixth transistor, and a second end of the bootstrap capacitor is connected to the second end of the sixth transistor.

9. A driving method, characterized in that: Applied to the GDL circuit according to any one of claims 1 to 8, the driving method comprises: Get the current driving frequency of the display panel; If the current driving frequency is low frequency, the DC power supply terminal is controlled to output a high level, so that the frequency flip module outputs a first level signal; If the current driving frequency is high frequency, the DC power supply end is controlled to output a low level, so that the output stage of the frequency flip module transmits the second level signal in the connection end; The control module controls the output module to output a gate driving signal according to the first level signal or the second level signal.

10. A gate drive circuit, characterized in that: The gate drive circuit comprises: A frequency detection circuit, used to detect the current driving frequency of the display panel; A power supply circuit, connected to the frequency detection circuit, and configured to output a high level or a low level according to a control signal output by the frequency detection circuit; N cascaded GDL circuits according to any one of claims 1 to 8, each GDL circuit is respectively connected to the power circuit and the corresponding scan line in the display panel, and is used to output a corresponding gate drive signal under the action of the power circuit output signal.

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