Method for etching back metal layer
By using two etching methods in the back metal layer etching of semiconductor devices, combined with pulse square wave bias power, the problems of overetching and metal residue are solved, and the reliability and yield of the product are improved.
Patent Information
- Application Number
- CN202510208359.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-05-16
AI Technical Summary
When the prior art etches the metal layer on the back of the semiconductor device, it is easy to cause overetching outside the trench and metal residues in the trench, reducing the reliability of the product.
The dielectric layer is removed by using a two-etching method, the first etching is used to remove the metal layer, and the second etching uses pulse square wave bias power to remove the metal layer, controlling the duty cycle and frequency to avoid overetching and metal residue.
By controlling the etching parameters, the average free path of molecules is improved, ensuring complete removal of the metal layer, avoiding overetching outside the trench and metal residue on the side walls, and improving product reliability and yield.
Smart Images
Figure CN120015624A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a method for etching a back metal layer. Background Art
[0002] In the semiconductor integrated circuit manufacturing industry, memory cell devices and logic devices are usually integrated on the same wafer, and the electrodes of the logic devices are usually led out through the metal layer in the grooves on the back side of the wafer.
[0003] refer to Figure 1 , which shows a cross-sectional schematic diagram of the metal layer on the back of the substrate before etching; Figure 2 , which shows a cross-sectional schematic diagram after etching the metal layer on the back of the substrate. Exemplarily, the substrate 110 is used to form a memory, which includes a memory cell area and a peripheral area, the memory cell area is used to form a memory cell device, and the peripheral area is used to form a logic device. Figure 1 and Figure 2 The cross-sectional view of the logic region is used as an example to illustrate that the substrate 110 has a front side and a back side. The front side is used to form a storage unit device and a logic device. A groove 301 is formed on the back side. A dielectric layer 120 and a metal layer 130 are formed on the back side in sequence from bottom to top. Figure 1 As shown in FIG. 1 , the thickness of the metal layer 130 formed at the bottom of the groove 301 is usually greater than the thickness outside the groove. Therefore, after the dielectric layer 120 and the metal layer 130 are selectively etched, in order to ensure that the metal layer 130 in the groove 301 is completely removed, it is easy to cause over-etching outside the groove 301 (such as Figure 2 ), and there is a certain probability of causing metal residue on the sidewall of the trench 301 ( Figure 2 ), thereby reducing the reliability of the product. Summary of the invention
[0004] The present application provides a method for etching a back metal layer, which can solve the problem that the back metal etching method provided in the related art easily causes over-etching outside the groove and metal residue in the groove. The method comprises:
[0005] A substrate is provided, wherein the substrate has a front side and a back side, and when viewed from a top view, the substrate includes a first region and a second region, wherein the front side of the first region is used to form a storage unit device, the front side of the second region is used to form a logic device, a groove is formed on the back side of the second region, a dielectric layer and a metal layer are sequentially formed on the back side from bottom to top, and the thickness of the metal layer in the groove is greater than the thickness of the metal layer outside the groove;
[0006] Performing a first etching on the target area until the dielectric layer in the target area is removed;
[0007] The target area is etched for the second time until the metal layer in the target area is removed. During the second etching, the bias power supplied is in the form of a pulsed square wave.
[0008] In some embodiments, the metal layer includes a tungsten layer, or a tungsten layer and a titanium nitride layer.
[0009] In some embodiments, the dielectric layer includes a silicon dioxide layer.
[0010] In some embodiments, the first etching and the second etching are performed in a TCP device.
[0011] In some embodiments, during the second etching process, the duty cycle of the pulse square wave is 20% to 50%.
[0012] In some embodiments, during the second etching process, the bias power ranges from 100 watts to 250 watts.
[0013] In some embodiments, during the second etching process, the frequency of the bias power is greater than 100 Hz.
[0014] The technical solution of this application has at least the following advantages:
[0015] The dielectric layer in the target area is removed by the first etching in a conventional manner, plasma is continuously generated, and a pulse mode is used to etch the metal layer in the groove. On the one hand, the duty cycle can be controlled so that most of the etching is in the stage where the bias power is turned off. At this time, the electron density is reduced to the minimum, and the sheath layer near the surface completely collapses, which increases the mean free path of the molecules and allows a large flux of negative ions and neutral particles to reach the bottom to etch the metal layer. At the same time, the etching by-products can stay at the top for protection. On the other hand, the frequency can be controlled so that electrons can still diffuse to the side walls to ensure that there is no metal residue on the side walls, thereby improving the reliability and yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0017] Figure 1 is a schematic cross-sectional view of the metal layer on the back side of the substrate before etching;
[0018] Figure 2 It is a cross-sectional schematic diagram after the metal layer on the back side of the substrate is etched by the etching method provided in the related art;
[0019] Figure 3 is a flow chart of a method for etching a back metal layer provided by an exemplary embodiment of the present application;
[0020] Figure 4 It is a schematic cross-sectional view after the metal layer on the back side of the substrate is etched by the etching method of the back side metal layer provided in the present application. DETAILED DESCRIPTION
[0021] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0022] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0023] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0024] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0025] refer to Figure 3 , which shows a flow chart of a method for etching a back metal layer provided by an exemplary embodiment of the present application, such as Figure 3 As shown, the method includes:
[0026] Step S1, providing a substrate, the substrate having a front side and a back side, and the substrate including a first area and a second area when viewed from a top view, the front side of the first area being used to form a storage unit device, the front side of the second area being used to form a logic device, a groove being formed on the back side of the second area, a dielectric layer and a metal layer being formed in sequence on the back side of the substrate from bottom to top, and the thickness of the metal layer in the groove being greater than the thickness of the metal layer outside the groove.
[0027] Step S2, performing a first etching on the target area until the dielectric layer in the target area is removed.
[0028] Step S3, performing a second etching on the target area until the metal layer in the target area is removed. During the second etching, the bias power supplied is in the form of a pulsed square wave.
[0029] The etching method of the back metal layer provided by the related art adopts a continuous plasma etching mode for etching. During the etching process, positive ions (ion+) and neutral free radicals (neutral) are continuously etched, and the etching polymer is generated to protect the thin film layer (passivate). However, due to the large difference in thickness between the bottom of the back groove and the outer metal layer (usually 1000 angstroms), the thickness of the metal layer is very large. In the etching process, when the metal layer at the bottom of the trench is completely etched, the silicon substrate outside the trench will also be lost a lot, causing silicon damage and serious damage to the device. At the same time, there may be metal residues on the sidewalls.
[0030] In the embodiment of the present application, the first etching and the second etching are both performed in a transformer coupled plasma (TCP) device. The first etching is performed in a conventional continuous plasma etching mode until the dielectric layer in the target area (the target area is larger than the area occupied by the groove and covers the area occupied by the groove) is removed, and the second etching is performed in a pulse mode (the bias power is a pulsed square wave). On the one hand, the duty cycle can be controlled (the duty cycle of the pulsed square wave is preferably 20% to 50%) to make most of the etching in the bias power off stage, at which time the electron density is reduced to the minimum, the sheath layer near the surface completely collapses, and the mean free path of the molecules is increased, so that a large flux of negative ions and neutral particles can reach the bottom of the etched metal layer, and the etching byproducts can stay at the top for protection. On the other hand, the frequency of the bias power can be controlled (preferably greater than 100 Hz) so that the electrons can still diffuse to the side wall to ensure that there is no metal residue on the side wall.
[0031] During the second etching process, the bias power ranges from 100 W to 250 W, the source power ranges from 750 W to 1000 W, and the etching gas used includes nitrogen trifluoride (NF 3 ) and chlorine (Cl 2 ), the pressure is 5 mTorr to 15 mTorr, thereby increasing the molecular mean free path, and etching away the remaining metal layer (which includes a tungsten (W) layer, or a tungsten layer and a titanium nitride (TiN) layer) in one step. Figure 4 As shown, after two etchings, the metal layer 230 and the dielectric layer 220 in the groove 302 on the back side of the substrate 210 are removed, and the substrate 210 outside the groove 302 is not over-etched and no metal layer 230 remains.
[0032] To summarize, in the embodiments of the present application, the dielectric layer of the target area is removed by the first etching in a conventional manner, plasma is continuously generated, and a pulse mode is used when etching the metal layer in the groove. On the one hand, the duty cycle can be controlled so that most of the etching is in the stage where the bias power is turned off. At this time, the electron density is reduced to a minimum, and the sheath layer near the surface completely collapses, thereby increasing the mean free path of the molecules, allowing a large flux of negative ions and neutral particles to reach the bottom to etch the metal layer. At the same time, the etching by-products can stay at the top for protection. On the other hand, the frequency can be controlled so that electrons can still diffuse to the side walls to ensure that there is no metal residue on the side walls, thereby improving the reliability and yield of the product.
[0033] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A method for etching a back metal layer, characterized in that: include: A substrate is provided, wherein the substrate has a front side and a back side, and when viewed from a top view, the substrate includes a first region and a second region, wherein the front side of the first region is used to form a storage unit device, the front side of the second region is used to form a logic device, a groove is formed on the back side of the second region, a dielectric layer and a metal layer are sequentially formed on the back side from bottom to top, and the thickness of the metal layer in the groove is greater than the thickness of the metal layer outside the groove; Performing a first etching on the target area until the dielectric layer in the target area is removed; The target area is etched for the second time until the metal layer in the target area is removed. During the second etching, the bias power supplied is in the form of a pulsed square wave.
2. The method according to claim 1, characterized in that The metal layer includes a tungsten layer, or a tungsten layer and a titanium nitride layer.
3. The method according to claim 2, characterized in that The dielectric layer includes a silicon dioxide layer.
4. The method according to any one of claims 1 to 3, characterized in that: The first etching and the second etching are performed in a TCP device.
5. The method according to claim 4, characterized in that During the second etching process, the duty cycle of the pulse square wave is 20% to 50%.
6. The method according to claim 5, characterized in that During the second etching process, the bias power ranges from 100 watts to 250 watts.
7. The method according to claim 6, characterized in that During the second etching process, the frequency of the bias power is greater than 100 Hz.