Preparation method of metal interconnection structure

Abstract

The invention provides a preparation method of a metal interconnection structure, and the method comprises the steps: carrying out the etching of a low-K dielectric layer and a barrier layer, so as to form a groove and a through hole, at least introducing hydrogen into a process chamber, and enabling the pressure of the process chamber to be 10 <-7 > Pa to 10 <-6 > Pa; and under the atmosphere that the process temperature is 25-90 DEG C, carrying out reaction type pre-cleaning treatment on the semiconductor device after the groove and the through hole are formed. According to the invention, by improving an Aktiveclear (H.) reaction type pre-cleaning treatment process and carrying out reaction type pre-cleaning treatment in an environment with relatively low gas pressure and relatively low process temperature, the situation that vacancies are generated in the reduction process of copper oxide at the bottom of the through hole is reduced or even avoided, so that the contact resistance of the through hole can be prevented from being increased, and the service life of the through hole is prolonged. And meanwhile, the damage to the low-K dielectric layer is also greatly reduced through the reactive pre-cleaning treatment.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a metal interconnection structure. Background Art

[0002] With the development of integrated circuits, the feature size continues to decrease, and the contact resistance (Rc) of the through hole has an increasingly greater impact on the electrical performance of the chip. Lower contact resistance can reduce the power supply voltage drop (IR drop) of circuit interconnections and reduce heat generation, thereby improving the reliability of the through hole, which is of great significance to improving chip performance.

[0003] At present, the main metal interconnect etching process is trench-through hole integrated etching (All in One, AIO ET). In this process, the surface of the metal layer at the bottom of the through hole will be oxidized to produce copper oxide. At the same time, the polymer residue produced by etching can easily lead to open circuit or high resistance of the through hole. Therefore, pre-cleaning treatment (pre-clean) before depositing the diffusion inhibition layer is very important.

[0004] At present, pre-cleaning treatment is mainly divided into physical cleaning and reactive pre-cleaning. Among them, physical cleaning, for example, uses argon ion bombardment to form a semiconductor device after the trench-through hole, but it is easy to cause greater damage to the low-K dielectric layer and is no longer applicable at small technology nodes; reactive pre-cleaning mainly includes: reactive clean (H+) and Aktive™ clean (H·) two reactive pre-treatment methods. Although these two reactive pre-treatment methods reduce the damage to the low-K dielectric layer, they are easy to generate more vacancies on the surface of the metal layer in the process of reducing the copper oxide at the bottom of the through hole, thereby increasing the contact resistance Rc of the through hole. Summary of the invention

[0005] The present application provides a method for preparing a metal interconnect structure, which can solve at least one of the problems that the pre-cleaning treatment after the traditional metal interconnect integrated etching causes significant damage to the low-K dielectric layer, and a large number of vacancies are generated on the surface of the metal layer at the bottom of the through hole, thereby increasing the contact resistance Rc of the through hole.

[0006] The present invention provides a method for preparing a metal interconnect structure, comprising: A semiconductor structure is provided, wherein a metal interconnection layer is formed in the semiconductor structure, a barrier layer and a low-K dielectric layer are sequentially formed on the semiconductor structure, the barrier layer covers the semiconductor structure and the metal interconnection layer, and the low-K dielectric layer covers the barrier layer; Etching the low-K dielectric layer and the barrier layer to form a trench and a through hole, wherein the through hole is located at the bottom of the trench and communicates with the trench; At least hydrogen is introduced into the process chamber to perform a reactive pre-cleaning treatment on the semiconductor device after the groove and the through hole are formed, wherein the process chamber pressure is 10 -7 Pa~10 -6 Pa; process temperature is 25℃~90℃; forming a diffusion suppression layer, wherein the diffusion suppression layer covers the sidewalls and bottom wall of the trench and the sidewalls of the through hole; A metal material layer is formed, wherein the metal material layer fills the through hole and the trench and is connected to the metal interconnection layer to obtain a metal interconnection structure.

[0007] Optionally, in the method for preparing the metal interconnect structure, the step of introducing at least hydrogen into the process chamber and performing a pre-cleaning treatment on the semiconductor device after forming the trench and the through hole comprises: Hydrogen is introduced into the process chamber to perform a reactive pre-cleaning treatment on the semiconductor device after the groove and the through hole are formed. The flow rate of hydrogen is 0-600 sccm. The process chamber pressure is 10 -7 Pa~10 -6 Pa; process temperature is 25℃~90℃; cleaning duration is 0s~30s.

[0008] Optionally, in the method for preparing the metal interconnect structure, the step of introducing at least hydrogen into the process chamber and performing a pre-cleaning treatment on the semiconductor device after forming the trench and the through hole comprises: Hydrogen and helium are introduced into the process chamber to perform a reactive pre-cleaning treatment on the semiconductor device after the groove and the through hole are formed. The ratio of hydrogen to helium is (1:20) to (1:5). The process chamber pressure is 10 -7 Pa~10 -6 Pa; process temperature is 25℃~40℃; cleaning duration is 30s~90s.

[0009] Optionally, in the method for preparing the metal interconnect structure, hydrogen and helium are introduced into the process chamber, and during the process of performing reactive pre-cleaning treatment on the semiconductor device after forming the grooves and the through holes, the flow rate of hydrogen is 20sccm~100sccm, and the flow rate of helium is 250sccm~500sccm.

[0010] Optionally, in the method for preparing the metal interconnect structure, the material of the barrier layer is SiCN.

[0011] Optionally, in the method for preparing the metal interconnect structure, the material of the metal interconnect layer is copper.

[0012] Optionally, in the method for preparing the metal interconnect structure, the metal material layer is made of copper.

[0013] Optionally, in the method for preparing the metal interconnect structure, the diffusion suppression layer includes: a stacked nitride layer and a layer, the nitride layer covers the side walls of the groove and the side walls and bottom walls of the through hole, and the layer covers the nitride layer.

[0014] Optionally, in the method for preparing the metal interconnect structure, the thickness of the diffusion suppression layer is 50 angstroms to 200 angstroms.

[0015] The technical solution of this application has at least the following advantages: In the method for preparing the metal interconnect structure provided in the present application, after etching the low-K dielectric layer and the barrier layer to form the grooves and the through holes, at least hydrogen is introduced into the process chamber and the pressure in the process chamber is 10 -7 Pa~10 -6 Pa; in an atmosphere of a process temperature of 25°C to 90°C, a reactive pre-cleaning treatment is performed on the semiconductor device after the groove and the through hole are formed. The present application improves the Aktive™ clean (H·) reactive pre-cleaning treatment process, and by performing the reactive pre-cleaning treatment under a lower gas pressure and a lower process temperature environment, it is possible to reduce or even avoid the generation of vacancies during the reduction of copper oxide at the bottom of the through hole, thereby avoiding an increase in the through hole contact resistance. At the same time, the reactive pre-cleaning treatment of the present application also greatly reduces the damage to the low-K dielectric layer and improves the reliability of the metal interconnect structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 is a flow chart of a method for preparing a metal interconnect structure according to an embodiment of the present invention; Figure 2-Figure 6 is a schematic diagram of a semiconductor structure in each process step of preparing a metal interconnect structure according to an embodiment of the present invention; The reference numerals are described as follows: 10-semiconductor structure, 11-metal interconnection layer, 12-diffusion suppression layer 1, 20-barrier layer, 30-low-K dielectric layer, 31-groove, 32-through hole, 40-diffusion suppression layer 2, 50-metal material layer. DETAILED DESCRIPTION

[0018] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0020] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0021] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0022] The present invention provides a method for preparing a metal interconnect structure. Figure 1 , Figure 1 1 is a flow chart of a method for preparing a metal interconnect structure according to an embodiment of the present invention. The method for preparing a metal interconnect structure includes: First, perform step S1: refer to Figure 2 , Figure 2 It is a schematic diagram of a semiconductor structure after a low-K dielectric layer is formed according to an embodiment of the present application. A semiconductor structure 10 is provided, in which a metal interconnection layer 11 is formed, and a barrier layer 20 and a low-K dielectric layer 30 are sequentially formed on the semiconductor structure 10, wherein the barrier layer 20 covers the semiconductor structure 10 and the metal interconnection layer 11, and the low-K dielectric layer 30 covers the barrier layer 20.

[0023] Furthermore, a diffusion suppression layer 12 may be formed between the semiconductor structure 10 and the metal interconnection layer 11 .

[0024] In this embodiment, the diffusion suppression layer 12 includes: a stacked tank layer 1 and a tank layer 2, wherein the tank layer 1 covers the sidewalls of the opening, and the tank layer 1 covers the tank layer 1.

[0025] In this embodiment, the metal interconnection layer 11 is made of copper.

[0026] Preferably, the barrier layer 20 is made of SiCN.

[0027] Then, execute step S2: refer to Figure 3 , Figure 3 It is a schematic diagram of the semiconductor structure after the grooves and through-holes are formed in an embodiment of the present application. The low-K dielectric layer 30 and the barrier layer 20 are etched to the surface of the metal interconnection layer 11 through an integrated etching process to form the groove 31 and the through-hole 32. The through-hole 32 is located at the bottom of the groove 31 and is connected to the groove 31.

[0028] In other embodiments, the low-K dielectric layer 30 , the barrier layer 20 and a partial thickness of the metal interconnect layer 11 may be etched by an integrated etching process to form a groove 31 and a through hole 32 , wherein the through hole 32 is located at the bottom of the groove 31 and is connected to the groove 31 .

[0029] It is worth noting that after etching the low-K dielectric layer 30 and the barrier layer 20 to form the trench 31 and the through hole 32 , the surface of the metal interconnection layer 11 at the bottom of the through hole 32 will inevitably be oxidized.

[0030] In this embodiment, the surface of the metal interconnection layer 11 at the bottom of the through hole 32 will inevitably be oxidized, thereby forming copper oxide.

[0031] Next, step S3 is performed: at least hydrogen is introduced into the process chamber to perform a reactive pre-cleaning treatment on the semiconductor device after the groove and the through hole are formed, wherein the process chamber pressure is 10 -7 Pa~10 -6 Pa; process temperature is 25℃~90℃.

[0032] In this embodiment, step S3 is: hydrogen is introduced into the process chamber to perform a reactive pre-cleaning treatment on the semiconductor device after the groove and the through hole are formed, and the flow rate of hydrogen is 0 sccm~600 sccm; the process chamber pressure is 10 -7 Pa~10 -6Pa; process temperature is 25℃~90℃; cleaning duration is 0s~30s.

[0033] In another embodiment, step S3 is: introducing hydrogen and helium into the process chamber to perform a reactive pre-cleaning treatment on the semiconductor device after the groove and the through hole are formed, wherein the ratio of hydrogen to helium is (1:20) to (1:5); the process chamber pressure is 10 -7 Pa~10 -6 Pa; the process temperature is 25°C to 40°C; the cleaning duration is 30s to 90s. Preferably, hydrogen and helium are introduced into the process chamber, and during the process of performing a reactive pre-cleaning treatment on the semiconductor device after the grooves and the through holes are formed, the flow rate of hydrogen is 20sccm to 100sccm, and the flow rate of helium is 250sccm to 500sccm.

[0034] Further, step S4 is performed: refer to Figure 4 , Figure 4 It is a schematic diagram of the semiconductor structure after forming the second diffusion suppression layer according to an embodiment of the present application, wherein the second diffusion suppression layer 40 is formed, and the second diffusion suppression layer 40 covers the sidewalls and the bottom wall of the trench 31 and the sidewalls of the through hole 32 .

[0035] Preferably, the diffusion suppression layer 40 comprises: a stacked nitride layer 2 and a layer 3, wherein the nitride layer 2 covers the sidewalls of the trench 31 and the sidewalls and bottom wall of the through hole 32, and the layer 3 covers the nitride layer 3.

[0036] Preferably, the second diffusion suppression layer 40 has a thickness of 50 angstroms to 200 angstroms.

[0037] Finally, execute step S5: reference Figure 5 and Figure 6 , Figure 5 is a schematic diagram of a semiconductor structure after a metal material layer is formed in an embodiment of the present application, Figure 6 It is a schematic diagram of the semiconductor structure after the metal material layer and the diffusion inhibition layer 2 that exceed the surface of the low-K dielectric layer are polished and removed according to an embodiment of the present application, to form a metal material layer 50, wherein the metal material layer 50 fills the through hole 32 and the groove 31, and the metal material layer 50 is connected to the metal interconnection layer 11 to obtain a metal interconnection structure.

[0038] Specifically, the steps of forming the metal interconnect structure include: Figure 5 As shown, a metal material layer 50 is formed, the metal material layer 50 fills the through hole 32 and the groove 31 and covers the diffusion suppression layer 2 40, wherein the metal material layer 50 is connected to the metal interconnection layer 11; further, as Figure 6As described above, the metal material layer 50 and the second diffusion suppression layer 40 that extend beyond the surface of the low-K dielectric layer 30 are polished and removed by a chemical mechanical polishing process to obtain a metal interconnection structure.

[0039] In this embodiment, the metal material layer 50 is made of copper.

[0040] In the present application, by improving the Aktive™ clean (H·) reactive pre-cleaning process and performing the reactive pre-cleaning process under a relatively low gas pressure and a relatively low process temperature, the generation of vacancies during the reduction of copper oxide at the bottom of the through hole can be reduced or even avoided, thereby avoiding an increase in the through hole contact resistance. At the same time, the reactive pre-cleaning process of the present application also greatly reduces the damage to the low-K dielectric layer and improves the reliability of the metal interconnect structure.

[0041] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing a metal interconnect structure, characterized in that: include: A semiconductor structure is provided, wherein a metal interconnection layer is formed in the semiconductor structure, a barrier layer and a low-K dielectric layer are sequentially formed on the semiconductor structure, the barrier layer covers the semiconductor structure and the metal interconnection layer, and the low-K dielectric layer covers the barrier layer; Etching the low-K dielectric layer and the barrier layer to form a trench and a through hole, wherein the through hole is located at the bottom of the trench and communicates with the trench; At least hydrogen is introduced into the process chamber to perform a reactive pre-cleaning treatment on the semiconductor device after the groove and the through hole are formed, wherein the process chamber pressure is 10 -7 Pa~10 -6 Pa; process temperature is 25℃~90℃; forming a diffusion suppression layer, wherein the diffusion suppression layer covers the sidewalls and bottom wall of the trench and the sidewalls of the through hole; A metal material layer is formed, wherein the metal material layer fills the through hole and the trench and is connected to the metal interconnection layer to obtain a metal interconnection structure.

2. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The step of introducing at least hydrogen into the process chamber and performing a pre-cleaning treatment on the semiconductor device after the groove and the through hole are formed comprises: Hydrogen is introduced into the process chamber to perform a reactive pre-cleaning treatment on the semiconductor device after the groove and the through hole are formed. The flow rate of hydrogen is 0 sccm to 600 sccm. The process chamber pressure is 10 -7 Pa~10 -6 Pa; process temperature is 25℃~90℃; cleaning duration is 0s~30s.

3. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The step of introducing at least hydrogen into the process chamber and performing a pre-cleaning treatment on the semiconductor device after the groove and the through hole are formed comprises: Hydrogen and helium are introduced into the process chamber to perform a reactive pre-cleaning treatment on the semiconductor device after the groove and the through hole are formed. The ratio of hydrogen to helium is (1:20) to (1:5). The process chamber pressure is 10 -7 Pa~10 -6 Pa; process temperature is 25℃~40℃; cleaning duration is 30s~90s.

4. The method for preparing a metal interconnection structure according to claim 3, characterized in that: Hydrogen and helium are introduced into the process chamber to perform a reactive pre-cleaning treatment on the semiconductor device after the grooves and the through holes are formed. The flow rate of hydrogen is 20 sccm-100 sccm, and the flow rate of helium is 250 sccm-500 sccm.

5. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The material of the barrier layer is SiCN.

6. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The material of the metal interconnection layer is copper.

7. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The material of the metal material layer is copper.

8. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The diffusion suppression layer includes: a stacked tank layer and a tank layer, the tank layer covers the sidewalls of the trench and the sidewalls and bottom wall of the through hole, and the tank layer covers the tank layer.

9. The method for preparing a metal interconnect structure according to claim 1, characterized in that: The diffusion suppression layer has a thickness of 50 angstroms to 200 angstroms.

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