A double-sided packaging structure for low parasitic inductance of a power device

Abstract

The present invention discloses a double-sided packaging structure for a power device with low parasitic inductance. By respectively arranging a plurality of conductor layers, vias and metal layers on the upper surface and the lower surface of the first insulating layer, the parasitic inductance of the double-sided packaging structure is reduced, enabling the traces on the ceramic substrate to be stacked, thereby further reducing the parasitic inductance. Different from the traditional DBC ceramic substrate where only the upper-layer conductor participates in conduction, the inner conductor layer of the multi-layer insulating layer can also participate in conduction and is connected to the upper-layer conductor through vias. The double-sided packaging structure is double-sidedly connected to the power device chip. In the case of realizing the parallel connection of multiple devices, both sides can be connected to the heat sink, greatly increasing the heat dissipation of the power device chip, thereby improving the working reliability of the double-sided packaging structure.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor chip packaging processes, and particularly relates to a double-sided packaging structure with low parasitic inductance for power devices. Background Art

[0002] Power electronic devices are developing towards modularization and intelligentization. The emergence of large-scale and very large-scale integrated circuits has led to higher and higher integration levels of power electronic devices, and the number and density of various chips assembled on the substrate are also increasing. To reduce the volume of power electronic modules and further improve the power density, it is required that the power module has good electrical, thermal performance and working reliability under both steady-state and transient conditions. All these lead to the chips suffering more and more high temperatures or temperature drifts during use. High temperature has a great impact on the reliability and rapid aging of power electronic products, and excessive temperature and temperature cycling often directly lead to premature failure of the products. Therefore, effective thermal management has become a major challenge for the future development of power electronics, and higher requirements are put forward for the research and development and progress of packaging technologies and packaging materials.

[0003] The traditional power electronic packaging form is as follows Figure 1 As shown, the power device chip is directly welded to the DBC substrate (copper-clad ceramic substrate), and then the DBC substrate with the chip attached is connected to the heat sink. This packaging form is called single-sided packaging. The heat dissipation channel of single-sided packaging is mainly that the heat generated by the chip is transferred to the DBC board through the adhesive layer, and then transferred to the heat sink through another adhesive layer. Finally, the heat sink dissipates heat through convection with air or water cooling. In the single-sided cooling packaging form, the heat transfer direction is unidirectional from the chip to the heat sink. Although connection materials with higher thermal conductivity or heat sinks with better heat dissipation capabilities can be used to increase the overall heat dissipation capacity of the structure, the improvement space is still very limited. Today, in the pursuit of greater power input and packaging density, the single-sided cooling packaging form can no longer meet the needs of high-power electronic packaging. Therefore, a double-sided cooling packaging technology has emerged. Usually, the double-sided cooling device form is a symmetric structure as follows Figure 2 As shown, the chip is welded between the upper and lower DBC substrates, and the upper and lower DBC boards are respectively connected to the heat sink through connection materials.

[0004] The parasitic inductance inside the module is an important indicator for the packaging design of power modules. When the power semiconductor device is turned off, the energy stored in the parasitic inductance will cause voltage spikes and oscillations, and may increase losses. Therefore, in order to ensure the performance and safe operation of power devices and power electronic systems, attention should be paid to reducing the packaging parasitic inductance during the packaging design of power modules. Therefore, there is an urgent need to provide a double-sided packaging structure with low parasitic inductance for power devices to solve the above-mentioned existing technical problems. Summary of the Invention

[0005] In view of this, the present invention provides a double-sided packaging structure for a power device with low parasitic inductance, which uses a multi-layer ceramic substrate, enabling the traces on the ceramic substrate to be stacked, thereby further reducing the parasitic inductance. Different from the traditional DBC ceramic substrate where only the upper conductor participates in conduction, the inner conductor of the multi-layer ceramic substrate can also participate in conduction and is connected to the upper conductor through vias. The following specific technical solutions are adopted to achieve this.

[0006] The present invention provides a double-sided packaging structure for a power device with low parasitic inductance, and the double-sided packaging structure includes:

[0007] A first insulating layer;

[0008] A first conductor layer formed on the upper surface of the first insulating layer, a second insulating layer arranged at intervals on the upper surface of the first conductor layer, and a first via located between the second insulating layers;

[0009] A second conductor layer filled in the first via and a third conductor layer located on the upper surface of the second insulating layer;

[0010] A first metal layer formed on the upper surface of the second conductor layer, a second metal layer on one side of the third conductor layer, and a first power device chip on the other side of the third conductor layer. The first power device chip is connected to the second conductor layer through a first metal wire;

[0011] A fourth conductor layer formed on the lower surface of the first insulating layer, a third insulating layer arranged at intervals on the lower surface of the fourth conductor layer, and a second via located between the third insulating layers and corresponding to the first via;

[0012] A fifth conductor layer filled in the second via and a sixth conductor layer located on the lower surface of the third insulating layer and corresponding to the third conductor layer;

[0013] A third metal layer formed on the lower surface of the fifth conductor layer, a fourth metal layer on one side of the sixth conductor layer, and a second power device chip on the other side of the sixth conductor layer. The second power device chip is connected to the fifth conductor layer through a second metal wire.

[0014] As a preference of the above technical solution, the projected area of the third conductor layer on the first insulating layer is smaller than the projected area of the second insulating layer on the first insulating layer, and the projected area of the sixth conductor layer on the first insulating layer is smaller than the projected area of the third insulating layer on the first insulating layer.

[0015] As a preference of the above technical solution, the thicknesses of the first conductor layer, the third conductor layer, the fourth conductor layer, and the sixth conductor layer are between 0.1 and 0.5 mm.

[0016] Preferably, as the above technical solution, the thicknesses of the first insulating layer, the second insulating layer, and the third insulating layer are between 0.2 and 1 mm.

[0017] Preferably, as the above technical solution, the first metal layer, the second metal layer, and the first power device chip are flush, and the third metal layer, the fourth metal layer, and the second power device chip are flush.

[0018] Preferably, as the above technical solution, the double-sided packaging structure further includes:

[0019] A first heat dissipation component, which includes a first heat sink, a first adhesion layer, and a first DBC substrate stacked in sequence. The first DBC substrate is close to the first power device chip, and the first heat sink is far from the first power device chip;

[0020] A second heat dissipation component, which includes a second DBC substrate, a second adhesion layer, and a second heat sink stacked in sequence. The second DBC substrate is close to the second power device chip, and the second heat sink is far from the second power device chip.

[0021] Preferably, as the above technical solution, when a first current with a first current density is input to the first metal layer, the first current sequentially passes through the second conductor layer, the first conductor layer, the second conductor layer, the first metal connection, the first power device chip, the third conductor layer, and the second metal layer to form a first current branch;

[0022] When a second current with a second current density is input to the fourth metal layer, the second current sequentially passes through the sixth conductor layer, the second power device chip, the second metal connection, the fifth conductor layer, and the third metal layer to form a second current branch. The first current density is the same as the second current density, and the currents of the first current branch and the second current branch are equal and opposite in direction.

[0023] Preferably, as the above technical solution, the first insulating layer, the second insulating layer, and the third insulating layer are all insulating ceramics, and the materials of the first conductor layer, the second conductor layer, the third conductor layer, the fourth conductor layer, the fifth conductor layer, and the sixth conductor layer are all copper.

[0024] Preferably, as the above technical solution, the preparation process of the double-sided packaging structure includes:

[0025] Providing a first insulating layer, and growing a first conductor layer and a fourth conductor layer on the upper surface and the lower surface of the first insulating layer respectively;

[0026] Etch the first conductor layer and the fourth conductor layer to fabricate completely mirror-image current paths;

[0027] Form a second insulating layer on the upper surface of the first conductor layer and a third insulating layer on the lower surface of the fourth conductor layer;

[0028] Etch via holes on both sides of the insulating ceramic, and etch the second insulating layer and the third insulating layer respectively to form a first via hole and a second via hole;

[0029] Fill the first via hole with a second conductor layer and form a third conductor layer on the upper surface of the second insulating layer, and fill the second via hole with a fifth conductor layer and form a sixth conductor layer corresponding to the third conductor layer on the lower surface of the third insulating layer;

[0030] Bond a first power device chip to one side of the third conductor layer and bond a second power device chip to one side of the sixth conductor layer;

[0031] Form a first metal layer on the upper surface of the second conductor layer, form a second metal layer on the other side of the third conductor layer, form a third metal layer on the lower surface of the fifth conductor layer, and form a fourth metal layer on the other side of the sixth conductor layer. The first power device chip is connected to the second conductor layer through a first metal connection, and the second power device chip is connected to the fifth conductor layer through a second metal connection.

[0032] As a preference of the above technical solution, perform double-sided DBC coverage to form a first heat dissipation component above the first power device chip and a second heat dissipation component below the second power device chip. The first heat dissipation component and the second heat dissipation component are symmetrically arranged with respect to the first insulating layer.

[0033] The present invention provides a low-parasitic inductance double-sided packaging structure for power devices. By respectively arranging a plurality of conductor layers, via holes and metal layers on the upper surface and the lower surface of the first insulating layer, the parasitic inductance of the double-sided packaging structure is reduced, enabling the traces on the ceramic substrate to be stacked, thereby further reducing the parasitic inductance. Different from the traditional DBC ceramic substrate where only the upper-layer conductor participates in conduction, the inner-layer conductor layers of the multi-layer insulating layers can also participate in conduction and are connected to the upper-layer conductors through via holes. The double-sided packaging structure is double-sidedly connected to the power device chips. In the case of realizing the parallel connection of multiple devices, both sides can be connected to the heat sink, greatly increasing the heat dissipation of the power device chips and improving the working reliability of the double-sided packaging structure. Description of the Drawings

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0035] Figure 1 Schematic diagram of the structure of a prior art power electronic packaging form;

[0036] Figure 2 Schematic diagram of the structure of a prior art double-sided cooling device form;

[0037] Figure 3 Schematic diagram of the double-sided packaging structure provided by the present invention;

[0038] Figure 4 Schematic diagram of the working current of the double-sided packaging structure provided by the present invention;

[0039] Figure 5 Schematic diagram of the structures of the first heat dissipation component and the second heat dissipation component provided by the present invention;

[0040] Figure 6 Flowchart of the preparation method of the double-sided packaging structure provided by the present invention.

[0041] The main component symbols are explained as follows:

[0042] 1 - Power device chip; 2 - DBC substrate; 3 - Heat sink; 4 - Adhesive layer; 10 - First insulating layer; 11 - First conductor layer; 12 - Second insulating layer; 13 - First via; 14 - Second conductor layer; 15 - Third conductor layer; 16 - First metal layer; 17 - Second metal layer; 18 - First power device chip; 19 - First metal connection; 20 - Fourth conductor layer; 21 - Third insulating layer; 22 - Second via; 23 - Fifth conductor layer; 24 - Sixth conductor layer; 25 - Third metal layer; 26 - Fourth metal layer; 27 - Second power device chip; 28 - Second metal connection; 30 - First heat sink; 31 - First adhesive layer; 32 - First DBC substrate; 34 - Second DBC substrate; 35 - Second adhesive layer; 36 - Second heat sink. Detailed implementation manners

[0043] The following will describe in detail the embodiments of the present invention. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions from beginning to end. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation of the present invention.

[0044] It should be noted that when an element is referred to as "fixed to" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. On the contrary, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for illustrative purposes.

[0045] In the present invention, unless otherwise clearly defined and limited, terms such as "installed", "connected", "connected to", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] Referring to Figure 3 , the present invention provides a double-sided packaging structure for a power device with low parasitic inductance. The double-sided packaging structure includes:

[0047] A first insulating layer 10;

[0048] A first conductor layer 11 formed on the upper surface of the first insulating layer 10, a second insulating layer 12 arranged at intervals on the upper surface of the first conductor layer 11, and a first via 13 located between the second insulating layers 12;

[0049] A second conductor layer 14 filled in the first via 13 and a third conductor layer 15 located on the upper surface of the second insulating layer 12;

[0050] A first metal layer 16 formed on the upper surface of the second conductor layer 14, a second metal layer 17 on one side of the third conductor layer 15, and a first power device chip 18 on the other side of the third conductor layer 15. The first power device chip 18 is connected to the second conductor layer 14 through a first metal wire 19;

[0051] A fourth conductor layer 20 formed on the lower surface of the first insulating layer 10, a third insulating layer 21 arranged at intervals on the lower surface of the fourth conductor layer 20, and a second via 22 located between the third insulating layers 21 and corresponding to the first via 13;

[0052] A fifth conductor layer 23 filled in the second via 22 and a sixth conductor layer 24 located on the lower surface of the third insulating layer 21 and corresponding to the third conductor layer 15;

[0053] A third metal layer 25 formed on the lower surface of the fifth conductor layer 23, a fourth metal layer 26 on one side of the sixth conductor layer 24, and a second power device chip 27 on the other side of the sixth conductor layer 24, wherein the second power device chip 27 is connected to the fifth conductor layer 23 through a second metal connection line 28.

[0054] In this embodiment, the projected area of the third conductor layer 15 on the first insulating layer 10 is smaller than the projected area of the second insulating layer 12 on the first insulating layer 10, and the projected area of the sixth conductor layer 24 on the first insulating layer 10 is smaller than the projected area of the third insulating layer 21 on the first insulating layer 10. The thicknesses of the first conductor layer 11, the third conductor layer 15, the fourth conductor layer 20, and the sixth conductor layer 24 are between 0.1 and 0.5 mm, the thicknesses of the first insulating layer 10, the second insulating layer 12, and the third insulating layer 21 are between 0.2 and 1 mm, the first metal layer 16, the second metal layer 17, and the first power device chip 18 are flush, and the third metal layer 25, the fourth metal layer 26, and the second power device chip 27 are flush. The double-sided packaging structure further includes: a first heat dissipation component, which includes a first heat sink 30, a first adhesion layer 31, and a first DBC substrate 32 stacked in sequence, the first DBC substrate 32 is close to the first power device chip 18, and the first heat sink 30 is far from the first power device chip 18; a second heat dissipation component, which includes a second DBC substrate 34, a second adhesion layer 35, and a second heat sink 36 stacked in sequence, the second DBC substrate 34 is close to the second power device chip 27, and the second heat sink 36 is far from the second power device chip 27.

[0055] It should be noted that when the first current with a first current density is input to the first metal layer 16, the first current successively passes through the second conductor layer 14, the first conductor layer 11, the second conductor layer 14, the first metal connection 19, the first power device chip 18, the third conductor layer 15, and the second metal layer 17 to form a first current branch; when the second current with a second current density is input to the fourth metal layer 26, the second current successively passes through the sixth conductor layer 24, the second power device chip 27, the second metal connection 28, the fifth conductor layer, and the third metal layer to form a second current branch. The first current density is the same as the second current density, and the currents of the first current branch and the second current branch are equal and opposite in direction. The first insulating layer, the second insulating layer, and the third insulating layer are all insulating ceramics, and the materials of the first conductor layer 11, the second conductor layer 14, the third conductor layer 15, the fourth conductor layer 20, the fifth conductor layer 23, and the sixth conductor layer 24 are all copper. Preferably, the thicknesses of the first conductor layer 11, the third conductor layer 15, the fourth conductor layer 20, and the sixth conductor layer 24 are equal, the thicknesses of the first insulating layer 10, the second insulating layer 12, and the third insulating layer 21 are equal, and the thicknesses of the second conductor layer 14 and the fifth conductor layer 23 are equal, which can improve the working stability of the double-sided packaging structure.

[0056] It should be understood that referring again to Figure 2, with the switching speed of power semiconductor devices becoming faster and faster in recent years, the problem of parasitic inductance in packaging has become more prominent. In traditional power modules, the parasitic inductance of packaging mainly consists of the following parts: (1) the current loop on the DBC; (2) the bonding wires on the upper surface of the chip; (3) the power connection terminals. To reduce the parasitic inductance of packaging, there are mainly the following three methods: 1) reducing the parasitic inductance of DBC traces through DBC layout design; 2) reducing the parasitic inductance of terminals through the design of connection terminals; 3) adopting a new connection method to replace the bonding wires on the chip surface to reduce the parasitic inductance introduced by the bonding wires. The main purpose of the lower-layer conduction of the traditional DBC (ceramic) substrate 2 is to facilitate the design of traces, that is, the metal layer and metal connections, to facilitate the control of the trace current and direction, thereby reducing the parasitic inductance and also reducing the resistance. And the present invention adopts an improved double-sided packaging structure to further reduce the parasitic inductance of the module packaging. By using a multi-layer ceramic substrate, the traces on the ceramic substrate can also be stacked, thereby further reducing the parasitic inductance. Different from the traditional DBC ceramic substrate where only the upper-layer conductor participates in conduction, the inner-layer conductors (the first conductor layer, the fourth conductor layer) of the multi-layer ceramic substrate can also participate in conduction and are connected to the upper-layer conductors (the third conductor layer, the sixth conductor layer) through vias. Since the thickness of the ceramic substrate is small, the loop area is small, thus reducing the parasitic inductance. In other words, by respectively arranging a plurality of conductor layers, vias and metal layers on the upper surface and the lower surface of the first insulating layer 10, the parasitic inductance of the double-sided packaging structure is reduced, enabling the traces on the ceramic substrate to be stacked, thereby further reducing the parasitic inductance. Different from the traditional DBC ceramic substrate where only the upper-layer conductor participates in conduction, the inner-layer conductor layers of the multi-layer insulating layer can also participate in conduction and are connected to the upper-layer conductors through vias. The double-sided packaging structure is double-sidedly connected to the power device chip. In the case of realizing the parallel connection of multiple devices, both sides can be connected to the heat sink, greatly increasing the heat dissipation of the power device chip and improving the working reliability of the double-sided packaging structure.

[0057] Specifically, the first power device chip 18 and the second power device chip 27 adopt vertical power device chips and are double-sided packaged on a new multi-layer insulating layer (ceramic substrate). The sizes of the first via 13 and the second via 22 can be made as large as possible based on the ceramic substrate to reduce the via resistance. The materials of the first metal layer 16, the second metal layer 17, the third metal layer 25, and the fourth metal layer 26 are copper. Copper has a low internal resistance and can be directly bonded to the DBC. The first metal connection 19 and the second metal connection 28 can be connected to the gate leads of the first power device chip 18 and the second power device chip 27, or can be the electrode leads of the control circuit part. The material of the conductor layer is preferably a material with good thermal conductivity. The heights of the first metal layer 16, the second metal layer 17, the third metal layer 25, and the fourth metal layer 26 are close to the thickness of the first power device chip 18 or the second power device chip 27. The edges of the first metal layer 16, the second metal layer 17, the third metal layer 25, and the fourth metal layer 26 cover the first DBC substrate 32 or the second DBC substrate 34 (DBC layer).

[0058] Specifically, the power device chips on the front side (the upper surface of the first insulating layer 10) and the back side (the lower surface of the first insulating layer 10) are connected in parallel, and the working current is shown as Figure 4 shown. For opposite current directions and the same current density, the package parasitic inductance can be significantly reduced. Because theoretically, the magnetic field between the traces with equal and opposite currents can be weakened, and the parasitic inductance can be cancelled out. That is, the currents in the first current branch (input from the light arrow to output from the dark arrow) and the second current branch (input from the dark arrow to output from the light arrow) are equal and opposite, which can reduce the parasitic inductance of the double-sided package structure. In other words, when multiple conductor layers and insulating layers are stacked in an interleaved manner, multi-layer wiring can be realized and it is convenient for routing, and the magnitude and direction of the current in the traces can be controlled to eliminate the parasitic inductance. In addition, as Figure 5 shown, after filling the insulating plastic on the front side and the back side according to actual application needs, heat sinks can be added to the double-sided package structure, which improves the heat dissipation performance of the power device chips after packaging.

[0059] Refer to Figure 6 , optionally, the preparation process of the double-sided package structure includes:

[0060] S1: Provide the first insulating layer 10, and grow the first conductor layer 11 and the fourth conductor layer 20 on the upper surface and the lower surface of the first insulating layer 10 respectively;

[0061] S2: Etch the first conductor layer 11 and the fourth conductor layer 20 to fabricate completely mirror-image current paths;

[0062] S3: Form the second insulating layer 12 on the upper surface of the first conductor layer 11 and form the third insulating layer 21 on the lower surface of the fourth conductor layer 20;

[0063] S4: Double-sided etching of vias on the insulating ceramic, etching the second insulating layer 12 and the third insulating layer 21 respectively to form a first via 13 and a second via 22;

[0064] S5: Fill the first via 13 with a second conductor layer 14 and form a third conductor layer 15 on the upper surface of the second insulating layer 12, and fill the second via 22 with a fifth conductor layer 23 and form a sixth conductor layer 24 corresponding to the third conductor layer 15 on the lower surface of the third insulating layer 21;

[0065] S6: Bond a first power device chip 18 to one side of the third conductor layer 15 and bond a second power device chip 27 to one side of the sixth conductor layer 24;

[0066] S7: Form a first metal layer 16 on the upper surface of the second conductor layer 14, form a second metal layer 17 on the other side of the third conductor layer 15, form a third metal layer 25 on the lower surface of the fifth conductor layer 23, and form a fourth metal layer 26 on the other side of the sixth conductor layer 24. The first power device chip 18 is connected to the second conductor layer 14 through a first metal wire 19, and the second power device chip 27 is connected to the fifth conductor layer 23 through a second metal wire 28.

[0067] In this embodiment, double-sided DBC coverage is performed to form a first heat dissipation component above the first power device chip 18 and a second heat dissipation component below the second power device chip 27. The first heat dissipation component and the second heat dissipation component are symmetrically arranged with respect to the first insulating layer 10. The preparation process of the double-sided packaging structure includes: growing conductor layers on both sides of the central insulating ceramic; etching the front and back conductor layers to fabricate completely mirror-image current paths; filling the double-sided coverage with insulating ceramic; double-sided etching of vias on the insulating ceramic; fabricating the double-sided coverage of conductor layers and etching the conductor layers on both sides; high-temperature melting; bonding of power device chips; fabrication of metal leads (metal layers) and metal wires; double-sided DBC coverage.

[0068] In all the examples shown and described here, any specific value should be construed as merely exemplary and not as a limitation. Therefore, other examples of the exemplary embodiments may have different values.

[0069] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0070] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all fall within the protection scope of the present invention.

Claims

1. A double-sided packaging structure for a power device with low parasitic inductance, characterized in that, The double-sided packaging structure includes: A first insulating layer; A first conductor layer formed on the upper surface of the first insulating layer, a second insulating layer arranged at intervals on the upper surface of the first conductor layer, and a first via hole located between the second insulating layers; A second conductor layer filled in the first via hole and a third conductor layer located on the upper surface of the second insulating layer; A first metal layer formed on the upper surface of the second conductor layer, a second metal layer on one side of the third conductor layer, and a first power device chip on the other side of the third conductor layer. The first power device chip is connected to the second conductor layer through a first metal wire; A fourth conductor layer formed on the lower surface of the first insulating layer, a third insulating layer arranged at intervals on the lower surface of the fourth conductor layer, and a second via hole located between the third insulating layers and corresponding to the first via hole; A fifth conductor layer filled in the second via hole and a sixth conductor layer located on the lower surface of the third insulating layer and corresponding to the third conductor layer; A third metal layer formed on the lower surface of the fifth conductor layer, a fourth metal layer on one side of the sixth conductor layer, and a second power device chip on the other side of the sixth conductor layer. The second power device chip is connected to the fifth conductor layer through a second metal wire; The projected area of the third conductor layer on the first insulating layer is smaller than the projected area of the second insulating layer on the first insulating layer, and the projected area of the sixth conductor layer on the first insulating layer is smaller than the projected area of the third insulating layer on the first insulating layer.

2. The double-sided packaging structure for a power device with low parasitic inductance according to claim 1, wherein The thicknesses of the first conductor layer, the third conductor layer, the fourth conductor layer, and the sixth conductor layer are between 0.1 and 0.5 mm.

3. The double-sided packaging structure for a power device with low parasitic inductance according to claim 1, characterized in that, The thicknesses of the first insulating layer, the second insulating layer, and the third insulating layer are between 0.2 and 1 mm.

4. The double-sided packaging structure for a power device with low parasitic inductance according to claim 1, characterized in that, The first metal layer, the second metal layer, and the first power device chip are flush, and the third metal layer, the fourth metal layer, and the second power device chip are flush.

5. The double-sided packaging structure for a power device with low parasitic inductance according to claim 1, characterized in that, The double-sided packaging structure further includes: A first heat dissipation component, which includes a first heat sink, a first adhesion layer, and a first DBC substrate stacked in sequence. The first DBC substrate is close to the first power device chip, and the first heat sink is far from the first power device chip; A second heat dissipation component, which includes a second DBC substrate, a second adhesion layer, and a second heat sink stacked in sequence. The second DBC substrate is close to the second power device chip, and the second heat sink is far from the second power device chip.

6. The double-sided packaging structure for a power device with low parasitic inductance according to claim 1, characterized in that, When a first current with a first current density is input to the first metal layer, the first current sequentially passes through the second conductor layer, the first conductor layer, the second conductor layer, the first metal wire, the first power device chip, the third conductor layer, and the second metal layer to form a first current branch; When a second current with a second current density is input to the fourth metal layer, the second current sequentially passes through the sixth conductor layer, the second power device chip, the second metal connection, the fifth conductor layer, and the third metal layer to form a second current branch. The first current density is the same as the second current density, and the currents in the first current branch and the second current branch are equal and opposite in direction.

7. The dual-sided packaging structure for a power device with low parasitic inductance according to claim 1, characterized in that, The first insulating layer, the second insulating layer, and the third insulating layer are all insulating ceramics, and the materials of the first conductor layer, the second conductor layer, the third conductor layer, the fourth conductor layer, the fifth conductor layer, and the sixth conductor layer are all copper.

8. The double-sided packaging structure for a power device with low parasitic inductance according to claim 1, characterized in that, The preparation process of the double-sided packaging structure includes: Providing a first insulating layer, and growing a first conductor layer and a fourth conductor layer on the upper surface and the lower surface of the first insulating layer respectively; Etching the first conductor layer and the fourth conductor layer to fabricate a completely mirror-image current path; Forming a second insulating layer on the upper surface of the first conductor layer and forming a third insulating layer on the lower surface of the fourth conductor layer; Double-sided etching vias in the insulating ceramic, and etching the second insulating layer and the third insulating layer respectively to form a first via and a second via; Filling a second conductor layer in the first via and forming a third conductor layer on the upper surface of the second insulating layer, and filling a fifth conductor layer in the second via and forming a sixth conductor layer corresponding to the third conductor layer on the lower surface of the third insulating layer; Bonding a first power device chip on one side of the third conductor layer and bonding a second power device chip on one side of the sixth conductor layer; Forming a first metal layer on the upper surface of the second conductor layer, forming a second metal layer on the other side of the third conductor layer, forming a third metal layer on the lower surface of the fifth conductor layer, and forming a fourth metal layer on the other side of the sixth conductor layer. The first power device chip is connected to the second conductor layer through a first metal connection, and the second power device chip is connected to the fifth conductor layer through a second metal connection.

9. The double-sided packaging structure for a power device with low parasitic inductance according to claim 1, characterized in that, It further includes: Double-sided DBC coverage to form a first heat dissipation component above the first power device chip and a second heat dissipation component below the second power device chip. The first heat dissipation component and the second heat dissipation component are symmetrically arranged with respect to the first insulating layer.

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