Flip chip quad flat no-lead (QFN) package

Abstract

The invention relates to a flip-chip quad flat no-lead (QFN) package. A lead frame includes a first lead and a second lead, wherein each of the first lead and the second lead has an upper surface. A first silver point and a second silver point are provided on an upper surface of each of the first lead and the second lead. The integrated circuit die has a front surface including a first interconnect pad and a second interconnect pad. A first pillar is mounted for each of the first interconnect pads, and a second pillar is mounted for each of the second interconnect pads. The integrated circuit die is mounted to the lead frame in a flip-chip orientation with the first pillar soldered to the first silver point and the second pillar soldered to the second silver point. The resin body encapsulates the integrated circuit die mounted to the lead frame.

Description

Technical Field

[0001] The present disclosure relates generally to packaging for integrated circuit devices, and more particularly to a quad flat no-lead (QFN) package that supports an integrated circuit die in a flip-chip orientation using stud bumps of varying sizes mounted to a lead frame. Background Art

[0002] Semiconductor manufacturing technology is used to form multiple integrated circuits on a wafer of semiconductor material using well-known front-end-of-line (FEOL) and back-end-of-line (BEOL) processes. Once the wafer of semiconductor material is processed, the processed wafer is cut into individual integrated circuit devices (each such device is also referred to in the art as an integrated circuit (IC) die) using a singulation process. Each individual integrated circuit device is then packaged by attaching the IC die to a lead frame and then encapsulating the IC die and lead frame in a resin body.

[0003] Different types of packages are known in the art. Of particular interest is the quad flat no-lead (QFN) package, which is well suited for surface mount mounting. The QFN package has a small square or rectangular resin body with no leads. In this context, "no leads" means that the electrode contacts of the packaged device do not extend away from the resin body.

[0004] Figure 1 A cross-sectional view of a conventional QFN packaged integrated circuit device 10 is illustrated. The lead frame 12 includes a die pad 12a and a plurality of leads 12b arranged around the die pad. The back side of the integrated circuit die 14 is mounted to the upper surface of the die pad 12a using a die attach material (e.g., die attach film (DAF), other adhesives, or soldering - not explicitly shown). The front surface of the integrated circuit die 14 includes interconnect pads 16, which are generally arranged adjacent to the peripheral edge of the die. These interconnect pads 16 are electrically connected to the circuit integrated on the semiconductor substrate of the die through an interconnect network (including, for example, a redistribution layer (RDL) and a metallization layer). The electrical connection of the interconnect pads 16 to the leads 12b is performed by bonding wires 18. The integrated circuit die 14 mounted to the die pad 12a and electrically connected to the leads 12b is then encapsulated in a resin body 20. The bottom surface of the die pad 12a is exposed at the bottom surface of the resin body (e.g., used as a thermal conductor or heat sink). In addition, the bottom surface of the lead 12b is exposed at the bottom surface of the resin body, and the side surface of the lead 12b is exposed at the side of the resin body to support surface mounting of the packaged IC die to a supporting substrate such as a printed circuit board (PCB). Summary of the invention

[0005] In an embodiment, an integrated circuit package includes: a lead frame including a first plurality of leads and a second plurality of leads, wherein each of the first plurality of leads and the second plurality of leads has an upper surface; at least one first silver dot on the upper surface of each of the first plurality of leads, wherein each first silver dot has a first size and a first shape in a plan view; at least one second silver dot on the upper surface of each of the second plurality of leads, wherein each second silver dot has a second size and a second shape in a plan view; an integrated circuit die having a front surface including a first plurality of interconnect pads and a second plurality of interconnect pads; a first column mounted to each of the first plurality of interconnect pads, wherein the first column has a third size and a third shape in a plan view; a second column mounted to each of the second plurality of interconnect pads, wherein the second column has a fourth size and a fourth shape in a plan view; wherein the integrated circuit die is mounted to the lead frame in a flip chip orientation, wherein the first column is soldered to the first silver dot and the second column is soldered to the second silver dot; and a resin body encapsulating the integrated circuit die mounted to the lead frame.

[0006] In an embodiment, there is a layer of non-solder wettable material (such as, for example, oxide) on an upper surface of each of the first and second pluralities of leads, the layer of non-solder wettable material surrounding the first and second silver dots.

[0007] In one embodiment, the first plurality of leads and the second plurality of leads provide electrode contacts for a flat no-lead type package. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings, in which:

[0009] Figure 1 illustrates a cross-sectional view of a conventional QFN packaged integrated circuit device;

[0010] Figure 2 illustrates a cross-sectional view of a QFN packaged integrated circuit device having a flip chip die;

[0011] Figure 3A illustrates a perspective view of a die using non-uniformly sized posts;

[0012] Figure 3B and Figure 3C Side views of columns with different sizes are shown;

[0013] Figure 4 A perspective view of a lead frame is illustrated;

[0014] Figure 5A and Figure 5B A comparison of the size and shape of the pillars and silvered dots is illustrated in plan view;

[0015] Figure 5C and Figure 5D A comparison of the size and shape of the pillars and silvered dots is illustrated in plan view;

[0016] Figure 6 Illustration of the use Figure 3A The die is flip-chip attached to Figure 4 A phantom perspective view of an integrated circuit device of a lead frame QFN package;

[0017] Figure 7 a cross section illustrating the connection of a die post to a lead of a lead frame; and

[0018] Fig. 8A , Figure 8B and Figure 8C A cross-sectional image of an integrated circuit device is shown. DETAILED DESCRIPTION

[0019] In different drawings, the same elements are designated by the same reference numerals. In particular, common structural and / or functional elements in different embodiments may be designated by the same reference numerals and may have the same structure, dimensions and material properties.

[0020] Throughout this disclosure, the term “connected” is used to designate a direct electrical connection between circuit elements with no intervening elements other than conductors, while the term “coupled” is used to designate an electrical connection between circuit elements that may be direct or may be via one or more intervening elements.

[0021] The terms “about”, “substantially” and “approximately” are used herein to designate a tolerance of plus or minus 10%, preferably plus or minus 5%, of the relevant value.

[0022] Reference now Figure 2 , Figure 2A cross-sectional view of an integrated circuit device 110 of a QFN package with a flip chip die is illustrated. A lead frame 112 includes a plurality of first (finger or segment) leads 112a and a plurality of second (end) leads 112b. The front surface of the integrated circuit die 114 includes a core post 116 (also referred to in the art as a bump) mounted to an interconnect pad 16. The interconnect pad 16 is electrically connected to the circuit integrated on the semiconductor substrate of the die through an interconnect network (including, for example, a redistribution layer (RDL) and a metallization layer). The integrated circuit die 114 is mounted to the lead frame in a "flip chip" orientation, wherein the front surface of the integrated circuit die 114 faces the upper surface of the lead frame 112. The distal ends of the core posts 116 are welded to the upper surface of the lead frame. Specifically, the ends of the core posts 116 disposed adjacent to the peripheral edge of the die are welded to the second leads 112b, and the core posts 116 disposed closer to the center of the die are welded to the first leads 112a. The integrated circuit die 114 mounted to the lead frame in a flip chip orientation is then packaged in a resin body 120 to form a packaged IC die. The bottom surface of the lead 112a is exposed at the bottom surface of the resin body, and the end surface of the lead 112a is exposed at the side of the resin body. In addition, the bottom surface of the lead 112b is exposed at the bottom surface of the resin body, and the side surface of the lead 112b is exposed at the side of the resin body.

[0023] Integrated circuit dies may be designed to use die posts of different sizes. Figure 3A A perspective view of an integrated circuit die 214 using non-uniformly sized pillars 216 is illustrated. The pillars 216 may include, for example, pillars 216a having a first size and shape (here shown as a circular shape having a first surface area in a plan view (i.e., facing the top)) and pillars 216b having a second size and shape (here shown as a stadium or track or oval shape having a second surface area greater than the first surface area in a plan view (i.e., facing the top)). The pillars 216a having the first size and shape are arranged adjacent to the peripheral edge of the die, while the pillars 216b having the second size and shape are arranged closer to the center on the die. This arrangement is merely an example and is not intended to be limiting, and the designer may provide pillars of different sizes and shapes at desired locations. In addition, although the die 214 is shown as having two different shapes of pillars in a plan view, it is understood that the integrated circuit die may be designed to use many different shapes and sizes of die pillars (e.g., may include three or more different sizes and shapes of pillars). As an example, but not by way of limitation, a first column having a stadium or track or oval shape in plan view, a second column having a first surface area that is circular in plan view, and a third column having a second surface area that is smaller than the first surface area that is circular in plan view may be included on a single tube core 214.

[0024] Figure 3BA side view of column 216a is shown and Figure 3C A side view of a column 216b is shown. Each column 216 includes a base 230 made of copper, which is mounted to a surface 232 of the interconnect pad 16 of the integrated circuit device. The top of the base 230 is covered with solder 234. A thin nickel layer can be provided between the solder 234 and the top of the base 230. Considering that the pillar growth is carried out by an electroplating process, having columns with different shapes means that there will be different electroplating areas to cover, coupled with process variations, which will lead to poor column coplanarity, thereby affecting the welding quality between the column and the lead frame. Note the topological difference in the height of the column, indicated by the dotted line. This topological difference can be a problem when the integrated circuit die 214 is mounted to the lead frame in a flip-chip manner, because the risk of forming a cold joint between the column 216a, the column 216b and the lead frame increases. In order to reduce this risk, it is proposed to form a silver point surrounded by a non-wetting layer on the lead frame. Both will strengthen the solder joint between the pillars 216a, 216b and the lead frame.

[0025] Reference now Figure 4 , Figure 4 A perspective view of a lead frame 212 is illustrated. The lead frame 212 is made of, for example, a copper sheet or copper alloy sheet that is formed by a manufacturing process such as stamping and etching to define a plurality of leads 214. The leads 214 may include a plurality of segment (or finger) leads 220 and a plurality of end leads 222. The segment leads 220 and the end leads 222 may have a half-etched configuration as known in the art to form an undercut region 227. It will be noted that for simplicity, Figure 4 The illustration in shows the lead frame 212 in the context of a single package.

[0026] Each segment lead 220 extends longitudinally in a first direction (ie, in the direction of its longer or length) and is Figure 6 , extending between opposite first and second sides of the package (those first sides being perpendicular to the first direction). The longitudinal end surface of each segment lead 220 is exposed from the package at the first and second sides of the package.

[0027] The end leads 222 are arranged in two groups. The first group is located laterally (i.e., in the width direction) on one side of the segmented leads 220, and the second group is located laterally (i.e., in the width direction) on the opposite side of the segmented leads 220. The end surfaces of some of the end leads 222 are exposed from the package at the first and second sides of the package. The end surfaces of other end leads 222 are exposed from the package at the third and fourth sides of the package, which extend perpendicularly to the first and second sides of the package.

[0028] Silver dots 226 are plated at specific locations on the upper surfaces of the segmented leads 220 and the end leads 222. A photomask can be deposited on the surface of the lead frame leads 220, 222 and patterned to include openings for the dots 226 at desired locations. An electrolytic growth process is then performed to plate the surfaces of the lead frame leads 220, 222 at the openings in the photomask and form the dots 226. The silver dots 226 can have a thickness in the range of 2.5 to 7.25 μm, for example. Portions of the upper surfaces of the segmented leads 220 and the end leads 222 that are not covered by the silver-plated dots 226 are coated with a non-solder wettable layer 228. As an example, the layer 228 can include a thin brown oxide layer. The oxide layer can have a thickness in the range of 10-100 nanometers, for example. For example, the brown oxide layer can be formed by a thermal oxidation process, a chemical process, or an electrochemical process. Before performing the process for forming the non-solder wetting layer 228 , the lead frame may be subjected to a fine etching process to provide surface roughness to support improved adhesion of the molding material to the lead frame.

[0029] The oxidation process to form layer 228 as a brown oxide layer may include, for example, a chemical interaction in which the lead frame is placed in a chemical bath in which chemicals react with copper but not with silver-plated dots 226. Prior to performing the chemical interaction, other surfaces of the lead frame where the oxide layer is not desired may be covered with a mask.

[0030] Other processes may also be used to passivate the lead frame to obtain the non-solder wetting layer 228. Such processes include, for example, chemical processes, heating processes, and sputtering processes.

[0031] When the integrated circuit die 214 is oriented and mounted to the lead frame 212 in a flip chip configuration, the location of the silver dots 226 on the upper surfaces of the segment leads 220 and the end leads 222 corresponds to (i.e., is aligned with or coincides with) the location of the posts 216a, 216b, as shown in FIG. Figure 6 and Figure 7 The size and shape of the silver-plated dots 226 generally correspond to the size and shape of the pillars 216a, 216b, so that during solder reflow, the solder material (e.g., Ag+tin alloy) melts and takes the shape of the silver dots. In a preferred embodiment, the area of ​​the dots 226 is slightly larger than the corresponding pillars to account for manufacturing tolerances and assembly tolerances. In particular, the size and shape of the silver-plated dots 226 correspond to the size and shape of the pillars 216a, 216b. Figure 5A and Figure 5B 216a, 216b shown in FIG. 216a and 216b (eg, circular 240a and circular 242a, and oval 244a and oval 246a). Alternatively, the size and shape of the silver-plated dots 226 may be slightly different from the size and shape of the columns 216a, 216b. For example, as shown in FIG. Figure 5CAs shown in FIG. 2 , the silver-plated dot 226 a has a square shape with rounded corners in plan view (reference numeral 240 b ), while the column 216 a has a circular shape in plan view (reference numeral 242 b ). As another example, Figure 5D As shown in FIG. 1 , the silver-plated dots 226 b have a rectangular shape with rounded corners in plan view (reference numeral 244 b ), while the posts 216 b have a stadium or racetrack or oval shape in plan view (reference numeral 246 b ).

[0032] Figure 6 Also shown in dotted lines is a general outline of a resin body 250 that encapsulates an integrated circuit die 214 that is flip-chip mounted to a lead frame 212. The bottom surfaces 260 of the segment leads 220 and the end leads 222 are exposed at the bottom surface of the resin body. In addition, the side edges 262 of the segment leads 220 and the end leads 222 are exposed at the sides of the resin body.

[0033] Figure 7 A cross section through the connection of the post 216 to the leads 220, 222 of the lead frame is illustrated. Each silver dot 226 surrounded by a non-solder wetting layer 228 reduces the oozing of solder 234 during reflow. Each silver dot 226 further improves the formation of a solder joint between the post 216 and the lead frame.

[0034] Fig. 8A , Figure 8B and Figure 8C They are shown separately Figure 4 8A, 8B and 8C. As shown, the constraint on solder seepage provided by the use of silver-plated dots 226 and non-solder wetting layer 228 enables a reduction in the post pitch distance, thereby accommodating a greater number of posts in the die design without increasing the die or overall package size.

[0035] Although the present invention has been illustrated and described in detail in the drawings and the above description, these illustrations and descriptions should be regarded as illustrative or exemplary rather than restrictive; the present invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and implemented by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure, and the appended claims.

Claims

1. An integrated circuit package, comprising: a lead frame comprising a first plurality of leads and a second plurality of leads, wherein each lead of the first plurality of leads and the second plurality of leads has an upper surface; at least one first silver dot on an upper surface of each lead of the first plurality of leads, wherein each first silver dot has a first size and a first shape in plan view; at least one second silver dot on the upper surface of each lead of the second plurality of leads, wherein each second silver dot has a second size and a second shape in plan view; an integrated circuit die having a front surface including a first plurality of interconnect pads and a second plurality of interconnect pads; a first pillar mounted to each interconnect pad of the first plurality of interconnect pads, wherein the first pillar has a third size and a third shape in plan view; a second post mounted to each interconnect pad of the second plurality of interconnect pads, wherein the second post has a fourth size and a fourth shape in plan view; wherein the integrated circuit die is mounted to the lead frame in a flip chip orientation, wherein the first post is soldered to the first silver dot and the second post is soldered to the second silver dot; as well as A resin body encapsulates the integrated circuit die mounted to the lead frame.

2. The integrated circuit package of claim 1 further comprising a non-solder wetting layer on an upper surface of each of the first plurality of leads and the second plurality of leads, the non-solder wetting layer surrounding the first silver dot and the second silver dot.

3. The integrated circuit package of claim 2, wherein the non-solder wetting layer is an oxide layer.

4. The integrated circuit package of claim 3, wherein the oxide layer is a brown oxide layer.

5. The integrated circuit package of claim 2, wherein the non-solder wetting layer is formed using at least one of a chemical process, a heating process, and a sputtering process.

6. The integrated circuit package of claim 1, wherein for a flat no-lead type package, the first plurality of leads provide electrode contacts on the sides and bottom of the resin body.

7. The integrated circuit package of claim 1, wherein for a flat no-lead type package, the second plurality of leads provide electrode contacts on the sides and bottom of the resin body.

8. The integrated circuit package of claim 1, wherein the first size is greater than the third size, and the first shape is the same as the third shape.

9. The integrated circuit package of claim 1, wherein the first size is greater than the third size, and the first shape is different from the third shape.

10. The integrated circuit package of claim 1, wherein the second size is greater than the fourth size, and the second shape is the same as the fourth shape.

11. The integrated circuit package of claim 1, wherein the second size is greater than the fourth size, and the second shape is different from the fourth shape.

12. The integrated circuit package of claim 1, wherein the second plurality of leads comprises segmented leads extending longitudinally in a first direction between opposing first and second sides of the resin body, wherein the first and second sides extend in a second direction perpendicular to the first direction.

13. The integrated circuit package of claim 12, wherein the resin body further comprises opposing third and fourth sides extending in the first direction, and wherein the first plurality of leads comprises end leads arranged in two groups, a first group of the two groups being arranged along the third side and a second group of the two groups being arranged along the fourth side.

14. The integrated circuit package of claim 13, wherein end surfaces of the segment leads are exposed from the resin body at the first side and the second side, and wherein end surfaces of the end leads are exposed from the resin body at the third side and the fourth side. 15 . The integrated circuit package of claim 14 , wherein end surfaces of some of the end leads are exposed from the resin body at the first side and the second side.

16. An integrated circuit package as described in claim 1, wherein the integrated circuit tube core also includes a third plurality of interconnect pads on the front surface, and further includes a third column mounted to each interconnect pad of the third plurality of interconnect pads, wherein at least one of the size and shape of the third column is different from the corresponding size and shape of each of the first column and the second column.

Images