Silicon capacitor

Abstract

The invention relates to the technical field of silicon capacitors, and is widely applied to application scenes of various radio frequency and optical communication products. According to the main technology, the silicon capacitor comprises a silicon through hole substrate, a dielectric layer, a second electrode layer, an insulating layer, a first electrode layer, a through hole lead, an upper bonding pad and a lower bonding pad. Through holes of the silicon through hole substrate are cylindrical, prismatic or dumbbell-shaped, the side walls of the cylinders are perpendicular to the prismatic side walls, the dumbbell-shaped side walls are inclined, through an inverted quadrangular frustum pyramid formed by anisotropic corrosion of two surfaces of silicon, the through holes are arranged in an array mode to form a repeated structure, and the diameter of an opening of each through hole is 2-20 [mu] m-20 [mu] m-20 [mu] m-20 [mu] m-20 [mu] m-20 [mu] m-20 [mu] m. The silicon through hole technology is adopted, openings are formed in the two faces, and the problems that in the prior art, U-shaped deep grooves are poor in etching uniformity, the depth of holes cannot be consistent, and due to the fact that one face of each U-shaped deep groove is opened, stress is large in the capacitor preparation process, and fragments are caused are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of capacitors, and in particular to a silicon capacitor. Background Art

[0002] With the rapid development of communication technology, there are increasingly higher requirements for bandwidth frequency and loss. Silicon capacitors have been widely used in various application scenarios of RF and optical communication products.

[0003] Silicon capacitors use semiconductor technology to use heavily doped silicon substrates as the lower electrode of the capacitor. Silicon dioxide and silicon nitride are commonly used as the dielectric of the capacitor, and heavily doped polysilicon is used as the upper electrode of the capacitor. To increase the capacitance value, the most common method is to use a trench structure by etching the substrate in a narrow and deep shape. Usually, the cross-section of the trench structure is similar to a "U" shape. In addition, in order to increase the electrostatic capacitance, the trenches are repeated at a certain interval on the silicon substrate to form an array.

[0004] However, due to the poor etching uniformity of the U-shaped deep grooves in the prior art, the depth of the holes cannot be guaranteed to be consistent, resulting in a large deviation in the capacitance value. In addition, one side of the U-shaped deep groove is open, which causes high stress during the capacitor preparation process and leads to breakage. Summary of the invention

[0005] The present invention proposes a silicon capacitor, the purpose of which is to overcome the problems in the prior art that the etching uniformity of a U-shaped deep groove is poor, the depth of the hole cannot be guaranteed to be consistent, and one side of the U-shaped deep groove is open, resulting in high stress and fragmentation in the capacitor preparation process. The present invention provides a silicon capacitor, in which the silicon groove is a through-hole structure, thereby avoiding the capacitance deviation caused by the poor uniformity caused by blind hole etching, and at the same time, because both sides are open, the stress generated during the deep silicon etching process is released.

[0006] The technical solution of the present invention is as follows: A silicon capacitor includes a first capacitor, wherein the first capacitor includes:

[0007] A first through silicon via substrate, wherein the first through silicon via substrate is low-resistance silicon, has a resistivity of 0.001 to 0.01 Ω·cm, a thickness of 50 to 300 μm, and a crystal orientation of 100;

[0008] A plurality of first through holes are provided and are alternately arranged in an array on the first through silicon via substrate, wherein the first through holes are cylindrical or prism-shaped, and the side walls of the cylindrical or prism-shaped holes are both vertical, and the opening diameter of a single through hole is 2 μm to 20 μm;

[0009] A first dielectric layer uniformly covers the surface of the first through silicon via substrate and the entire area of ​​the first through hole sidewall, and has a thickness of 1 nm to 2000 nm;

[0010] A first upper electrode layer uniformly covers the surface of the first dielectric layer and also includes the surface of the first through silicon via substrate and the sidewalls of the first through hole, thereby filling the inside of the first through hole, has a thickness of 10nm to 2000nm, and forms an upper electrode structure with the first dielectric layer;

[0011] A first insulating layer uniformly covers the first upper electrode layer on the lower surface of the first through silicon via substrate;

[0012] A first through-hole lead is led out vertically from the bottom of the first through-silicon via substrate and serves as a lead in a vertical direction between the first lower electrode layer and the low-resistance first through-silicon via substrate to form an electrical connection;

[0013] The first lower electrode layer is located at the bottom of the first through silicon via substrate, uniformly covers the surface of the first insulating layer, has a thickness of 10nm to 2000nm, and together with the first through silicon via substrate constitutes a lower electrode, thereby forming a complete capacitor structure with the upper electrode;

[0014] A first upper pad is located on the surface of the first upper electrode layer and has a thickness of 1000nm to 10000nm;

[0015] The first lower pad is located on the surface of the first lower electrode layer and has a thickness of 1000nm to 10000nm.

[0016] Preferably, the first dielectric layer is one or a combination of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, indium oxide, etc.

[0017] Preferably, the first upper electrode layer is one of heavily doped polysilicon, metal gold, metal aluminum, metal copper, tantalum nitride and titanium nitride.

[0018] Preferably, the first lower electrode layer is made of one of metal gold, metal aluminum, metal copper, tantalum nitride and titanium nitride.

[0019] Preferably, the first upper pad and the first lower pad are both made of metal gold, metal aluminum, metal copper, metal titanium, metal nickel, metal palladium, or a combination of multiple metals.

[0020] A silicon capacitor, comprising a second capacitor, wherein the second capacitor comprises:

[0021] A second through silicon via substrate, wherein the second through silicon via substrate is low-resistance silicon, has a resistivity of 0.001 to 0.01 Ω·cm, a thickness of 50 to 300 μm, and a crystal orientation of 100;

[0022] A plurality of second through holes are provided and are alternately arranged in an array on a second through silicon via substrate, the second through holes are dumbbell-shaped, the side walls are symmetrically distributed at obtuse angles, an inverted tetrahedral structure is formed on the hole wall by anisotropic etching of both sides of silicon, and the opening diameter of a single through hole is 2 μm to 20 μm;

[0023] A second dielectric layer uniformly covers the surface of the second through silicon via substrate and the entire area of ​​the sidewall of the second through hole of the second through silicon via substrate, and has a thickness of 1 nm to 2000 nm;

[0024] A second upper electrode layer uniformly covers the surface of the second dielectric layer and also includes the surface of the second through silicon via substrate and the sidewalls of the second through hole, thereby filling the inside of the second through hole, has a thickness of 10nm to 2000nm, and forms an upper electrode structure with the second dielectric layer;

[0025] A second insulating layer uniformly covers the second upper electrode layer on the lower surface of the second through silicon via substrate;

[0026] A second through-hole lead is led out vertically from the bottom of the substrate to form an electrical connection between the second lower electrode layer and the low-resistance second through-silicon via substrate in a vertical direction;

[0027] The second lower electrode layer is located at the bottom of the second through silicon via substrate, uniformly covers the surface of the second insulating layer, has a thickness of 10nm to 2000nm, and together with the second through silicon via substrate forms a lower electrode, thereby forming a complete capacitor structure with the upper electrode;

[0028] A second upper pad is located on the surface of the second upper electrode layer and has a thickness of 1000nm to 10000nm;

[0029] The second lower pad is located on the surface of the second lower electrode layer and has a thickness of 1000nm to 10000nm.

[0030] Preferably, the second dielectric layer is one or a combination of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, indium oxide, etc.

[0031] Preferably, the second upper electrode layer is one of heavily doped polysilicon, metal gold, metal aluminum, metal copper, tantalum nitride and titanium nitride.

[0032] Preferably, the second lower electrode layer is made of one of metal gold, metal aluminum, metal copper, tantalum nitride and titanium nitride.

[0033] Preferably, the second upper pad and the second lower pad are both made of one or more combinations of metal gold, metal aluminum, metal copper, metal titanium, metal nickel, and metal palladium.

[0034] The beneficial effects of the present invention are:

[0035] The present invention adopts silicon through hole technology with openings on both sides, thus overcoming the problems in the prior art of poor etching uniformity of U-shaped deep grooves, inability to ensure consistent hole depth, and high stress and fragmentation in the capacitor preparation process caused by one side of the U-shaped deep groove being open. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0037] Figure 1 A schematic cross-sectional structure diagram of a silicon capacitor proposed in Embodiment 1 of the present invention;

[0038] Figure 2 A schematic cross-sectional structure diagram of a silicon capacitor proposed in Embodiment 2 of the present invention;

[0039] Figure 3 A capacitor and a traditional silicon capacitor capacitance distribution proposed in Embodiment 1 and Embodiment 2 of the present invention;

[0040] In the figure: 100, a first capacitor; 101, a first through silicon via substrate; 102, a first through hole; 103, a first dielectric layer; 104, a first upper electrode layer; 105, a first insulating layer; 106, a first through hole lead; 107, a first lower electrode layer; 108, a first upper pad; 109, a first lower pad; 200, a second capacitor; 201, a second through silicon via substrate; 202, a second through silicon via substrate; 202, a second through hole; 203, a second dielectric layer; 204, a second upper electrode layer; 205, a second insulating layer; 206, a second through hole lead; 207, a second lower electrode layer; 208, a second upper pad; 209, a second lower pad. DETAILED DESCRIPTION

[0041] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] Embodiment 1

[0043] See also Figure 1 The present embodiment provides a silicon capacitor, including a first capacitor 100, wherein the first capacitor 100 includes a first through silicon via substrate 101, a first through hole 102, a first dielectric layer 103, a first upper electrode layer 104, a first insulating layer 105, a first through hole lead 106, a first lower electrode layer 107, a first upper pad 108, and a first lower pad 109, wherein the first through silicon via substrate 101 is low-resistance silicon, has a resistivity of 0.001 to 0.01 Ω·cm, a thickness of 50 to 300 μm, and a crystal orientation of 100.

[0044] Specifically, a plurality of first through holes 102 are arranged alternately in an array on the first through silicon via substrate 101. The first through holes 102 are cylindrical or prismatic. The side walls of the cylindrical and prismatic shapes are both vertical. The opening diameter of a single through hole is 2 μm to 20 μm.

[0045] Furthermore, the first dielectric layer 103 uniformly covers the surface of the first through silicon via substrate 101 and the entire area of ​​the sidewall of the first through hole 102, with a thickness of 1nm to 2000nm. The first dielectric layer 103 is one or a combination of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, indium oxide, etc. If a single layer of silicon oxide is used, it can be deposited by a thermal oxidation process, and other materials are deposited by plasma enhanced chemical vapor deposition (PECVD) or atomic vapor deposition (ALD) process.

[0046] Further, the first upper electrode layer 104 uniformly covers the surface of the first dielectric layer 103 and also includes the surface of the first silicon via substrate 101 and the side walls of the first through hole 102, thereby filling the inside of the first through hole 102 with a thickness of 10nm to 2000nm, and forms an upper electrode structure with the first dielectric layer 103. The first upper electrode layer 104 is one of heavily doped polysilicon, metal gold, metal aluminum, metal copper, tantalum nitride and titanium nitride. If heavily doped polysilicon is used, an in-situ doping low-pressure chemical vapor deposition (LPCVD) process can be used. If metal is used, a magnetron sputtering sidewall seed layer can be used to cover the upper and lower surfaces of the silicon via substrate 101 and the side walls of the through hole with a thickness of 10nm to 100nm, and then an electroplating process is used to fill the inside of the through hole.

[0047] Furthermore, the first insulating layer 105 uniformly covers the first upper electrode layer 104 on the lower surface of the first through silicon via substrate 101, and its main purpose is to isolate the electrical connection between the first 107 and the second electrode layer 104, and adopts plasma enhanced chemical vapor deposition (PECVD) or atomic vapor deposition (ALD) process, with a thickness of 5nm to 2000nm.

[0048] Specifically, the first through-hole lead 106 is vertically led out from the bottom of the first through-silicon via substrate 101 to form an electrical connection between the first lower electrode layer 107 and the low-resistance first through-silicon via substrate 101 in a vertical direction.

[0049] Further, the first lower electrode layer 107 is located at the bottom of the first silicon via substrate 101, uniformly covers the surface of the first insulating layer 105, is deposited by magnetron sputtering process, has a thickness of 10nm to 2000nm, and together with the first silicon via substrate 101 constitutes a lower electrode, thereby forming a complete capacitor structure with the upper electrode. The capacitance value depends on the thickness of the dielectric layer and the height and arrangement density of the through hole. If a higher capacitance value is required, the dielectric layer and the electrode layer can be repeatedly deposited in the first through hole 102 to form a plurality of capacitor parallel structures. The first lower electrode layer 107 is one of metal gold, metal aluminum, metal copper, tantalum nitride and titanium nitride.

[0050] Furthermore, the first upper pad 108 is located on the surface of the first upper electrode layer 104, and is thickened by electroplating process, with a thickness of 1000nm to 10000nm. The first lower pad 109 is located on the surface of the first lower electrode layer 107, and has a thickness of 1000nm to 10000nm. The first upper pad 108 and the first lower pad 109 are both one or more combinations of metal gold, metal aluminum, metal copper, metal titanium, metal nickel, and metal palladium.

[0051] Embodiment 2

[0052] See also Figure 2 The present embodiment provides a silicon capacitor, including a second capacitor 200, the second capacitor 200 including a second through silicon via substrate 201, a second through hole 202, a second dielectric layer 203, a second upper electrode layer 204, a second insulating layer 205, a second through hole lead 206, a second lower electrode layer 207, a second upper pad 208, and a second lower pad 209, wherein the second through silicon via substrate 201 is low-resistance silicon, with a resistivity of 0.001-0.01Ω·cm, a thickness of 50-300μm, and a crystal orientation of 100, a plurality of second through holes 202 are provided and are alternately arranged in an array on the second through silicon via substrate 201, and different from the first embodiment, the second through holes 202 in the present embodiment are dumbbell-shaped, with side walls symmetrically distributed at obtuse angles, and an inverted quadrangular pyramid structure is formed on the hole wall by anisotropic etching of both sides of silicon, and the opening diameter of a single through hole is 2μm-20μm, and the rest of the structure is the same as the first embodiment.

[0053] The above embodiment provides a silicon capacitor, in which the silicon trench of the silicon capacitor is a through-hole structure, thereby avoiding the capacitance deviation caused by poor uniformity caused by blind hole etching. Figure 3 As can be seen from the table below, the capacitance uniformity of the through silicon via structure within the wafer is less than 1.3%, and the capacitance uniformity of the blind via structure with the same depth within the wafer is about 15.5%. The statistical data clearly show the advantage of the present invention in improving capacitance deviation.

[0054]

[0055] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A silicon capacitor, characterized in that: The invention comprises a first capacitor (100), wherein the first capacitor (100) comprises: A first through silicon via substrate (101), wherein the first through silicon via substrate (101) is low-resistance silicon, has a resistivity of 0.001 to 0.01 Ω·cm, a thickness of 50 to 300 μm, and a crystal orientation of 100; A plurality of first through holes (102) are provided and are alternately arranged in an array on the first through silicon via substrate (101); the first through holes (102) are cylindrical or prism-shaped; the side walls of the cylindrical or prism-shaped holes are both vertical; and the opening diameter of a single through hole is 2 μm to 20 μm; A first dielectric layer (103) uniformly covers the surface of the first through silicon via substrate (101) and the entire area of ​​the sidewall of the first through hole (102), and has a thickness of 1 nm to 2000 nm; A first upper electrode layer (104) uniformly covers the surface of the first dielectric layer (103) and also includes the surface of the first through silicon via substrate (101) and the sidewalls of the first through hole (102), thereby filling the inside of the first through hole (102) with a thickness of 10nm to 2000nm, and forming an upper electrode structure with the first dielectric layer (103); A first insulating layer (105) uniformly covers the outside of the first upper electrode layer (104) on the lower surface of the first through silicon via substrate (101); A first through-hole lead (106) is vertically led out from the bottom of the first through-silicon via substrate (101) and serves as a lead in a vertical direction between the first lower electrode layer (107) and the low-resistance first through-silicon via substrate (101) to form an electrical connection; A first lower electrode layer (107) is located at the bottom of the first through silicon via substrate (101), uniformly covers the surface of the first insulating layer (105), has a thickness of 10nm to 2000nm, and together with the first through silicon via substrate (101) forms a lower electrode, thereby forming a complete capacitor structure with the upper electrode; A first upper pad (108), located on the surface of the first upper electrode layer (104), having a thickness of 1000nm to 10000nm; The first lower pad (109) is located on the surface of the first lower electrode layer (107) and has a thickness of 1000nm to 10000nm.

2. A silicon capacitor according to claim 1, characterized in that: The first dielectric layer (103) is one or a combination of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, indium oxide, etc.

3. The silicon capacitor according to claim 1, characterized in that: The first upper electrode layer (104) is one of heavily doped polysilicon, metal gold, metal aluminum, metal copper, tantalum nitride and titanium nitride.

4. The silicon capacitor according to claim 1, characterized in that: The first lower electrode layer (107) is made of one of metal gold, metal aluminum, metal copper, tantalum nitride and titanium nitride.

5. The silicon capacitor according to claim 1, characterized in that: The first upper pad (108) and the first lower pad (109) are both made of one or more combinations of metal gold, metal aluminum, metal copper, metal titanium, metal nickel, and metal palladium.

6. A silicon capacitor, characterized in that: The invention comprises a second capacitor (200), wherein the second capacitor (200) comprises: A second through silicon via substrate (201), wherein the second through silicon via substrate (201) is low-resistance silicon, has a resistivity of 0.001 to 0.01 Ω·cm, a thickness of 50 to 300 μm, and a crystal orientation of 100; A plurality of second through holes (202) are provided and are alternately arranged in an array on a second through silicon via substrate (201); the second through holes (202) are dumbbell-shaped, with side walls symmetrically distributed at obtuse angles; an inverted quadrangular pyramid structure is formed on the hole wall by anisotropic etching of both sides of silicon; and the opening diameter of a single through hole is 2 μm to 20 μm; A second dielectric layer (203) uniformly covers the surface of the second through silicon via substrate (201) and the entire sidewall of the second through hole (202) of the second through silicon via substrate, and has a thickness of 1 nm to 2000 nm; A second upper electrode layer (204) uniformly covers the surface of the second dielectric layer (203) and also includes the surface of the second through silicon via substrate (201) and the sidewalls of the second through hole (202), thereby filling the inside of the second through hole (202) with a thickness of 10nm to 2000nm, and forms an upper electrode structure with the second dielectric layer (203); A second insulating layer (205) uniformly covers the second upper electrode layer (204) on the lower surface of the second through silicon via substrate (201); A second through-hole lead (206) is vertically led out from the bottom of (201) to form an electrical connection between the second lower electrode layer (207) and the low-resistance second through-silicon via substrate (201) in a vertical direction; A second lower electrode layer (207) is located at the bottom of the second through silicon via substrate (201), uniformly covers the surface of the second insulating layer (205), has a thickness of 10 nm to 2000 nm, and together with the second through silicon via substrate (201) forms a lower electrode, thereby forming a complete capacitor structure with the upper electrode; A second upper pad (208), located on the surface of the second upper electrode layer (204), having a thickness of 1000nm to 10000nm; The second lower pad (209) is located on the surface of the second lower electrode layer (207) and has a thickness of 1000nm to 10000nm.

7. The silicon capacitor according to claim 6, characterized in that: The second dielectric layer (203) is one or a combination of silicon oxide, silicon nitride, hafnium oxide, aluminum oxide, zirconium oxide, tungsten oxide, indium oxide, etc.

8. The silicon capacitor according to claim 6, characterized in that: The second upper electrode layer (204) is one of heavily doped polysilicon, metal gold, metal aluminum, metal copper, tantalum nitride and titanium nitride.

9. The silicon capacitor according to claim 6, characterized in that: The second lower electrode layer (207) is made of one of metal gold, metal aluminum, metal copper, tantalum nitride and titanium nitride.

10. The silicon capacitor according to claim 6, characterized in that: The second upper pad (208) and the second lower pad (209) are both made of one or more combinations of metal gold, metal aluminum, metal copper, metal titanium, metal nickel, and metal palladium.

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