Bonding device structure and manufacturing method thereof

Abstract

The bonding device structure includes: a carrier structure; an integrated circuit (IC) die bonded to a surface of the carrier structure via a bonding layer, where the IC die includes an eave vertically spaced from and over the surface of the carrier structure, a bay region between the eave and the surface of the carrier structure; and a molded portion within the bay region. Various characteristics of the bay region and / or the molding compound may be designed to provide improved stress distribution and reduce crack defects. In some embodiments, the ratio of width to height of the bay region may gt; 1. In some embodiments, the void ratio of the molding compound may be between 0.2 and 0.4. The embodiment of the invention relates to a bonding device structure and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to bonding device structures and methods of manufacturing the same. Background Art

[0002] The semiconductor industry has grown due to the continuous improvement in the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.).

[0003] In addition to smaller electronic components, improvements to component packaging have been developed in an effort to provide smaller packages that occupy less area than previous packages. Exemplary methods include quad flat packages (QFP), pin grid arrays (PGA), ball grid arrays (BGA), flip chips (FC), three-dimensional integrated circuits (3DIC), wafer level packages (WLP), stacked packages (PoP), systems on chips (SoC) or systems on integrated circuits (SoIC) devices. Some of these three-dimensional devices are prepared by placing a chip above the chip. These three-dimensional devices provide improved integration density and other advantages due to the reduced length of the interconnects between the stacked chips. However, there are many challenges associated with three-dimensional devices. Summary of the invention

[0004] Some embodiments of the present application provide a bonding device structure, comprising: a carrier structure; an integrated circuit (IC) die bonded to the surface of the carrier structure via a bonding layer, the integrated circuit die comprising an eaves above the surface of the carrier structure, wherein a bay area is located between the eaves and the surface of the carrier structure, and a ratio of a width dimension to a height dimension of the bay area is at least 1; and a molding portion laterally surrounding the integrated circuit die and located within the bay area between the surface of the carrier structure and the eaves.

[0005] Other embodiments of the present application provide a bonding device structure, comprising: a carrier structure; at least one integrated circuit (IC) die bonded to the surface of the carrier structure via a bonding layer, each integrated circuit die comprising an eaves above the surface of the carrier structure, wherein a bay area is located between the eaves and the surface of the carrier structure; and a molding portion laterally surrounding each integrated circuit die and located within the bay area between the surface of the carrier structure and the eaves of each integrated circuit die, and a ratio of a total volume of voids in the molding portion to a total volume of a molding compound in the molding portion is between 0.2 and 0.4.

[0006] Still other embodiments of the present application provide a method for manufacturing a bonding device structure, comprising: forming a bonding layer above a semiconductor substrate; performing a plasma cutting process to remove a portion of the bonding layer and forming an opening, the opening having a recessed surface recessed relative to an upper surface of the bonding layer and a sidewall extending between the recessed surface and the upper surface of the bonding layer; performing a cutting process through the semiconductor substrate to provide an integrated circuit (IC) die; bonding the bonding layer to a surface of a carrier structure to form a bonding device structure, wherein the upper surface of the bonding layer contacts the surface of the carrier structure, the integrated circuit die includes an eaves above the surface of the carrier structure, and a bay area is located between the eaves and the surface of the carrier structure, and a ratio of a width dimension to a height dimension of the bay area is at least 1; and forming a molding portion that laterally surrounds the integrated circuit die and is located within the bay area. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 is a vertical cross-sectional view showing a portion of a semiconductor wafer according to various embodiments of the present disclosure.

[0009] Figure 2 is a vertical cross-sectional view of a semiconductor wafer 100 , illustrating a plurality of first metal bonding pads and first bonding vias in a first bonding layer according to various embodiments of the present disclosure.

[0010] Figure 3 is a vertical cross-sectional view of a semiconductor wafer illustrating a protection layer over an upper surface of a first bonding layer according to various embodiments of the present disclosure.

[0011] Figure 4A is a vertical cross-sectional view of a semiconductor wafer illustrating a plurality of openings in a first bonding layer according to various embodiments of the present disclosure.

[0012] Figure 4B is a vertical cross-sectional view of a semiconductor wafer showing a plurality of openings in a first bonding layer according to another embodiment of the present disclosure.

[0013] Figure 5 is a vertical cross-sectional view of a semiconductor wafer after a thinning process of removing a backside portion of a first semiconductor substrate according to various embodiments of the present disclosure.

[0014] Figure 6is a vertical cross-sectional view of a semiconductor wafer illustrating a plurality of trenches formed through an interconnect structure according to various embodiments of the present disclosure.

[0015] Figure 7 is a vertical cross-sectional view of an integrated circuit (IC) die according to various embodiments of the present disclosure.

[0016] Figure 8 is a vertical cross-sectional view showing an IC die bonded to a carrier structure to form a bonded device structure according to various embodiments of the present disclosure.

[0017] Fig. 9 is a vertical cross-sectional view of a bonded device structure including a protective film over an exposed surface of the bonded device structure 130 according to various embodiments of the present disclosure.

[0018] Fig.10 is a vertical cross-sectional view of a bonded device structure after a grinding process to remove a protective film from over a backside surface of a first semiconductor substrate of an IC die according to various embodiments of the present disclosure.

[0019] Fig.11 is a vertical cross-sectional view of a bonded device structure showing a molded portion around an IC die according to various embodiments of the present disclosure.

[0020] Fig.12 is a vertical cross-sectional view of a bonded device structure having a multi-layer configuration according to various embodiments of the present disclosure.

[0021] Fig.13A is a vertical cross-sectional view of a bonded device structure having a multi-layer configuration according to another embodiment of the present disclosure.

[0022] Fig. 13B yes Fig.13A An enlarged vertical cross-sectional view of region B.

[0023] Fig. 13C yes Fig.13A An enlarged vertical cross-sectional view of region C.

[0024] Fig.14A is a vertical cross-sectional view of a bonded device structure having a multi-layer configuration according to an embodiment of the present disclosure.

[0025] Fig. 14B yes Fig.14A Top view of the first IC die of the bonded device structure.

[0026] Fig. 14C yes Fig.14A An enlarged vertical cross-sectional view of region D of FIG.

[0027] Fig.14D According to another embodiment of the present disclosure Fig.14A An enlarged vertical cross-sectional view of region D of FIG.

[0028] FIG. 15A to FIG. 15H is a vertical cross-sectional view of a multi-layer bonded device structure, showing different configurations of protective films according to various embodiments of the present disclosure.

[0029] FIG. 16A to FIG. 16I is a vertical cross-sectional view of a bonded device structure showing different shapes of the bay area under the eaves according to various embodiments of the present disclosure.

[0030] FIG. 17A to FIG. 17I is a vertical cross-sectional view of a multi-layer bonded device structure showing various configurations for the shape of the bay regions of IC dies in different layers according to various embodiments of the present disclosure.

[0031] 18A to 18D is a top view of a bonded device structure according to various embodiments of the present disclosure.

[0032] Fig.18E yes Fig.18A The bonding device structure along Fig.18A A vertical cross-sectional view taken along line EE' in FIG.

[0033] Fig.19 is a flow chart illustrating a method of fabricating a bonded device structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0035] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly. Unless expressly stated otherwise, each element having the same reference numeral is assumed to be of the same material composition and having a thickness within the same thickness range.

[0036] Various embodiments disclosed herein are directed to semiconductor devices, and in particular, to a bonded device structure including at least one semiconductor integrated circuit (IC) die bonded to a carrier structure, which may be, for example, a substrate, an interposer, another semiconductor die, or a semiconductor wafer. At least one semiconductor IC die may be bonded to the carrier structure in a configuration such as a system on an integrated chip (SoIC), a chip on wafer on substrate (CoWoS), a chip on wafer (CoW), etc. Such a bonded device structure may increase the density of devices that may occupy a given planar area or "footprint".

[0037] A semiconductor IC die may include a semiconductor material substrate, such as a silicon substrate, having a plurality of circuit components and elements formed on and / or within the semiconductor material. Semiconductor dies are typically manufactured by: sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate (e.g., a wafer); patterning the various material layers using photolithography to form integrated circuits; and separating individual dies from the substrate, such as by sawing along scribe lines between the integrated circuits.

[0038] A bonded device structure may be formed by placing a first device structure (e.g., an IC die) on a carrier structure in a "face down" configuration such that an integrated circuit component formed on a first side (i.e., front) of a semiconductor substrate of the first device structure faces a surface of the carrier structure. A bonding process may be used to bond a bonded feature on the first device structure to a corresponding bonded feature on the carrier structure.

[0039] In some examples, the bonded device structure can include multiple levels or "layers" of device structures. For example, a first IC die can be bonded to a carrier structure, as described above. Then, a second IC die can be bonded over the second (i.e., back) side of the first IC die, a third IC die can be bonded over the second IC die, and so on, to provide a multi-layer bonded device structure.

[0040] In some embodiments, direct bonding techniques, such as metal-to-metal (MM) and dielectric-to-dielectric (DD) bonding techniques, can be used to bond device structures to form bonded device structures. In such bonding techniques, a bonding layer including an array of metal bonding pads surrounded by dielectric materials can be formed on the structure to be bonded. The bonding layer on the first device structure can be aligned above the corresponding bonding layer on the second device structure, and the two bonding layers can contact each other. This can produce chemical pre-bonding between the dielectric materials of the corresponding bonding layers. An annealing process can then be implemented to promote the bonding of the metal bonding pads of the corresponding bonding layers, thereby producing a metal bond extending between the first device structure and the second device structure. After the bonding process, a molded portion can be provided to seal and protect each device structure.

[0041] One problem with a bonded device structure utilizing bonding techniques as described above is that mechanical stresses may become concentrated in certain areas of the structure. These mechanical stresses may result in poor bonding of molded parts, cracks forming in the IC die, and other defects. This may adversely affect device performance and yield.

[0042] Various embodiments disclosed herein are directed to a bonded device structure that can provide improved performance and yield by providing more effective stress distribution and reduced crack defects. In various embodiments disclosed herein, the bonded device structure may include a carrier structure, an integrated circuit (IC) die bonded to the surface of the carrier structure via a bonding layer, wherein the IC die includes an eaves vertically separated from the surface of the carrier structure and located above the surface of the carrier structure. The bay area may be located between the eaves and the surface of the carrier structure, and the molded portion may be located within the bay area. In various embodiments, designing various characteristics of the bay area, such as the size, shape and / or relative size of the bay area, can enable stress to be distributed more effectively, which can result in reduced crack formation, and can improve the overall performance and yield of the bonded device structure.

[0043] In some embodiments, the IC die can be formed such that in an instance where the IC die is bonded to a carrier structure, the aspect ratio of the bay region (which can be defined as the ratio of the width dimension of the bay region to the height dimension) can be equal to or greater than 1, such as between 1 and 80. By implementing such a ratio, the IC die can promote effective stress distribution, which can help improve the performance of the bonded device structure. In various embodiments disclosed herein, the size, shape and / or relative size of the bay region can be controlled by controlling the process used to manufacture the IC die, which can include a plasma cutting process, a laser slotting process and / or a mechanical cutting process.

[0044] In further embodiments, the molded portion may have a void ratio between 0.2 and 0.4, where the void ratio may be defined as the ratio of the total volume of the void area in the molded portion to the total volume of the molding compound in the molded portion. By implementing such a void ratio, various embodiments may enable the molded portion to provide adequate mechanical support and / or protection for various components of the joined device structure while also enabling the molded portion to be adequately bonded to the surrounding structure.

[0045] In some embodiments, one or more protective layers may be provided over the surface of the IC die to help suppress crack defects.

[0046] Figures 1 to 11 are sequential vertical cross-sectional views illustrating intermediate structures during a process of fabricating a bonded device structure according to various embodiments of the present disclosure. Figure 1 1 is a vertical cross-sectional view showing a portion of a semiconductor wafer 100 according to various embodiments of the present disclosure. The semiconductor wafer 100 may include a first semiconductor substrate 101, which may include an elemental semiconductor such as silicon or germanium and / or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide, or a combination thereof. Other semiconductor substrate materials are within the contemplation of the embodiments of the present disclosure. In some embodiments, the first semiconductor substrate 101 may be a semiconductor on insulator (SOI) substrate.

[0047] The first semiconductor substrate 101 may include a first main surface (i.e., front side surface 102) and a second main surface (i.e., back side surface 103). In some embodiments, the thickness of the first semiconductor substrate 101 between the front side surface 102 and the back side surface 103 may be between about 100 μm and about 800 μm, but a first semiconductor substrate 101 having a greater or lesser thickness may also be utilized.

[0048] In some embodiments, multiple devices ( Figure 1 The device (not shown) may be disposed on, above and / or in the front side surface 102 of the first semiconductor substrate 101. The device may include, for example, an active device, a passive device, or a combination thereof. In some embodiments, the device disposed on, above and / or in the front side surface 102 of the first semiconductor substrate 101 may include an integrated circuit device. The integrated circuit device may include, for example, a transistor (e.g., a field effect transistor (FET)), a capacitor, a resistor, a diode, a photodiode, a fuse device, or other similar devices. In some embodiments, the integrated circuit device may include a gate electrode, a source / drain region, a spacer, an isolation trench, etc.

[0049] The semiconductor wafer 100 may additionally include an interconnect structure 105 over the front side surface 102 of the first semiconductor substrate 101. The interconnect structure 105 may include a metal feature 107 (e.g., a metal line, a via, etc.) formed in a dielectric material 106 (e.g., one or more interlayer dielectric (ILD) layers and / or intermetal dielectric (IMD) layers), which may provide connections to various devices located on, over, and / or in the front side surface 102 of the first semiconductor substrate 101 and / or connections between various devices located on, over, and / or in the front side surface 102 of the first semiconductor substrate 101.

[0050] According to various embodiments of the present disclosure, the semiconductor wafer 100 may further include a first bonding layer 109 above the interconnect structure 105. The first bonding layer 109 may include one or more dielectric material layers 108 composed of suitable dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, dielectric polymer materials, etc. Other suitable dielectric materials are within the scope of consideration of the embodiments of the present disclosure. In a non-limiting embodiment, one or more first bonding layers 109 may include two or more dielectric material layers 108 with different compositions, wherein the etching resistance of different dielectric layers 108 may be different relative to the etching chemicals used during the subsequent etching step. Therefore, one or more of the dielectric material layers 108 may be referred to as etching stop layers. In various embodiments, one or more dielectric material layers 108 may be deposited using any suitable deposition process. Herein, "suitable deposition process" may include chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, high density plasma CVD (HDPCVD) process, low pressure CVD process, metal organic CVD (MOCVD) process, plasma enhanced CVD (PECVD) process, sputtering process, laser ablation, etc., including various combinations thereof. The first bonding layer 109 may have a flat upper surface 112, such as Figure 1 as shown in .

[0051] Figure 1 A unit area (UA) of a semiconductor wafer 100 is shown. A UA of the semiconductor wafer 100 may be a portion of the semiconductor wafer 100 that may be subsequently separated (i.e., singulated) from the remainder of the semiconductor wafer 100 to provide an integrated circuit (IC) die, as further described below. The UA may include a group of integrated circuit devices disposed on, over, and / or in the front side surface 102 of the first semiconductor substrate 101, an interconnect structure 105 over the front side surface 102 of the first semiconductor substrate 101, and a portion of the first bonding layer 109. The semiconductor wafer 100 may generally include a plurality of UAs that may each be separated from the semiconductor wafer 100 to form a respective IC die.

[0052] Figure 2 is a vertical cross-sectional view of the semiconductor wafer 100 , illustrating a plurality of first metal bonding pads 111 and first bonding vias 113 in the first bonding layer 109 according to various embodiments of the present disclosure. Figure 2 An embodiment including three dielectric material layers is shown, including a first dielectric material layer 108a above the interconnect structure 105, a second dielectric material layer 108b above the first dielectric material layer 108a, and a third dielectric material layer 108c above the second dielectric material layer 108b. However, it should be understood that more or less than three dielectric material layers 108a, 108b, and 108c may be utilized. Figure 2 The first dielectric material layer 108a, the second dielectric material layer 108b, and the third dielectric material layer 108c shown in the figure may include suitable dielectric materials as described above. The first dielectric material layer 108a, the second dielectric material layer 108b, and the third dielectric material layer 108c may have the same composition or may have different compositions. In a non-limiting embodiment, the first dielectric material layer 108a and the third dielectric material layer 108c may have the same composition, and the second dielectric material layer 108b may have different compositions. The second dielectric material layer 108b may be the etch stop layer described above.

[0053] refer to Figure 2 , the first metal bonding pad 111 and the first bonding via 113 can be formed by forming a plurality of openings in one or more dielectric material layers 108 of the first bonding layer 109 and depositing a metal material within the openings, such as via a damascene or dual damascene process. This can include, for example, implementing one or more etching processes through a photolithographically patterned mask to form openings in one or more dielectric material layers 108; and depositing a suitable metal material within the opening to form the first metal bonding pad 111 and / or the first bonding via 113. An optional planarization process can be used to remove excess conductive material from above the planar upper surface 112 of the first bonding layer 109. The first metal bonding pad 111 and the first bonding via 113 may include a suitable conductive material, such as copper (Cu), tungsten (W), aluminum (Al), etc. The first metal bonding pad 111 and the first bonding via 113 can be formed using a suitable deposition process, such as, for example, physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), electrochemical deposition (e.g., electroplating), or a combination thereof.

[0054] Reference again Figure 2The plurality of first metal bonding pads 111 may be laterally surrounded by the dielectric material layer 108 of the first bonding layer 109 . At least some of the first metal bonding pads 111 may be electrically coupled to the underlying metal feature 107 of the interconnect structure 105 via first bonding vias 113 .

[0055] Figure 3 1 is a vertical cross-sectional view of the semiconductor wafer 100, showing the protective layer 114 located above the upper surface of the first bonding layer 109 according to various embodiments of the present disclosure. Figure 3 , the protective layer 114 can be configured to protect selected areas of the semiconductor wafer 100 from damage during a subsequent plasma cutting step, which will be further described below. The protective layer 114 can be patterned so that the protective layer 114 can cover a central area of ​​the unit area (UA) and can include an opening through the protective layer 114 near the periphery of the UA. The protective layer 114 can be deposited as a continuous layer over the first metal bonding pad 111 and the first bonding layer 109, and can be patterned to form a plurality of openings through the protective layer 114. In some embodiments, the protective layer 114 can be composed of a polymer-based material, such as a photosensitive material (e.g., a photoresist material) that can be patterned using photolithography techniques. Other suitable materials can be used for the protective layer 114.

[0056] Figure 4A 1 is a vertical cross-sectional view of a semiconductor wafer 100 showing a plurality of openings 115 in a first bonding layer 109 according to various embodiments of the present disclosure. Figure 4A In various embodiments, a plasma cutting process may be used to remove the portion of one or more dielectric material layers 108 of the first bonding layer 109 exposed by the opening in the protective layer 114. The opening 115 may be used as a cutting path or "road" that may extend around the periphery of the unit area (UA) of the semiconductor wafer 100. Plasma cutting is a dry etching process that uses plasma to selectively etch away the target material. In a non-limiting embodiment, the plasma cutting process may include a pulse or time-division multiplexing process that alternates between an isotropic etching process (e.g., using sulfur hexafluoride (SF6) plasma) and a thin passivation layer (e.g., using octafluorocyclobutane (C4F8) plasma) deposited above the etching surface. During the subsequent etching process, the directional ions erode and remove the passivation layer and the underlying material from the surface perpendicular to the incident ions, while the passivation layer protects the sidewall surface from etching. Repeating these etching and deposition steps multiple times can provide a highly directional etching that can produce steep, almost vertical sidewalls. After the plasma etching process, the protective layer 114 may be removed using a suitable process, such as by ashing or dissolution using a solvent.

[0057] In various embodiments, plasma cutting can achieve shorter process times, reduced device damage, and lower particle generation than other similar techniques (such as mechanical blade and / or laser cutting processes). In addition, plasma cutting can achieve improved precision and control of the size and shape of the opening 115 formed in the first bonding layer 109. Referring again to Figure 4A , the opening 115 formed by the plasma cutting process can have a groove-like shape, including a recessed surface 118 and an inner sidewall 117 extending between the recessed surface 118 and the flat upper surface 112 of the first bonding layer 109. Various parameters of the plasma etching process, such as plasma power, the specific plasma gas utilized, the etching selectivity of the material of the first bonding layer 109, the size and position of the opening through the protective layer 114, etc., can be selected and controlled to control the size and shape of the opening 115. As discussed in further detail below, controlling the size and shape of the opening 115 can help improve stress distribution and reduce crack defects in the bonded device structure that will be formed later.

[0058] Although Figure 4A An opening 115 is shown extending through the first bonding layer 109 to the dielectric material 106 of the interconnect structure 105, but it should be understood that in other embodiments, the opening 115 may not extend completely through the first bonding layer 109, or the opening 115 may extend into the dielectric material 106 of the interconnect structure 105 and / or into the first semiconductor substrate 101. Figure 4B is a vertical cross-sectional view of the semiconductor wafer 100 according to another embodiment, wherein the opening 115 extends through the third dielectric material layer 108 c and the second dielectric material layer 108 b and exposes the first dielectric material layer 108 a of the first bonding layer 109 .

[0059] Figure 5 is a vertical cross-sectional view of the semiconductor wafer 100 after a thinning process of removing a backside portion of the first semiconductor substrate 101 according to various embodiments of the present disclosure. Figure 5 In some embodiments, a thinning process may be performed to remove a backside portion of the first semiconductor substrate 101 of the semiconductor wafer 100. The thinning process may include, for example, a grinding process. In various embodiments, a grinding device may be used to mechanically grind the backside surface 103 of the first semiconductor substrate 101 to remove material from the backside of the first semiconductor substrate 101 and reduce the thickness of the first semiconductor substrate 101. In some embodiments, the thinning process on the first semiconductor substrate 101 may expose one or more conductive through-hole structures (e.g., through-substrate vias (TSVs)) in the backside surface 103 of the first semiconductor substrate 101. Figure 5 not shown). Figure 51 shows an embodiment in which the opening 115 through the first bonding layer 109 extends partially through the first bonding layer (ie, through the third dielectric material layer 108c and the second dielectric material layer 108b), as shown in FIG. Figure 4B As shown in FIG. 1 , it should be understood that in other embodiments, the opening 115 may extend through the entire first bonding layer 109, such as Figure 4A as shown in .

[0060] Figure 6 1 is a vertical cross-sectional view of semiconductor wafer 100 showing a plurality of trenches 119 formed through interconnect structure 105 according to various embodiments of the present disclosure. Figure 6 , a laser grooving process may be performed to remove portions of the interconnect structure 105, including the dielectric material 106 and any metal features 107, from around the periphery of the unit area (UA). The laser grooving process may include directing a high energy laser beam at selected areas of the semiconductor wafer 100, resulting in localized heating and vaporization of the irradiated area. This may allow the formation of Figure 6 1. The local trench or groove 119 shown in FIG. 119 can extend through the entire interconnect structure 105 so that the first semiconductor substrate 101 can be exposed at the bottom of the trench 119. In some embodiments, the trench 119 can further extend partially into the first semiconductor substrate 101. The trench 119 can laterally surround each of the UAs of the semiconductor wafer 100. The laser grooving process can "pre-cut" the individual UAs before performing the final cutting process through the entire thickness of the first semiconductor substrate 101 to form individual IC dies. Performing the pre-cutting of the UAs before the final cutting can achieve a cleaner cutting process with fewer sawing defects.

[0061] Reference again Figure 6 , a laser grooving process may be performed between adjacent pairs of openings 115 in the semiconductor wafer 100. The laser grooving process may remove a portion of the first bonding layer 109 that is located between each adjacent pair of openings 115 and defines one of the sidewalls 117 of the corresponding opening 115. Thus, the laser grooving process may remove one of the sidewalls 117 of each of the openings 115. The grooves 119 formed via the laser grooving process may be offset relative to the remaining sidewalls 117 of each of the openings 115 described above within each UA. Thus, after the laser grooving process, at least a portion of the recessed surface 118 of the opening 115 may remain between the groove 119 and the remaining sidewall 117 of the opening 115. Each UA may include a mesa structure 116 that includes a flat upper surface 112 and a sidewall 117 extending between the flat upper surface 112 and the recessed surface 118. The recessed surface 118 may laterally surround the mesa structure 116 and may extend between the mesa structure 116 and the groove 119 surrounding the periphery of the UA.

[0062] Figure 7 is a vertical cross-sectional view of an integrated circuit (IC) die 120 according to various embodiments of the present disclosure. Figure 7 , the semiconductor wafer 100 may be subjected to a cutting process. In various embodiments, the cutting process may be a mechanical cutting process using a blade such as a diamond or carbide blade to cut (e.g., saw) through the semiconductor wafer 100, including through the first semiconductor wafer 100. The cutting may be performed along the pre-cut grooves 119 described above, so that the independent UAs may be separated from the semiconductor wafer 100 to provide Figure 7 Each of the IC dies 120 may include a side surface 124 extending between the backside surface 103 of the first semiconductor substrate 101 and the recessed surface 118; and a mesa structure 116 including a planar upper surface 112 and a sidewall 117 extending between the planar upper surface 112 and the recessed surface 118.

[0063] Reference again Figure 7 , IC die 120 may include any type of die, including a functional die (e.g., a logic die, a memory die, an analog die, an RF die, an integrated passive device (IPD) die, etc., including various combinations thereof). In other embodiments, IC die 120 may be a non-functional or "dummy" die, which may include, for example, a metal interconnect structure above a semiconductor substrate, which may be used to route signals within a bonded device structure to be formed subsequently.

[0064] Figure 8 is a vertical cross-sectional view showing IC die 120 bonded to carrier structure 140 to form bonded device structure 130 according to various embodiments of the present disclosure. Figure 8 , the IC die 120 may be relative to the Figure 7 The orientation shown in is inverted (i.e., flipped) such that the planar upper surface 112 of the first bonding layer 109 faces downward and the back side 103 of the first semiconductor substrate 101 faces upward. The IC die 120 can be aligned over the carrier structure 140. The carrier structure 140 may include, for example, another IC die, a semiconductor wafer, an interposer, and / or a substrate (e.g., a semiconductor, glass, or organic substrate) that can be configured to support the IC die 120. The carrier structure 140 may include a first surface 147 facing the IC die 120 (i.e., a front side surface 147) and a second surface 148 opposite the first surface 147 (i.e., a back side surface 148). Figure 8In the embodiment shown in , the carrier structure 140 may include a metal interconnect feature 144 extending through the thickness of the carrier structure 140. The metal interconnect feature 144 may be electrically coupled to a bonding structure 146 (e.g., a bonding pad) on a backside surface 148 of the carrier structure 140. The bonding structure 146 may enable the device structure 140 to be bonded to another supporting structure, such as a package substrate or a printed circuit board (PCB), such as via a solder connection.

[0065] The carrier structure 140 may additionally include a second bonding layer 141. The second bonding layer 141 may be similar to the first bonding layer 109 described above. In particular, the second bonding layer 141 may include one or more dielectric material layers 145 composed of a suitable dielectric material as described above. The upper surface of the uppermost dielectric material layer 145 of the second bonding layer 141 may form a front side surface 147 of the carrier structure 140. A plurality of second metal bonding pads 142 may be formed within the dielectric material layer 145 of the second bonding layer 141. Each of the second metal bonding pads 142 may be laterally surrounded by the dielectric material layer 145. The upper surface of the second metal bonding pads 142 may be exposed on the front side surface 147 of the carrier structure 140. At least some of the second metal bonding pads 142 may be electrically coupled to the underlying metal interconnection features 144 of the carrier structure via second bonding vias 143.

[0066] The layout of the second metal bonding pads 142 of the second bonding layer 141 may correspond to the layout of the first metal bonding pads 111 of the first bonding layer 109. The IC die 120 may be aligned over the carrier structure 140 such that each first metal bonding pad 111 of the first bonding layer 109 may be aligned with a corresponding second metal bonding pad 142 of the second bonding layer 141.

[0067] Reference again Figure 8In various embodiments, the first bonding layer 109 may be bonded to the second bonding layer 141 via metal-to-metal (MM) and dielectric-to-dielectric (DD) direct bonding techniques to mechanically and electrically couple the IC die 120 to the carrier structure 140. In some embodiments, before bonding the IC die 120 to the carrier structure 140, the surface of the first bonding layer 109 on the IC die 120 and / or the second bonding layer 141 on the carrier structure 140 may be optionally subjected to a pre-treatment process (e.g., a plasma treatment process) to promote surface activation of the first bonding layer 109 and / or the second bonding layer 141 before bonding the IC die 120 to the carrier structure 140. To perform the bonding process, the IC die 120 and the carrier structure 140 may be put together so that the first bonding layer 109 of the IC die 120 contacts the second bonding layer 141 of the carrier structure 140. The IC die 120 and the carrier structure 140 may be aligned such that the first metal bonding pad 111 of the first bonding layer 109 contacts the corresponding second metal bonding pad 142 of the second bonding layer 141, and the dielectric material of the first bonding layer 109 contacts the dielectric material of the second bonding layer 141. In a direct bonding process, such as metal-to-metal (MM) and dielectric-to-dielectric (DD) bonding processes, contacting the first bonding layer 109 and the second bonding layer 141 to each other may produce a pre-bonding process, wherein chemical bonds (e.g., hydrogen bridge bonds) may be formed at a planar interface between the dielectric material of the first bonding layer 109 and the dielectric material of the second bonding layer 141. In some embodiments, the pre-bonding process may be performed at ambient temperature (e.g., ~20° C.). In other embodiments, the pre-bonding process may be performed at an elevated temperature. In some embodiments, during the pre-bonding process, a compressive force may be applied to the IC die 120 and the carrier structure 140. In other embodiments, no compressive force may be applied during the pre-bonding process.

[0068] Reference again Figure 8 In some embodiments, an annealing process may be performed to complete the bonding of the first metal bonding pad 111 of the first bonding layer 109 to the second metal bonding pad 142 of the second bonding layer 141 according to various embodiments of the present disclosure. The annealing process may be performed at an elevated temperature, such as 100° C. or higher, such as between about 150° C. and about 350° C., although lower and higher temperatures may also be utilized. In some embodiments, during the annealing process, a compressive force may be applied to the IC die 120 and the carrier structure 140. In other embodiments, no compressive force may be applied during the annealing process.

[0069] After the bonding process, the bonded device structure 130 may include the IC die 120 mechanically and electrically coupled to the underlying carrier structure 140. Figure 8As shown in FIG. 1 , the flat upper surface 112 (see FIG. 1 ) of the mesa structure 116 of the IC die 120 Figure 7 ) can contact and can be bonded to the front side surface 147 of the carrier structure 140. The recessed surface 118 (see FIG. 1 ) of the IC die 120 Figure 7 ) may be vertically offset relative to the front side surface 147 of the carrier structure 140. Figure 8 As shown in , the portion of the IC die 120 located around the periphery of the IC die 120 can overhang the front side surface 147 of the carrier structure 140. The portion of the IC die 120 overhanging the front side surface 147 of the carrier structure 140 can be referred to as an "eave" 121. The recessed surface 118, the sidewall surface 117 of the mesa structure 116, and the surface on which the IC die 120 is mounted (i.e., Figure 8 The space below the eaves 121 between the front side surface 147 of the carrier structure 140 in the embodiment of the present invention can be referred to as a "bay" region 126. Controlling various characteristics of the bay region 126 located below the eaves 121, such as the size and shape of the bay region 126, can help improve stress distribution, reduce crack defects, and promote adhesion of one or more protective films over the exposed surface of the bonded device structure 130, as described in further detail below.

[0070] Fig. 9 is a vertical cross-sectional view of a bonded device structure 130 including a protective film 150 over an exposed surface of the bonded device structure 130 according to various embodiments of the present disclosure. Fig. 9 , at least one protective film 150 may be conformally deposited over the exposed surfaces of the bonded device structure 130 (including the front side surface 147 of the carrier structure 140, the side surface 124 of the IC die 120, the back side surface 103 of the first semiconductor substrate 101), and over the sidewall surface 117 and the recessed surface 118 within the bay region 126 under the eaves 121. In various embodiments, the at least one protective film 150 may be composed of a suitable dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SIC) and / or silicon carbonitride (SICN). Other suitable materials, including oxide, nitride and / or carbide materials, may be used for the at least one protective film 150. The at least one protective film 150 may be deposited using a suitable deposition method as described above.

[0071] Although Fig. 9At least one protective film 150 is shown deposited over a bonded device structure 130 including an IC die 120 bonded to a carrier structure 140, but in other embodiments, the at least one protective film 150 may be deposited over the IC die 120 before the IC die 120 is bonded to the carrier structure 140 to form the bonded device structure 130. In such embodiments, the first bonding layer 109 may be masked to prevent the at least one protective film 150 from being deposited over the planar upper surface 112 of the first bonding layer 109 that is subsequently bonded to the carrier structure 140. Alternatively, the at least one protective film 150 may be deposited over all exposed surfaces of the IC die 120 and removed from selected surfaces, such as the planar upper surface 112, via etching or another suitable process.

[0072] Fig.10 is a vertical cross-sectional view of the bonded device structure 130 after a grinding process to remove the protection film 150 from over the backside surface 103 of the first semiconductor substrate 101 of the IC die 120 according to various embodiments of the present disclosure. Fig.10 , an optional mechanical grinding process may be performed to remove the at least one protective film 150 from over the backside surface 103 of the first semiconductor substrate 101. After the grinding process, the at least one protective film 150 may remain over the frontside surface 147 of the carrier structure 140, the side surface 124 of the IC die 120, and in the bay area 126. In other embodiments, the grinding step may be omitted, and the at least one protective film 150 may remain over the backside surface 103 of the first semiconductor substrate 101 of the IC die 120.

[0073] Fig.11 1 is a vertical cross-sectional view of the bonded device structure 130 showing the molded portion 151 surrounding the IC die 120 according to various embodiments of the present disclosure. Fig.11 , the molded portion 151 can be formed over the front side surface 147 of the carrier structure 140, over the back side surface 103 of the first semiconductor substrate 101, over the side surface 124 of the IC die 120, and within the bay area 126 located below the eaves 121. In a location where there is at least one protective film 150, the molded portion 151 can be formed over the at least one protective film 150 and can contact the at least one protective film 150. In various embodiments, the molded portion 151 may include an epoxy material. For example, the molded portion 151 may include an epoxy molding compound (EMC), which may include an epoxy resin, a hardener (i.e., a curing agent), silicon dioxide or other filling materials, and optionally additional additives. The EMC can be applied around the periphery of the IC die 120 in liquid or solid form, and can be hardened (i.e., cured) to form a molded portion 151 having sufficient rigidity and mechanical strength around the IC die 120. Although Fig.11 The molded portion 151 is shown positioned above the backside surface 103 of the first semiconductor substrate 101, but in other embodiments, a planarization process (such as a chemical mechanical planarization (CMP) process) may be used to remove the portion of the molded portion 151 extending above a horizontal plane including the backside surface 103 of the first semiconductor substrate 101.

[0074] Fig.12 is a vertical cross-sectional view of a bonded device structure 130 having a multi-layer configuration according to various embodiments of the present disclosure. Fig.12 , the bonded device structure 130 includes a first IC die 120a bonded to the front side surface 147 of the carrier structure 140, and a second IC die 120b located above the first IC die 120a and bonded to the first IC die 120a. The first IC die 120a and the second IC die 120b can be similar to the above reference Figures 8 to 11 The IC die 120 described above is shown in FIG. 1 . Therefore, for the sake of brevity, repeated discussion of the same elements is omitted. The first IC die 120a and the second IC die 120b can be the same type of die (e.g., a logic die, a memory die, a "dummy" die, etc.) or can be different types of dies. Fig.12 In the embodiment shown in , the front side of the second IC die 120b can be bonded to the backside surface 103 of the first semiconductor substrate 101 of the first IC die 120a in a "front to back" configuration. The second IC die 120b can be bonded to the first IC die 120a via a bonding portion 157, which can be formed using MM and DD direct bonding techniques as described above. Through substrate vias 153 (TSVs) can extend through the first semiconductor substrate 101 and can be used to transmit signals between the second semiconductor IC die 120b and devices and / or interconnect components located above the frontside surface 102 of the first semiconductor substrate 101. The first IC die 120a and the second IC die 120b can both include an eave 121, wherein the bay area 126 is located below the eave 121. In the example of the second IC die 120b, the eave 121 can include a portion of the second IC die 120b that overhangs the first IC die 120a. At least one protective layer 150 may be located over surfaces of the first IC die 120a and the second IC die 120b. A molding portion 151 may laterally surround the first IC die 120a and the second IC die 120b and may extend within the bay area 126 located below the eaves 121.

[0075] In various embodiments, the IC dies 120 mounted directly to the front side surface 147 of the carrier structure 140 may be referred to as a first layer of IC dies 120. Additional IC dies 120 mounted above the first layer of IC dies 120 may be referred to as a second layer of IC dies 120, and so on. Fig.12 The embodiment shown in includes two layers of IC dies 120 above a carrier structure 140 , but it should be understood that the bonded device structure 130 according to various embodiments may have N layers, where N is an integer ≥ 1 (ie, N=1, 2, 3, 4 . . . ).

[0076] Fig.13A is a vertical cross-sectional view of a bonded device structure 130 having a multi-layer configuration according to another embodiment of the present disclosure. Fig. 13B yes Fig.13A An enlarged vertical cross-sectional view of region B. Fig. 13C yes Fig.13A An enlarged vertical cross-sectional view of region C. Fig.13A , Fig.13A The bonding device structure 130 is similar to the above reference Fig.12 The described bonding device structure 130. Therefore, for the sake of brevity, repeated discussion of the same elements is omitted. Fig.13A The bonded device structure 130 does not include the protective film 150 described above, but is otherwise equivalent to Fig.12 The bonding device structure 130 is provided.

[0077] Fig. 13B yes Fig.13A FIG. 1 is an enlarged vertical cross-sectional view of region B of FIG. 1 , showing the eave 121 and the bay area 126 located below the eave 121. For clarity of illustration, Fig. 13B The molding portion 151 is not shown. As mentioned above, various characteristics of the bay area 126 located below the eaves 121 of the IC die 120 can be designed to provide improved device yield and performance.

[0078] refer to Fig. 13B , the width dimension W of the bay area 126 may be defined as W1*0.5+W2*0.5, where W1 is the horizontal width of the eaves 121 defining the top surface of the bay area 126, and W2 is the horizontal width of the bay area 126 on the bottom surface of the bay area 126. Similarly, the height dimension H of the bay area 126 may be defined as H1*0.5+H2*0.5, where H1 is the vertical inner height of the bay area 126 on the inner side of the bay area 126 (i.e., Fig. 13B117 ), and H2 is the vertical outer height of the bay area 126 on the outer side of the bay area 126 (i.e., the side of the bay area 126 defined by the peripheral edge of the eaves 121). In other words, the width dimension W can be defined as the average of the horizontal width dimensions of the bay area 126 along the top and bottom surfaces of the bay area 126 (i.e., (W1+W2) / 2), and the height dimension H can be defined as the average of the vertical height dimensions of the bay area 126 on the inner and outer sides of the bay area 126 (i.e., (H1+H2) / 2). The aspect ratio of the bay area 126 can be defined as the width divided by the height, or W / H. During the plasma cutting, laser slotting, and cutting processes described above for forming the IC die 120, the aspect ratio of the bay area 126 can be controlled. In various embodiments, the aspect ratio of the bay area 126 can be ≥1, such as ≥1 and ≤80. Aspect ratios in the range of 1 to 80 can provide effective stress distribution, bonding of the protective film 150, and minimize crack defects, while also enabling sufficient filling of the molding compound. In some embodiments, all IC dies 120 bonded to the device structure 130 can include an eave 121 as described above, and each of the bay regions 126 located under the corresponding eave can have an aspect ratio of ≥1 and ≤80.

[0079] Reference again Fig. 13B Another characteristic of the eaves 121 and the underlying bay region 126 that can be controlled is the angle θ1 between the inner sidewalls 117 and the top surface 118 of the bay region 126. The angle θ1 can be controlled at least in part by controlling the parameters of the plasma cutting process used to form the inner sidewalls 117 of the mesa structure 116 and the recessed surface 118 of the IC die 120, as described above with reference to FIG. 4A to FIG. 7 Described. In various embodiments, θ1 may be at least 10°. In some embodiments, θ1 may be greater than 10° and less than or equal to 170°. In some embodiments, values ​​of θ1 of ≥10° and ≤170° may provide effective stress distribution, minimize crack defects, while also enabling one or more protective films 150 to be well bonded above the surface of the bay region 126. In some embodiments, all IC dies 120 bonded to the device structure 130 may include an eaves 121 as described above, wherein the angle θ1 between the inner sidewall 117 and the top surface 118 of the bay region 126 located below the corresponding eaves may be ≥10° and ≤170°.

[0080] Another characteristic of the eaves 121 and the underlying bay region 126 that can be controlled is the angle θ2 between the inner sidewalls 117 and the bottom surface 147 of the bay region 126. For an IC die 120 in a first layer of bonded device structure 130, the bottom surface 147 of the bay region 126 can be the front side surface 147 of the carrier structure 140. For an IC die in a higher layer (i.e., layer N, where N ≥ 2), the bottom surface 147 of the bay region 126 can be the upper surface of the underlying layer (i.e., layer N-1). This angle θ2 can be controlled at least in part by controlling the parameters of the plasma cutting process used to form the inner sidewalls 117 of the mesa structure 116, as described above with reference to FIG. 4A to FIG. 7 Described. In various embodiments, θ2 may be at least 10°. In some embodiments, θ2 may be greater than 10° and less than or equal to 170°. In some embodiments, values ​​of θ2 of ≥10° and ≤170° may provide effective stress distribution, minimize crack defects, while also enabling one or more protective films 150 to be well bonded above the surface of the bay region 126. In some embodiments, all IC dies 120 bonded to the device structure 130 may include an eaves 121 as described above, wherein the angle θ2 between the inner sidewall 117 and the bottom surface 147 of the bay region 126 located below the corresponding eaves may be ≥10° and ≤170°.

[0081] Reference again Fig. 13B , another characteristic that can be controlled is the horizontal width dimension W1 of the eaves 121. The horizontal width dimension W1 of the eaves 121 can be expressed as L1*cos(θ1+θ2-180°), where L1 is the length of the lower surface of the top surface 118 of the eaves 121 that forms the bay area 126. The horizontal width dimension W1 of the eaves 121 can be controlled during the plasma cutting, laser slotting, and cutting processes described above for forming the IC die 120. In various embodiments, the horizontal width W1 of the eaves 121 can be ≤100μm. In some embodiments, a value of W1 of ≤100μm can provide effective stress distribution, minimize crack defects, while also enabling one or more protective films 150 to be well bonded above the surface of the bay area 126. In instances where the eaves 121 has an excessively large horizontal width dimension W1, it may be difficult to fill the bay area 126 with a molding compound, which may result in poor reliability of the bonded device structure 130. In some embodiments, all IC dies 120 bonded to device structure 130 may include eaves 121 having a horizontal width dimension W1 of ≤ 100 μm.

[0082] In some embodiments, the horizontal width dimension W1 of the eaves 121 may also be at least partially a function of the thickness of the IC die 120. Fig.13A and Fig. 13B, the IC die 120 may have a thickness dimension T along the side surface 124 of the IC die 120. In various embodiments, the horizontal width dimension W1 of the eaves 121 may be <1 / 100*T. In some embodiments, the width dimension W1 of the eaves 121 that is less than one percent of the thickness dimension T of the IC die 120 may provide effective stress distribution, minimize crack defects, while also enabling one or more protective films 150 to be well bonded above the surface of the bay area 126. In instances where the eaves 121 has a horizontal width dimension W1 that is equal to 1 / 100 or more of the thickness dimension T, the bonding stress may be too high, which may be detrimental to bonding. In some embodiments, all IC dies 120 bonded to the device structure 130 may include eaves 121 having a horizontal width dimension W1 that is <1 / 100 of the thickness dimension T of the corresponding IC die 120.

[0083] Reference again Fig. 13B , another characteristic that can be controlled is the horizontal width dimension W2 of the bottom surface of the bay area 126. During the plasma cutting, laser slotting and cutting processes described above for forming the IC tube core 120, the horizontal width dimension W2 of the bottom surface of the bay area 126 can be controlled. In various embodiments, the horizontal width W2 of the bottom surface of the bay area 126 can be between 0.5 and 1.5 times the horizontal width dimension W1 of the eaves 121 described above. In some embodiments, the value of W1 of ≥0.5*W1 and ≤0.5*W1 can provide effective stress distribution, minimize crack defects, while also enabling one or more protective films 150 to be well bonded above the surface of the bay area 126. In some embodiments, all IC tube cores 120 bonded to the device structure 130 can include the horizontal width dimension W2 of the bottom surface of the bay area 126, W2 ≥0.5*W1 and ≤0.5*W1.

[0084] Reference again Fig.13A and Fig. 13B , another characteristic that can be controlled is the vertical inner height dimension H1 of the bay region 126. In various embodiments, the vertical inner height dimension H1 of the bay region 126 can be less than half of the thickness dimension T of the IC die 120. In some embodiments, a vertical inner height dimension H1 of the bay region 126 <0.5*T can provide effective stress distribution, minimize crack defects, while also enabling one or more protective films 150 to be well bonded above the surface of the bay region 126. In instances where the vertical inner height dimension H1 is too large relative to the thickness T of the IC die 120, the bonding of one or more protective films 150 may be poor. In some embodiments, all IC dies 120 bonded to the device structure 130 may include a bay region having a vertical inner height dimension H1 that is less than half of the thickness dimension T of the corresponding IC die 120.

[0085] In some embodiments, the bay region 126 may have a minimum vertical inner height dimension H1. In some embodiments, the minimum vertical inner height dimension H1 may be at least about 1 μm. Alternatively or additionally, the minimum vertical inner height dimension H1 may be at least about 1 / 200*T. In various embodiments, keeping the vertical inner height dimension H1 at or above the minimum distance may enable the molding compound to fully fill the bay region 126 with the molding compound, which improves the reliability of the bonded device structure 130.

[0086] Fig. 13C yes Fig.13A FIG. 1 is an enlarged vertical cross-sectional view of region C of FIG. 1 , showing molded portion 151. In some embodiments, the properties of molded portion 151 can be designed to provide improved device yield and performance. One property of molded portion 151 that can be controlled is void fraction. Fig. 13C , molded portion 151 is generally not a completely solid material, but generally includes void regions 155 within molded portion 151 that do not include molding compound. Void fraction can be defined as the total volume of voids 155 divided by the total volume of solid molding compound within molded portion 151. Void fraction can be controlled in part by controlling the process conditions used to form molded portion 151. For example, void fraction can be controlled in part by selecting a curing temperature and a heating rate of a molding process used to form molded portion 151.

[0087] In various embodiments, the void ratio of the molded portion 151 may be between 0.2 and 0.4. A void ratio of the molded portion 151 of ≥0.2 and ≤0.4 may provide effective mechanical support, good adhesion to the surrounding structure, reduced stress, and good thermal matching. A molded portion 151 with too high a void ratio may not provide sufficient mechanical support and / or protection for the various components of the device structure 130 being bonded. A molded portion 151 with too low a void ratio may be too dense, which may cause a mismatch with the large coefficient of thermal expansion (CTE) of the surrounding structure, which may result in poor adhesion of the molded portion 151.

[0088] Fig.14A is a vertical cross-sectional view of a bonded device structure 130 having a multi-layer configuration according to an embodiment of the present disclosure. Fig. 14B yes Fig.14A FIG. 1 is a top view of the first IC die 120 a of the bonded device structure 130 . Fig. 14C yes Fig.14A An enlarged vertical cross-sectional view of region D of FIG. Fig.14D According to another embodiment of the present disclosure Fig.14A An enlarged vertical cross-sectional view of region D of FIG. Fig.14A , Fig.14A The bonding device structure 130 is similar to the above reference Fig.12 and Fig.13A The described bonding device structure 130. Therefore, for the sake of brevity, repeated discussion of the same elements is omitted. Fig.14A The bonded device structure 130 includes the protective film 150 described above located above the side surface 124 and within the bay area 126 below the eaves 121 in each of the IC die 120a and 120b. Providing at least one protective film 150 above the surface of the IC die 120 can help improve the adhesion between the molded portion 151 and the IC die 120, and can also help reduce thermal stress, which may cause undesirable crack formation. As noted above, suitable materials for at least one protective film 150 may include, for example, SiO, SiN, SiON, SIC, SICN, etc. Other suitable materials for at least one protective film 150 may also be utilized. A single protective film 150 may be used, or, as described in further detail below, multiple protective films 150 may be located above selected surfaces of the IC die 120. Multiple protective films 150 may have the same composition, or different protective films 150 may have different compositions.

[0089] Fig. 14B is a top view of the first IC die 120a. Fig.14A and Fig. 14B The area between the dotted line in FIG. 1 and the periphery of the first IC die 120 a schematically illustrates a “keep out zone” 160 (KOZ) of the first IC die 120 a. The KOZ 160 is an area of ​​the IC die 120 (or of the UA in the semiconductor wafer 100 before singulation) that cannot be used to form device structures due to thermal management components, cooling, and mounting restrictions. The KOZ 160 is typically located around the periphery of the IC die 120, such as Fig.14A and Fig. 14B. In various embodiments, it may be advantageous to utilize one or more protective films 150 over the surface of the IC die 120, such as over the side surface 124 of the IC die 120 and within the bay area 126, when the KOZ 160 of the IC die 120 is relatively small. This may help avoid cracks extending into portions of the IC die 120 that include device structures that may be damaged by the cracks. In contrast, when the KOZ 160 of the IC die 120 is larger, crack formation may be limited to the KOZ 160 of the IC die 120, such that the device structures may not be damaged. In such instances, the protective film 150 may be omitted in some embodiments. In some embodiments, when the KOZ 160 of the IC die 120 is ≤20 μm, one or more protective films 150 may be utilized. In embodiments where the KOZ 160>20 μm, the protective film 150 may not be utilized in some instances. The protective film 150 may be applied before the IC dies 120 a , 120 b are bonded over the carrier structure 140 to form the bonded device structure 130 , or may be applied after the IC dies 120 a , 120 b are bonded over the carrier structure 140 to form the bonded device structure 130 .

[0090] Fig. 14C yes Fig.14A FIG. 1 is an enlarged vertical cross-sectional view of area D of FIG. 1 , showing a single protective film 150 over the first IC die 120 a . Fig.14D yes Fig.14A 1 is an enlarged vertical cross-sectional view of region D of , showing an optional embodiment in which a first protective film 150a, a second protective film 150b, and a third protective film 150c are located above the first IC die 120a. The materials of the first protective film 150a, the second protective film 150b, and the third protective film 150c may be the same or may be different. In some embodiments, the materials of the protective film 150 may be selected based on their compatibility with the molded portion 151 formed above the protective film 150. In some embodiments, when the aspect ratio (W / H) of the bay area 126 is relatively large, a single protective film 150 may be preferred, while when the aspect ratio of the bay area 126 is relatively small, multiple (e.g., two or three) protective films 150 may be utilized. In some embodiments, the total thickness of the protective film 150 may be less than half of the vertical inner height dimension H1 of the bay area 126.

[0091] FIG. 15A to FIG. 15H is a vertical cross-sectional view of the multi-layer bonded device structure 130 , illustrating different configurations of the protection film 150 according to various embodiments of the present disclosure. Fig.15AAn embodiment is shown in which a single protective film 150 is located above the first IC die 120a in the first layer and the second IC die 120b in the second layer. The protective film 150 is located above the side surface 124 and within the bay area 126 of the first IC die 120a, but is not present above the upper surface of the first IC die 120a. In contrast, the protective film 150 is located above the side surface 124, within the bay area 126, and above the upper surface of the second IC die 120b. Fig. 15B Shows something like Fig.15A The embodiment of the embodiment is different from the embodiment of the embodiment in that the protection film 150 is not located over the upper surface of the second IC die 120b.

[0092] Fig. 15C An embodiment is shown in which the first protective film 150a, the second protective film 150b, and the third protective film 150c are located above the first IC die 120a and the second IC die 120b. The first protective film 150a, the second protective film 150b, and the third protective film 150c are each located above the side surface 124 and within the bay area 126 of the first IC die 120a and the second IC die 120b, but are not located above the upper surface of the first IC die 120a or the second IC die 120b. Fig.15D shows a similar configuration, except that in Fig.15D , the first protection film 150a, the second protection film 150b, and the third protection film 150c are each located over the upper surface of the second IC die 120b.

[0093] Fig.15E An embodiment is shown in which the first protective film 150a, the second protective film 150b, and the third protective film 150c are located above the first IC die 120a and the single protective film 150 is located above the second IC die 120b. In this embodiment, the first protective film 150a, the second protective film 150b, and the third protective film 150c are located above the side surface and within the bay region of the first IC die 120a, but are not located above the upper surface of the first IC die 120. The single protective film 150 is located above the side surface, within the bay region, and above the upper surface of the second IC die 120b. Fig.15F Shows something like Fig.15E Another embodiment of the invention is different in that, in Fig.15F In the embodiment of FIG. 1 , the protective film 150 is not present over the upper surface of the second IC die 120 b .

[0094] Figure 15G and Fig.15H An embodiment is shown in which a single protective film 150 is located over the first IC die 120a and the first protective film 150a, the second protective film 150b, and the third protective film 150c are located over the second IC die 120b. Figure 15Gand Fig.15H In FIG. 1 , a single protective film 150 is located over the side surfaces and within the bay region of the first IC die 120 a , but is not located over the upper surface of the first IC die 120 a . Figure 15G In the embodiment shown in , the first protective film 150a, the second protective film 150b, and the third protective film 150c are each located above the side surface and within the bay region of the second IC die 120b, but are not located above the upper surface of the second IC die 120b. Fig.15H In the embodiment shown in FIG. 1 , the first protective film 150 a , the second protective film 150 b , and the third protective film 150 c are also located over the upper surface of the second IC die 120 b .

[0095] FIG. 16A to FIG. 16I 1 is a vertical cross-sectional view of a bonded device structure 130, illustrating different shapes of the bay region 126 located below the eave 121 according to various embodiments of the present disclosure. The shape of the bay region 126 can be defined in part by an angle θ1 between the inner sidewall 117 and the top surface 118 of the bay region 126, and an angle θ2 between the inner sidewall 117 and the bottom surface 147 of the bay region 126. The differences in these angles θ1 and θ2 can produce bay regions 126 of different shapes when viewed in a vertical cross-section. FIG. 16A to FIG. 16C An embodiment is shown where the sum of angles θ1 and θ2 equals 180°. In such an example, the top surface 118 and the bottom surface 147 of the bay region 126 are parallel to each other, and the bay region 126 may have a truncated parallelogram shape. Fig.16A An example of θ1>θ2 is shown, and Fig. 16B An example where θ1<θ2 is shown. Fig. 16C An example is shown where θ1=θ2 (ie, θ1 and θ2 are both 90°), in which the bay region 126 has a rectangular shape.

[0096] FIG. 16D to FIG. 16I An example is shown where the top surface 118 and the bottom surface 147 of the bay region 126 are not parallel, and the bay region 126 has an irregular polygonal shape. Fig.16D and Fig.16E An example of a bay region 126 having an irregular polygonal shape is shown, where θ2=90°, 0°<θ1<180°, and θ1≠θ2. Fig.16E An example of θ1>90° is shown, and Fig.16E An example where θ1<90° is shown.

[0097] Fig.16F and Figure 16G An example of a bay region 126 having an irregular polygonal shape is shown, where θ2>90°, 0°<θ1<180°, and θ1+θ2≠180°. Fig.16FAn example of θ1<90° is shown, and Figure 16G An example where θ1>90° is shown.

[0098] Fig.16H and Fig.16I An example of a bay region 126 having an irregular polygonal shape is shown, where θ2<90°, 0°<θ1<180°, and θ1+θ2≠180°. Fig.16H An example of θ1<90° is shown, and Fig.16I An example where θ1>90° is shown.

[0099] In the multi-layer bonded device structure 130 as described above, different IC dies 120a, 120b may include bay regions 126 having the same or different shapes. FIG. 17A to FIG. 17I is a vertical cross-sectional view of a multi-layer bonded device structure 130 showing various configurations of the shape of the bay regions 126 for IC dies 120 a , 120 b in different layers according to various embodiments of the present disclosure. 17A to 17C An example is shown where a first IC die 120a in a first layer and a second IC die 120b in a second layer include bay areas 126 having the same type of shape. Fig.17A An example is shown where both bay regions 126 have a truncated parallelogram shape. Fig. 17B An example is shown where both bay areas 126 have a rectangular shape. Fig. 17C An example is shown where both bay areas 126 have irregular polygonal shapes.

[0100] FIG. 17D to FIG. 17I An example is shown where a first IC die 120a in a first layer and a second IC die 120b in a second layer include bay areas 126 having different types of shapes. Fig.17D An example is shown where the bay area 126 of the first IC die 120a has a rectangular shape and the bay area 126 of the second IC die 120b has a truncated parallelogram shape. Fig.17E An example is shown where the bay area 126 of the first IC die 120a has an irregular polygonal shape and the bay area 126 of the second IC die 120b has a truncated parallelogram shape. Fig.17F An example is shown where the bay area 126 of the first IC die 120a has a truncated parallelogram shape and the bay area 126 of the second IC die 120b has a rectangular shape. Figure 17G An example is shown where the bay area 126 of the first IC die 120a has a rectangular shape and the bay area 126 of the second IC die 120b has an irregular polygonal shape. Fig.17HAn example is shown where the bay area 126 of the first IC die 120a has an irregular polygonal shape and the bay area 126 of the second IC die 120b has a rectangular shape. Fig.17I An example is shown where the bay area 126 of the first IC die 120a has a truncated parallelogram shape and the bay area 126 of the second IC die 120b has an irregular polygonal shape.

[0101] 18A to 18D is a top view of a bonding device structure 130 according to various embodiments of the present disclosure. 18A to 18D In some embodiments, one or more layers of the multilayer bonded device structure 130 may include multiple IC dies 120. For example, the first layer may include multiple first IC dies 120a bonded to the carrier structure 140. The multiple first IC dies 120a may be laterally spaced apart from each other, and the molded portion 151 described above may be located between adjacent first IC dies 120a. One or more second IC dies 120b may be bonded over the multiple first IC dies 120a to form a second layer. The molded portion 151 may laterally surround each of the one or more second IC dies 120b. Additional IC dies 120 may optionally be bonded over the one or more second IC dies 120b to form additional layers of the bonded device structure 130.

[0102] 18A to 18D An exemplary configuration of a bonded device structure 130 having two layers is shown. 18A to 18D The molded portion 151 is omitted. Fig.18A , the bonded device structure 130 may include four square-shaped first IC dies 120a having identical dimensions bonded to the carrier structure 140 to form a first layer. A single square-shaped second IC die 120b having dimensions greater than the dimensions of the first IC die 120a may be bonded over each of the first IC dies 120a and may be partially located above each of the first IC dies 120a to form a second layer. Fig.18E is along Fig.18A The line E-E' in Fig.18A A vertical cross-sectional view of the bonding device structure 130. Fig.18A and Fig.18EAs shown in , in some embodiments, the sidewalls of the second IC die 120b may not be vertically aligned with the corresponding sidewalls of the underlying first IC die 120a. In some embodiments, the sidewalls of the second IC die 120b may be laterally offset relative to the outer sidewalls of the first IC die 120a (i.e., not facing the sidewalls of the adjacent first IC die 120a) so that the eaves 121 of the second IC die 120b do not extend to or beyond the outer sidewalls of the underlying first IC die 120a. In other embodiments, the sidewalls of the second IC die 120b may be vertically aligned with the outer sidewalls of the underlying first IC die 120a, or may extend beyond the outer sidewalls of the underlying first IC die 120a. Fig.18B A similar configuration is shown where the first IC die 120a and the second IC die 120b each have a rectangular shape.

[0103] Fig.18C A bonded device structure 130 is shown including three first IC dies 120a bonded to a carrier structure 140 to form a first layer. The first IC dies 120a include a pair of square-shaped first IC dies 120a on one side of the carrier structure 140 and a larger rectangular-shaped first IC die 120a on the other side of the carrier structure 140. A single square-shaped second IC die 120b is bonded over and partially above each of the first IC dies 120a to form a second layer.

[0104] Fig.18D A bonded device structure 130 is shown including four square-shaped first IC dies 120a of identical dimensions bonded to a carrier structure 140 to form a first layer. A single rectangular-shaped second IC die 120b is bonded over and partially above each of the first IC dies 120a to form a second layer.

[0105] Various other arrangements of the multi-layer bonded device structure 130 may be utilized. For example, although 18A to 18D The embodiment shown in shows a first layer including multiple first IC die 120a and a second layer including a single second IC die 120b, but in other embodiments, the first layer may include a single first IC die 120a and the second layer may include multiple second IC die 120b, or both the first layer and the second layer may include multiple IC dies 120a, 120b.

[0106] Fig.19 is a flow chart illustrating a method 200 of manufacturing a bonded device structure 130 according to an embodiment of the present disclosure. Figure 1 , Figure 2 and Fig.19In step 201 of the method 200, a first bonding layer 109 may be formed over the semiconductor substrate 101. Figure 3 , Figure 4A , Figure 4B and Fig.19 In step 203 of method 200, a plasma cutting process may be performed to remove a portion of the first bonding layer 109 to form an opening 115 having a recessed surface 118 recessed relative to the planar upper surface 112 of the first bonding layer 109 and an inner sidewall 117 extending between the recessed surface 118 and the planar upper surface 112 of the first bonding layer 109. Figure 6 , Figure 7 and Fig.19 In step 205 of method 200 , a sawing process may be performed through semiconductor substrate 101 to provide IC die 120 . Figure 8 , Fig.13A , Fig. 13B and Fig.19 In step 207 of method 200, first bonding layer 109 may be bonded to surface 147 of carrier structure 140 to form bonded device structure 130, wherein planar upper surface 112 of first bonding layer 109 contacts surface 147 of carrier structure 140, IC die 120 includes eaves 121 above surface 147 of carrier structure 140, and bay region 126 is located between eaves 121 and surface 147 of carrier structure 140, and bay region 126 has a ratio of width dimension W to height dimension H of at least 1. Fig.11 , Fig.13A , Fig. 13C and Fig.19 In step 209 , a molding portion 151 may be formed laterally surrounding the IC die 120 and within the bay area 126 .

[0107] With reference to all the accompanying drawings and in accordance with various embodiments of the present disclosure, the bonding device structure 130 includes: a carrier structure 140; an integrated circuit (IC) die 120 bonded to a surface 147 of the carrier structure 140 via a first bonding layer 109, the IC die 120 including an eaves 121 above the surface 147 of the carrier structure 140, wherein a bay area 126 is located between the eaves 121 and the surface 147 of the carrier structure 140, and a ratio of a width dimension W to a height dimension H of the bay area 126 is at least 1; and a molded portion 151 laterally surrounding the IC die 120 and located within the bay area 126 between the surface 147 of the carrier structure 140 and the eaves 121.

[0108] In one embodiment, bay area 126 is located between lower surface 118 of eave 121 , surface 147 of carrier structure, and inner sidewall 117 extending between lower surface 118 of eave 121 and surface 147 of carrier structure 140 .

[0109] In another embodiment, the width dimension W of the bay area 126 is equal to the average of the horizontal width dimensions (W1, W2) of the bay area 126 along the top and bottom surfaces (118, 147) of the bay area 126, and the height dimension H of the bay area is equal to the average of the vertical height dimensions (H1, H2) of the bay area on the inner and outer sides of the bay area, and wherein the ratio of the width dimension W to the height dimension H of the bay area is equal to or less than 80.

[0110] In another embodiment, a first angle θ1 between the inner sidewall 117 and the lower surface 118 of the eave 121 is between 10° and 170°, and a second angle θ2 between the inner sidewall 117 and the surface 147 of the carrier structure 140 is between 10° and 170°.

[0111] In another embodiment, the horizontal width dimension W1 of the bay region 126 along the top surface 118 of the bay region 126 is equal to or less than 100 μm, the horizontal width dimension W2 of the bottom surface 147 of the bay region 126 along the bay region 126 is between 0.5 and 1.5 times the horizontal width dimension W1 of the bay region 126 along the top surface 118 of the bay region 126, and the vertical height dimension H1 of the bay region 126 on the inner side of the bay region 126 is equal to or greater than 1 μm.

[0112] In another embodiment, the IC die 120 has a thickness dimension T along the side surface 124 of the IC die 120, the horizontal width dimension W of the eaves is greater than 1 / 100 of the thickness dimension T of the IC die 120, and the vertical height dimension H1 of the bay area on the inner side of the bay area 126 is greater than 1 / 200 of the thickness dimension T of the IC die 120 and less than 1 / 2 of the thickness dimension T of the IC die 120.

[0113] In another embodiment, the bay region 126 has a rectangular, truncated parallelogram, or irregular polygonal shape in vertical cross-section.

[0114] In another embodiment, the bonded device structure 130 further includes: at least one protective film 150 located above the side surface 124 of the IC die and within the bay area 126 above the bottom surface 118 and the inner sidewall 117 of the eave 121 , and at least one protective film 150 located between the IC die 120 and the molded portion 151 .

[0115] In another embodiment, a ratio of the total volume of the voids 155 in the molded portion 151 to the total volume of the molding compound in the molded portion 151 is between 0.2 and 0.4.

[0116] In another embodiment, IC die 120 includes a logic die, a memory die, an analog die, an RF die, an integrated passive device (IPD) die, or a dummy die, and carrier structure 140 includes a substrate, an interposer, a semiconductor die, or a semiconductor wafer.

[0117] In another embodiment, the first bonding layer 109 of the IC die 120 includes a plurality of first metal bonding pads 111 formed within the dielectric material layer 108 and is bonded to corresponding bonding layers 141 of the carrier structure 140 via metal-to-metal and dielectric-to-dielectric direct bonding.

[0118] In another embodiment, the IC die includes a first IC die 120a, and the bonded device structure 130 also includes a second IC die 120b bonded above the first IC die 120a, the second IC die 120b includes an eaves 121 and a bay area 126 located below the eaves 121, and a ratio of a width dimension W to a height dimension H of the bay area 126 located below the eaves 121 of the second IC die 120b is at least 1, and the molded portion 151 laterally surrounds the second IC die 120b and is located within the bay area 126 below the eaves 121 of the second IC die 120b.

[0119] Another embodiment relates to a bonded device structure 130, comprising: a carrier structure 140; at least one integrated circuit (IC) die 120, bonded to a surface 147 of the carrier structure 140 via a first bonding layer 109, each IC die 120 comprising an eaves 121 above the surface 147 of the carrier structure 140, wherein a bay area 126 is located between the eaves 121 and the surface 147 of the carrier structure 140; and a molded portion 151, laterally surrounding the IC die 120 and located within the bay area 126 between the surface 147 of the carrier structure 140 and the eaves 121, and a ratio of a total volume of voids 155 in the molded portion 151 to a total volume of a molding compound in the molded portion 151 is between 0.2 and 0.4.

[0120] In one embodiment, the bonded device structure 130 includes a multi-layer bonded device structure 130, the multi-layer bonded device structure 130 includes a plurality of IC dies 120, wherein one or more first IC dies 120a bonded to a surface 147 of a carrier structure 140 form a first layer of IC dies, and one or more second IC dies 120b bonded above the first IC dies 120a form a second layer of IC dies, each of the first IC dies 120a and the second IC dies 120b include an eaves 121, wherein a bay area 126 is located below the eaves 121, and a molded portion 151 laterally surrounds each of the first IC dies 120a and the second IC dies 120b and is located within each of the bay areas 126 below the eaves 121 of the first IC dies 120a and the second IC dies 120b.

[0121] In another embodiment, the protection film 150 is provided over the surface of each IC die ( 120 a , 120 b ) having a keep-out area of ​​20 μm or less.

[0122] In another embodiment, the bay area 126 beneath the eaves of the one or more first IC dies 120a and the one or more second IC dies 120b has a non-uniform shape.

[0123] Another embodiment relates to a method of manufacturing a bonded device structure 130, the method comprising: forming a first bonding layer 109 over a semiconductor substrate 101; performing a plasma cutting process to remove a portion of the first bonding layer 109 and form an opening 115, the opening 115 having a recessed surface 118 recessed relative to a planar upper surface 112 of the bonding layer 109 and an inner sidewall 117 extending between the recessed surface 118 and the planar upper surface 112 of the bonding layer; performing a cutting process through the semiconductor substrate 101 to provide an IC die 120; separating the first bonding layer 109 from the semiconductor substrate 101; and removing the first bonding layer 109 from the semiconductor substrate 101. 109 is bonded to the surface 147 of the carrier structure 140 to form a bonded device structure 130, wherein the flat upper surface 112 of the bonding layer 109 contacts the surface 147 of the carrier structure 140, the IC die 120 includes an eaves 121 above the surface of the carrier structure 140, and the bay area 126 is located between the eaves 121 and the surface 147 of the carrier structure 140, and the ratio of the width dimension W to the height dimension H of the bay area 126 is at least 1; and a molded portion 151 is formed laterally surrounding the IC die 120 and located within the bay area 126.

[0124] In one embodiment, forming the molded portion 151 includes controlling a curing temperature and a heating rate of the molding process such that a ratio of a total volume of the voids 155 in the molded portion 151 to a total volume of the molding compound in the molded portion 151 is between 0.2 and 0.4.

[0125] In another embodiment, the method further includes performing a laser grooving process to form a groove 119 around the periphery of the IC die 120 before performing a cutting process through the semiconductor substrate 101, wherein, after the laser grooving process, at least a portion of the recessed surface 118 remains between the groove 119 and the inner sidewall 117.

[0126] In another embodiment, the first bonding layer 109 includes a first bonding layer 109 having a plurality of first metal bonding pads 111 laterally surrounded by a dielectric material layer 108, and wherein bonding the first bonding layer 109 to a surface 147 of a carrier structure 140 includes: contacting the IC die 120 with the carrier structure 140 so that a flat upper surface 112 of the first bonding layer 109 contacts a second bonding layer 141 on the carrier structure 140, wherein each of the first metal bonding pads 111 of the first bonding layer 109 contacts a corresponding bonding pad 142 of the second bonding layer 141; and performing an annealing process to promote mutual diffusion between the bonding pads 111 of the first bonding layer 109 and the corresponding bonding pads 142 of the second bonding layer 141.

[0127] Some embodiments of the present application provide a bonding device structure, comprising: a carrier structure; an integrated circuit (IC) die bonded to the surface of the carrier structure via a bonding layer, the integrated circuit die comprising an eaves above the surface of the carrier structure, wherein a bay area is located between the eaves and the surface of the carrier structure, and a ratio of a width dimension to a height dimension of the bay area is at least 1; and a molding portion laterally surrounding the integrated circuit die and located within the bay area between the surface of the carrier structure and the eaves.

[0128] In some embodiments, the bay area is located between the lower surface of the eaves, the surface of the carrier structure, and the sidewall extending between the lower surface of the eaves and the surface of the carrier structure. In some embodiments, the width dimension of the bay area is equal to the average of the horizontal width dimensions of the bay area along the top surface of the bay area and the bottom surface of the bay area, and the height dimension of the bay area is equal to the average of the vertical height dimensions of the bay area on the inner side and the outer side of the bay area, and wherein the ratio of the width dimension of the bay area to the height dimension is equal to or less than 80. In some embodiments, the first angle between the sidewall and the lower surface of the eaves is between 10° and 170°, and the second angle between the sidewall and the surface of the carrier structure is between 10° and 170°. In some embodiments, the horizontal width dimension of the bay region along the top surface of the bay region is equal to or less than 100 μm, the horizontal width dimension of the bay region along the bottom surface of the bay region is between 0.5 and 1.5 times the horizontal width dimension of the bay region along the top surface of the bay region, and the vertical height dimension of the bay region on the inner side of the bay region is equal to or greater than 1 μm. In some embodiments, the integrated circuit die includes a thickness dimension along the side surface of the integrated circuit die, the horizontal width dimension of the eaves is greater than 1 / 100 of the thickness dimension of the integrated circuit die, and the vertical height dimension of the bay region on the inner side of the bay region is greater than 1 / 200 of the thickness dimension of the integrated circuit die and less than 1 / 2 of the thickness dimension of the integrated circuit die. In some embodiments, the bay region has a rectangular, truncated parallelogram, or irregular polygonal shape in a vertical cross section. In some embodiments, the bonded device structure further comprises at least one protective film located above the side surface of the integrated circuit die and within the bay region above the lower surface of the eaves and the sidewalls, and the at least one protective film is located between the integrated circuit die and the molded portion. In some embodiments, the ratio of the total volume of the voids in the molded portion to the total volume of the molding compound in the molded portion is between 0.2 and 0.4. In some embodiments, the integrated circuit die comprises a logic die, a memory die, an analog die, an RF die, an integrated passive device (IPD) die, or a dummy die, and the carrier structure comprises a substrate, an interposer, a semiconductor die, or a semiconductor wafer. In some embodiments, the bonding layer of the integrated circuit die comprises a plurality of bonding pads embedded in a dielectric material, and the bonding layer of the integrated circuit die is bonded to a corresponding bonding layer of the carrier structure via metal-to-metal and dielectric-to-dielectric direct bonding.In some embodiments, the integrated circuit die includes a first integrated circuit die, the bonded device structure also includes a second integrated circuit die bonded above the first integrated circuit die, the second integrated circuit die includes an eaves and a bay area located under the eaves, and the ratio of the width dimension to the height dimension of the bay area located under the eaves of the second integrated circuit die is at least 1, and the molded portion laterally surrounds the second integrated circuit die and is located in the bay area under the eaves of the second integrated circuit die.

[0129] Other embodiments of the present application provide a bonding device structure, comprising: a carrier structure; at least one integrated circuit (IC) die bonded to the surface of the carrier structure via a bonding layer, each integrated circuit die comprising an eaves above the surface of the carrier structure, wherein a bay area is located between the eaves and the surface of the carrier structure; and a molding portion laterally surrounding each integrated circuit die and located within the bay area between the surface of the carrier structure and the eaves of each integrated circuit die, and a ratio of a total volume of voids in the molding portion to a total volume of a molding compound in the molding portion is between 0.2 and 0.4.

[0130] In some embodiments, the bonded device structure comprises a multi-layer bonded device structure, the multi-layer bonded device structure comprising a plurality of integrated circuit dies, wherein one or more first integrated circuit dies bonded to the surface of the carrier structure form a first layer of integrated circuit dies, and one or more second integrated circuit dies bonded above the first integrated circuit dies form a second layer of integrated circuit dies, each of the first integrated circuit die and the second integrated circuit die comprises an eaves, wherein a bay area is located under the eaves, and the molded portion laterally surrounds each of the first integrated circuit die and the second integrated circuit die and is located within each of the bay areas under the eaves of the first integrated circuit die and the second integrated circuit die. In some embodiments, a protective film is provided over the surface of each integrated circuit die having a keep-out area of ​​20 μm or less. In some embodiments, the bay area located under the eaves of the one or more first integrated circuit dies and the one or more second integrated circuit dies has a non-uniform shape.

[0131] Still other embodiments of the present application provide a method for manufacturing a bonding device structure, comprising: forming a bonding layer above a semiconductor substrate; performing a plasma cutting process to remove a portion of the bonding layer and forming an opening, the opening having a recessed surface recessed relative to an upper surface of the bonding layer and a sidewall extending between the recessed surface and the upper surface of the bonding layer; performing a cutting process through the semiconductor substrate to provide an integrated circuit (IC) die; bonding the bonding layer to a surface of a carrier structure to form a bonding device structure, wherein the upper surface of the bonding layer contacts the surface of the carrier structure, the integrated circuit die includes an eaves above the surface of the carrier structure, and a bay area is located between the eaves and the surface of the carrier structure, and a ratio of a width dimension to a height dimension of the bay area is at least 1; and forming a molding portion that laterally surrounds the integrated circuit die and is located within the bay area.

[0132] In some embodiments, forming the molded portion includes controlling a curing temperature and a heating rate of a molding process such that a ratio of a total volume of voids in the molded portion to a total volume of a molding compound in the molded portion is between 0.2 and 0.4. In some embodiments, the method further includes: before performing the cutting process through the semiconductor substrate, performing a laser grooving process to form a groove around the periphery of the integrated circuit die, wherein at least a portion of the recessed surface remains between the groove and the sidewall after the laser grooving process. In some embodiments, the bonding layer includes a first bonding layer, the first bonding layer including a plurality of bonding pads laterally surrounded by a dielectric material, and wherein bonding the first bonding layer to the surface of the carrier structure includes: contacting the integrated circuit die with the carrier structure such that the upper surface of the bonding layer contacts a second bonding layer on the carrier structure, wherein each of the plurality of bonding pads of the first bonding layer contacts a corresponding bonding pad of the second bonding layer; and performing an annealing process to promote interdiffusion between the bonding pads of the first bonding layer and the corresponding bonding pads of the second bonding layer.

[0133] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent configurations do not deviate from the spirit and scope of the embodiments of the present disclosure, and in examples that do not deviate from the spirit and scope of the embodiments of the present disclosure, they can make various changes, substitutions and modifications herein.

Claims

1. A bonding device structure, comprising: Carrier structure; an integrated circuit (IC) die bonded to the surface of the carrier structure via a bonding layer, the integrated circuit die comprising an eave above the surface of the carrier structure, wherein a bay region is located between the eave and the surface of the carrier structure, and wherein a ratio of a width dimension to a height dimension of the bay region is at least 1; as well as A molded portion laterally surrounds the integrated circuit die and is located within the bay region between the surface of the carrier structure and the eaves.

2. The bonding device structure according to claim 1, wherein: The bay area is located between a lower surface of the eave, the surface of the carrier structure, and a sidewall extending between the lower surface of the eave and the surface of the carrier structure.

3. The bonding device structure according to claim 2, wherein: The width dimension of the bay area is equal to the average value of the horizontal width dimensions of the bay area along the top surface of the bay area and the bottom surface of the bay area, and the height dimension of the bay area is equal to the average value of the vertical height dimensions of the bay area on the inner side and the outer side of the bay area, and wherein the ratio of the width dimension of the bay area to the height dimension is equal to or less than 80.

4. The bonding device structure according to claim 3, wherein: A first angle between the side wall and the lower surface of the eave is between 10° and 170°, and a second angle between the side wall and the surface of the carrier structure is between 10° and 170°.

5. The bonding device structure according to claim 3, wherein: The horizontal width dimension of the bay region along the top surface of the bay region is equal to or less than 100 μm, the horizontal width dimension of the bay region along the bottom surface of the bay region is between 0.5 and 1.5 times the horizontal width dimension of the bay region along the top surface of the bay region, and the vertical height dimension of the bay region on the inner side of the bay region is equal to or greater than 1 μm.

6. The bonding device structure according to claim 3, wherein: The integrated circuit die includes a thickness dimension along the side surface of the integrated circuit die, the horizontal width dimension of the eaves is greater than 1 / 100 of the thickness dimension of the integrated circuit die, and the vertical height dimension of the bay area on the inner side of the bay area is greater than 1 / 200 of the thickness dimension of the integrated circuit die and less than 1 / 2 of the thickness dimension of the integrated circuit die.

7. The bonding device structure according to claim 1, wherein: The bay area has a rectangular, truncated parallelogram, or irregular polygonal shape in vertical cross-section.

8. The bonded device structure according to claim 2 further includes at least one protective film located above the side surface of the integrated circuit die and within the bay area above the lower surface of the eaves and the side wall, and the at least one protective film is located between the integrated circuit die and the molding part.

9. A bonding device structure, comprising: Carrier structure; at least one integrated circuit (IC) die bonded to the surface of the carrier structure via a bonding layer, each integrated circuit die comprising an eave above the surface of the carrier structure, wherein a bay region is located between the eave and the surface of the carrier structure; as well as A molded portion laterally surrounds each integrated circuit die and is located in the bay area between the surface of the carrier structure and the eaves of each integrated circuit die, and the ratio of the total volume of the voids in the molded portion to the total volume of the molding material in the molded portion is between 0.2 and 0.

4.

10. A method of manufacturing a bonded device structure, comprising: forming a bonding layer over the semiconductor substrate; performing a plasma cutting process to remove a portion of the bonding layer and form an opening having a recessed surface that is recessed relative to an upper surface of the bonding layer and a sidewall extending between the recessed surface and the upper surface of the bonding layer; performing a dicing process through the semiconductor substrate to provide integrated circuit (IC) dies; bonding the bonding layer to a surface of a carrier structure to form a bonded device structure, wherein the upper surface of the bonding layer contacts the surface of the carrier structure, the integrated circuit die includes an eaves above the surface of the carrier structure, and a bay region is located between the eaves and the surface of the carrier structure, and the ratio of a width dimension to a height dimension of the bay region is at least 1; as well as A molding portion is formed laterally surrounding the integrated circuit die and within the bay area.

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