High-voltage protection circuit applied to a data transmission chip

Abstract

The present invention discloses a high-voltage protection circuit applied to a data transmission chip, which realizes multi-level protection and dynamic biasing through the collaborative design of an output driver protection circuit and a maximum value extraction protection circuit. The output driver protection circuit adopts differential input transistors and two-stage cascaded CMOS high-voltage protection transistor pairs, and reduces the drain terminal voltage stress of short-channel transistors through hierarchical voltage division, enabling them to operate safely under a 3.3V power supply. The maximum value extraction protection circuit dynamically selects the highest potential to provide bias for the low-threshold transistor substrate by comparing the analog power supply voltage and the output common-mode voltage, avoiding performance degradation caused by abnormal substrate voltage. A specially designed tail current transistor is linked with the control signal to automatically switch the working mode when the chip enables / disables the analog power supply. Through the voltage distribution mechanism of the two-stage protection transistor pairs and the dynamic substrate biasing technology, it not only ensures high-speed transmission at 6GSPS under the 3V common-mode voltage required by the HDMI2.0 protocol, but also effectively prevents transistor breakdown.

Description

Technical Field

[0001] The present invention relates to a protection circuit, and particularly to a high-voltage protection circuit applied to a data transmission chip. Background Art

[0002] With the increasing demand for data transmission rate, the high-speed serial interface (HSS) technology has gradually replaced the parallel interface and become the mainstream. As the core module, SerDes (Serializer / Deserializer) needs to implement the conversion between high-speed differential signals and low-speed parallel signals. CN107346971A (A Design Method of Full-Swing Output VCO Delay Unit for SerDes) discloses a full-swing VCO design in a low-voltage power supply environment, which improves the phase noise performance by optimizing the MOS transistor size and load structure, but it does not involve the breakdown protection problem of short-channel transistors under high power supply voltages.

[0003] Meanwhile, the initially widely used data transmission technology was the low-speed serial interface technology. With the further increase of data transmission rate requirements, the traditional low-speed serial interface technology gradually fails to meet the needs. To increase the total bandwidth of data, the first thing that comes to mind is to increase the data transmission bit width, that is, the parallel interface method. However, with the development of the parallel interface, people have found that problems such as the tightness of chip I / O numbers, crosstalk between parallel port data, and difficulties in data synchronization will limit the improvement of the data transmission rate of the parallel interface.

[0004] Meanwhile, the SerDes technology used in high-speed serial links converts low-speed parallel signals into high-speed differential signals and sends them through a serial link, and at the same time can receive high-speed differential signals input serially and correctly convert them into low-speed parallel signals, that is, complete the conversion between parallel-to-serial and serial-to-parallel of data. To meet the GSPS-level rate requirements, short-channel low-threshold voltage transistors are often used. However, in scenarios where the interface protocol requires a 3.3V common-mode voltage (such as PCIe, USB4, etc.), it is necessary to additionally consider how to effectively protect transistors with shorter channel lengths under the condition of a high power supply voltage of 3.3V to prevent short-channel transistors from being broken down.

[0005] Currently, the industry needs to implement a physical layer protection scheme for short-channel transistors under a 3.3V power supply while meeting the GSPS-level transmission rate. Existing technologies mostly focus on signal integrity optimization. Although the existing technologies CN119232142B clock data recovery circuit and CN118631409B SerDes data clock recovery method provide methods and structures for protection. However, they lack a systematic design method for the compatibility between high-voltage working conditions and short-channel devices.

[0006] In view of the above-mentioned deficiencies, the present inventor has actively carried out research and innovation in order to create a high-voltage protection circuit applied to a data transmission chip, making it more valuable in industrial applications. Summary of the Invention

[0007] To solve the above technical problems, the object of the present invention is to provide a high-voltage protection circuit applied to a data transmission chip.

[0008] The high-voltage protection circuit applied to a data transmission chip of the present invention includes an output driver protection circuit and a maximum value extraction protection circuit.

[0009] The output driver protection circuit includes differential signal input transistors MP1 and MP2, and also includes a first-stage high-voltage protection transistor pair composed of transistors MP3 and MP4, a second-stage high-voltage protection transistor pair composed of transistors MP5 and MP6, and a tail current transistor MP7.

[0010] The output terminal VNW of the maximum value extraction protection circuit is connected to the input terminal VB of the output driver protection circuit, and is used for protecting and biasing the substrates of transistors MP1, MP2, and MP7 in the output driver protection circuit.

[0011] The gate terminal of transistor MP1 is connected to the differential input signal VIN, and the gate terminal of transistor MP2 is connected to the differential input signal VIP; the gate terminals of transistors MP3 and MP4 are connected to the protection bias voltage PBHV1.

[0012] The maximum value extraction protection circuit includes transistors MN1, MN2, MP8, MP9, MP10, MP11, MP12, MP13, and MP14, where

[0013] The gate terminal and source terminal of transistor MN1 are both connected to the ground GND, and its drain terminal is connected to the source terminal of transistor MN2.

[0014] The gate terminal of transistor MN2 is connected to the protection bias voltage VN, its source terminal is connected to the drain terminal of transistor MN1, and its drain terminal is respectively connected to the drain terminals of transistors MP8 and MP10, and is also connected to the output control signal V3SW.

[0015] The source terminal of transistor MP8 is connected to the protection bias voltage VP, the gate terminal is connected to its own drain terminal and the drain terminals of transistors MP10 and MN2, and the drain terminal is also connected to the output control signal V3SW.

[0016] The gate terminal of the transistor MP9 is connected to the protection bias voltage VP, the source terminal is connected to the output common-mode voltage VOUTCM, and its drain terminal is connected to the source terminal of the transistor MP10.

[0017] The gate terminal of the transistor MP10 is connected to the analog power supply voltage AVDD, its source terminal is connected to the drain terminal of the transistor MP9, and its drain terminal is connected to the drain terminals of the transistor MP8 and the transistor MN2. The drain terminal is also connected to the output control signal V3SW.

[0018] The gate terminal of the transistor MP11 is connected to the protection bias voltage VP, the source terminal is connected to the output common-mode voltage VOUTCM, and its drain terminal is connected to the source terminal of the transistor MP12.

[0019] The gate terminal of the transistor MP12 is connected to the analog power supply voltage AVDD, its source terminal is connected to the drain terminal of the transistor MP11, and its drain terminal is connected to the drain terminals of the transistor MP13 and the transistor MP14. The source terminal is also connected to the output voltage VNW.

[0020] The gate terminal of the transistor MP13 is connected to the output control signal V3SW, the source terminal is connected to the analog power supply voltage AVDD and the source terminal of the transistor MP14, and its drain terminal is connected to the drain terminals of the transistor MP12 and the transistor MP14. The drain terminal is also connected to the output voltage VNW.

[0021] The gate terminal of the transistor MP14 is connected to its own drain terminal and the drain terminals of the transistor MP12 and the transistor MP13, and the source terminal is connected to the analog power supply voltage AVDD and the source terminal of the transistor MP13.

[0022] Further, in the above high-voltage protection circuit applied to the data transmission chip, the transistors MP1, MP2, and MP7 are short-channel low-threshold voltage transistors, and the transistors MP3, MP4, MP5, and MP6 are CMOS 0.18μm standard threshold voltage transistors.

[0023] Furthermore, in the above high-voltage protection circuit applied to the data transmission chip, the source terminal of the transistor MP3 is connected to the drain terminal of the transistor MP1, and its drain terminal is connected to the source terminal of the transistor MP5.

[0024] The source terminal of the transistor MP4 is connected to the drain terminal of the transistor MP2, and its drain terminal is connected to the source terminal of the transistor MP6.

[0025] The gate terminal of the transistor MP5 is connected to the protection bias voltage PBHV2, and its drain terminal is connected to the differential output signal VOUTP.

[0026] The gate terminal of the transistor MP6 is connected to the protection bias voltage PBHV2, and its drain terminal is connected to the differential output signal VOUTN.

[0027] The gate terminal of the transistor MP7 is connected to the bias voltage VBP, the source terminal is connected to the analog power supply AVDD, and its drain terminal is connected to the source terminals of the transistors MP1 and MP2.

[0028] Furthermore, in the above high-voltage protection circuit applied to the data transmission chip, during the operation of the first-stage high-voltage protection pair of transistors, the drain terminal voltages of the transistors MP1 and MP2 are:

[0029] VD(MP1 / MP2)=VG(MP3 / MP4)+|VGS(MP3 / MP4)|=VPBHV1+|VGS(MP3 / MP4)|.

[0030] By setting the value of the bias voltage PBHV1, the drain terminal voltages of the transistors MP1 and MP2 are within a suitable range, so that they are not broken down and operate normally in the saturation region.

[0031] During the operation of the second-stage high-voltage protection pair of transistors, the drain terminal voltages of the transistors MP3 and MP4 are:

[0032] VD(MP3 / MP4)=VG(MP5 / MP6)+|VGS(MP5 / MP6)|=VPBHV2+|VGS(MP5 / MP6)|.

[0033] By setting the value of the bias voltage PBHV2, the drain terminal voltages of the transistors MP3 and MP4 are within a suitable range, so that they are not broken down and operate normally in the saturation region, and the transistors MP5 and MP6 will not be broken down after being connected to the corresponding differential output signals VOUTP and VOUTN.

[0034] Still further, in the above high-voltage protection circuit applied to the data transmission chip, the maximum value protection circuit reasonably biases the substrate of the low-threshold voltage PMOS transistor in the SerDes circuit when the data transmission chip does not use the analog power supply, to prevent the PMOS transistor from being abnormal due to the substrate voltage being lower than the source voltage in this operating mode.

[0035] By means of the above solution, the present invention has at least the following advantages:

[0036] 1. It can achieve effective hierarchical voltage protection, realize the series voltage division of two-stage PMOS transistor pairs, and reduce the drain terminal voltage stress of key transistors.

[0037] 2. It can achieve dynamic substrate biasing and can automatically select the highest potential through a maximum value circuit to provide stable biasing for the low-threshold PMOS substrate.

[0038] 3. It can achieve dual-mode compatibility. Depending on the output control signal V3SW, it can achieve seamless switching of the power supply mode to ensure reliability in different scenarios.

[0039] The above description is only an overview of the technical solution of the present invention. In order to understand the technical means of the present invention more clearly and implement it in accordance with the content of the specification, the following describes the preferred embodiments of the present invention in detail with reference to the accompanying drawings. Brief Description of the Drawings

[0040] Figure 1 It is a schematic structural diagram of an output driver protection circuit.

[0041] Figure 2 It is a schematic structural diagram of a maximum value protection circuit.

[0042] Figure 3 It is a schematic diagram of combining the high-voltage protection circuit of the present application with a data transmission chip. Detailed Embodiment

[0043] The following combines the accompanying drawings and embodiments to further describe the detailed implementation of the present invention in detail. The following embodiments are used to illustrate the present invention but are not used to limit the scope of the present invention.

[0044] As Figures 1 to 3 A high-voltage protection circuit applied to a data transmission chip is different in that the circuit includes an output driver protection circuit and a maximum value protection circuit. The output driver protection circuit includes differential signal input transistors MP1 and MP2, and also includes a first-stage high-voltage protection transistor pair composed of transistors MP3 and MP4, and at the same time includes a second-stage high-voltage protection transistor pair composed of transistors MP5 and MP6. Thus, multi-stage protection can be achieved. And, it also includes a tail current transistor MP7 to avoid accidental breakdown. During implementation, the output terminal VNW of the maximum value protection circuit is connected to the input terminal VB of the output driver protection circuit for protecting and reasonably biasing the substrates of transistors MP1, MP2, and MP7 in the output driver protection circuit. At the same time, the gate terminal of transistor MP1 is connected to the differential input signal VIN, and the gate terminal of transistor MP2 is connected to the differential input signal VIP; the gate terminals of transistors MP3 and MP4 are connected to the protection bias voltage PBHV1.

[0045] The maximum value protection circuit adopted by the present invention includes transistors MN1, MN2, MP8, MP9, MP10, MP11, MP12, MP13, and MP14. Specifically, the gate terminal and the source terminal of transistor MN1 are both connected to the ground GND, and its drain terminal is connected to the source terminal of transistor MN2. The gate terminal of transistor MN2 is connected to the protection bias voltage VN, its source terminal is connected to the drain terminal of transistor MN1, and its drain terminal is respectively connected to the drain terminals of transistors MP8 and MP10, and is also connected to the output control signal V3SW to facilitate receiving the corresponding control signal.

[0046] Meanwhile, the source terminal of transistor MP8 is connected to the protection bias voltage VP, the gate terminal is connected to its own drain terminal and the drain terminals of transistors MP10 and MN2, and the drain terminal is also connected to the output control signal V3SW. The gate terminal of transistor MP9 is connected to the protection bias voltage VP, the source terminal is connected to the output common-mode voltage VOUTCM, and its drain terminal is connected to the source terminal of transistor MP10.

[0047] The gate terminal of transistor MP10 is connected to the analog power supply voltage AVDD, its source terminal is connected to the drain terminal of transistor MP9, and its drain terminal is connected to the drain terminals of transistors MP8 and MN2, and the drain terminal is also connected to the output control signal V3SW. Similarly, it is convenient for subsequent control through the output control signal V3SW.

[0048] During implementation, the gate terminal of transistor MP11 is connected to the protection bias voltage VP, the source terminal is connected to the output common-mode voltage VOUTCM, and its drain terminal is connected to the source terminal of transistor MP12. The gate terminal of transistor MP12 is connected to the analog power supply voltage AVDD, its source terminal is connected to the drain terminal of transistor MP11, and its drain terminal is connected to the drain terminals of transistors MP13 and MP14, and the source terminal is also connected to the output voltage VNW to facilitate the introduction of the output voltage VNW. Meanwhile, the gate terminal of transistor MP13 is connected to the output control signal V3SW, the source terminal is connected to the analog power supply voltage AVDD and the source terminal of transistor MP14, and its drain terminal is connected to the drain terminals of transistors MP12 and MP14, and the drain terminal is also connected to the output voltage VNW. Furthermore, the gate terminal of transistor MP14 is connected to its own drain terminal and the drain terminals of transistors MP12 and MP13, and the source terminal is connected to the analog power supply voltage AVDD and the source terminal of transistor MP13.

[0049] In view of a preferred embodiment of the present invention, the transistors MP1, MP2, and MP7 are short-channel low-threshold voltage transistors. The transistors MP1 and MP2 are key transistors in the entire signal transmission link, and their operating speed directly affects the data transmission rate of the overall SerDes circuit. Therefore, short-channel devices with faster speed are preferably used. During use, the substrate terminals of the transistors MP1 and MP2 are connected to the input terminal VB of the output driver protection circuit and then biased. Moreover, the transistors MP3, MP4, MP5, and MP6 are CMOS 0.18μm standard threshold voltage transistors. It should be noted that since the substrates of the transistors MP3 to MP6 are all normally biased and can be directly connected to the analog power supply AVDD, the connection of their substrate terminals is not marked in Figure 1 the figure.

[0050] Furthermore, the source terminal of the transistor MP3 is connected to the drain terminal of the transistor MP1, and its drain terminal is connected to the source terminal of the transistor MP5. The source terminal of the transistor MP4 is connected to the drain terminal of the transistor MP2, and its drain terminal is connected to the source terminal of the transistor MP6. At the same time, considering the control requirements of the corresponding differential signals, the gate terminal of the transistor MP5 is connected to the protection bias voltage PBHV2, and its drain terminal is connected to the differential output signal VOUTP. The gate terminal of the transistor MP6 is connected to the protection bias voltage PBHV2, and its drain terminal is connected to the differential output signal VOUTN. Considering the convenience of introducing the analog power supply AVDD, the gate terminal of the transistor MP7 is connected to the bias voltage VBP, the source terminal is connected to the analog power supply AVDD, and its drain terminal is connected to the source terminals of the transistors MP1 and MP2.

[0051] To achieve effective high-voltage protection, during the operation of the first-stage high-voltage protection pair of transistors adopted by the present invention, the drain voltages of the transistors MP1 and MP2 are:

[0052] VD(MP1 / MP2)=VG(MP3 / MP4)+|VGS(MP3 / MP4)|=VPBHV1+|VGS(MP3 / MP4)|.

[0053] In this way, by setting the value of the bias voltage PBHV1, the drain voltages of the transistors MP1 and MP2 can be within a suitable range, so that they are not broken down and operate normally in the saturation region. At this time, since the transistors MP3 and MP4 are CMOS 0.18μm standard threshold voltage transistors, if they are directly connected to VOUTP / VOUTN, there is still a risk that the first-stage high-voltage protection transistors themselves will be broken down, resulting in the failure of the protection function.

[0054] Moreover, during the operation of the second-stage high-voltage protection pair of transistors adopted, the drain voltages of the transistors MP3 and MP4 are:

[0055] VD(MP3 / MP4) = VG(MP5 / MP6) + |VGS(MP5 / MP6)| = VPBHV2 + |VGS(MP5 / MP6)|.

[0056] In this way, by setting the value of the bias voltage PBBHV2, the drain voltages of transistors MP3 and MP4 can be made to fall within a suitable range, preventing them from being breakdown and enabling them to operate normally in the saturation region. At the same time, it can also prevent transistors MP5 and MP6 from being breakdown when connected to the corresponding differential output signals VOUTP and VOUTN.

[0057] For this reason, by adopting the solution of the present invention, after being protected by two-stage high-voltage protection circuits, the low-threshold-voltage transistors MP1, MP2, MP7 with short channel lengths and the CMOS 0.18μm standard-threshold-voltage transistors MP3, MP4, MP5, MP6 for protection can all operate normally under a power supply voltage of 3.3V without the risk of being breakdown.

[0058] In the present invention, transistors MP1 and MP2 constituting the differential input pair are key transistors in the entire signal transmission link, and their operating speed is directly related to the data transmission rate that the overall SerDes circuit can achieve. Taking the HDMI2.0 data transmission protocol as an example, the protocol stipulates that the common-mode voltage for data transmission is 3V, that is, it is assumed that the common-mode level of VOUTP / VOUTN is 3V during circuit design. If transistors MP1 and MP2 are not protected at this time, but their drain terminals are directly connected to VOUTP / VOUTN, the 3V common-mode voltage will directly breakdown the short-channel transistors MP1 and MP2 after being connected to the external port impedance, causing the circuit to fail to work.

[0059] Looking further, by adopting the maximum-value protection circuit, when the data transmission chip does not use analog power supply, the diode in the ESD protection circuit in the chip pin provides power supply voltage for the analog circuit, which is a power supply voltage that does not generate current. For this reason, the substrate of the low-threshold-voltage PMOS transistor in the SerDes circuit can be reasonably biased to prevent the PMOS transistor from being abnormal due to the substrate voltage being lower than the source voltage in this operating mode. In this way, problems such as reduced conduction current, decreased driving ability, and increased leakage current can be effectively avoided.

[0060] That is to say, the main function of the maximum-value protection circuit is to reasonably bias the substrate of the low-threshold-voltage PMOS transistor in the SerDes circuit when the data transmission chip does not use analog power supply. It realizes automatically connecting the substrate of the low-threshold-voltage PMOS transistor to the actual highest potential in the circuit under different operating modes. The specific working principle is as follows:

[0061] When the data transmission chip is powered by a 3.3V analog power supply, the highest potential of the circuit at this time is the analog power supply voltage of 3.3V. In this operating mode, in conjunction with the level shift of the control signal, the substrate of the low-threshold voltage PMOS transistor can be directly connected to 3.3V without the risk of breakdown. In this operating mode, the transistor MP10 is cut off, and the protection bias voltage VP is connected to the output control signal V3SW through the transistor MP8. At this time, the transistors MN1 and MN2 are within a reasonable voltage bias range and there is no risk of breakdown. During this period, the output control signal V3SW controls the transistor MP13 to conduct, making the transistor MP12 cut off, and the output voltage VNW is connected to the analog power supply voltage AVDD and connected to the substrate of the low-threshold voltage PMOS transistor.

[0062] When the data transmission chip is not powered by a 3.3V analog power supply, the voltage of the AVDD pin is less than the output common-mode voltage VOUTCM at this time, that is, the highest potential of the circuit is the output common-mode voltage VOUTCM. In this operating mode, if the substrate of the low-threshold voltage PMOS transistor is directly connected to the analog power supply voltage AVDD, problems such as a decrease in conduction current, a decrease in driving ability, and an increase in leakage current will occur due to the substrate voltage being lower than the source voltage. In this operating mode, the transistor MP10 conducts, and the output common-mode voltage VOUTCM is connected to the output control signal V3SW through the transistors MP9 and MP10, and makes the transistor MP8 cut off. At the same time, the MN2 transistor will not be at risk of breakdown because its gate terminal is connected to the protection bias voltage VN. During this period, the output control signal V3SW controls the MP13 transistor to cut off, and the analog power supply voltage AVDD lower than the output common-mode voltage VOUTCM can control the transistor MP12 to conduct. Thus, the output common-mode voltage VOUTCM is connected to the output voltage VNW through the transistors MP11 and MP12, and the transistor MP14 is cut off.

[0063] The working principle of the present invention is as follows:

[0064] As Figure 3 shown, the circuit of the present invention is combined with a data transmission chip (TX, Transmitter, transmitter) that supports the HDMI2.0 protocol. This data transmission chip requires the data output common mode to be 2.8 to 3.2V and the data transmission rate to be 6GSPS. The main circuit of this data transmission chip consists of modules such as an input register, a protocol layer, a parallel-to-serial conversion circuit, a differential signal transmitter, and a PLL clock. During implementation, the input clock is connected to the PLL clock. Thus, the PLL clock can be used to provide a low-speed parallel data clock and a high-speed serial data clock for the circuit.

[0065] The working process in practical applications is as follows:

[0066] First, the input register buffers and stores the input data. Then, according to the interface protocol of HDMI 2.0, the protocol layer encodes the input low-speed parallel data in different formats. Thereby, it can ensure that the data does not stop changing for a long time, preventing possible incorrect sampling in the clock recovery circuit (CDR) of the data receiving chip (RX).

[0067] Next, the serial-to-parallel conversion circuit converts the low-speed parallel data encoded by the protocol layer into a high-speed low-voltage signal, that is, high-speed serial data, implementing the most critical serial-to-parallel conversion function in the TX. At the same time, the differential signal transmitter drives the high-speed differential signal, which is used as the output of the data transmission chip and sent to the input IO port of the data receiving chip. In this module, the speed of the transistor plays a key role in the overall data transmission rate of the data transmission chip. Therefore, in the circuit design of the present invention, transistors with short channel lengths are selected. The high-voltage protection circuit proposed in this application protects the transistors with short channel lengths used in this module.

[0068] During implementation, the maximum value protection circuit first selects the larger voltage between the analog power supply voltage AVDD or the common-mode voltage VOUTCM according to the actual working state of the chip. Then, it biases the substrate of the low-threshold voltage transistor in the output driver protection circuit. In this way, after being reasonably biased, the output driver protection circuit can further protect the gate, source, and drain of the transistors with short channel lengths in the differential signal transmitter, ensuring that there will be no defect that the transistors are broken down due to excessive voltage.

[0069] It can be seen from the simulation verification that the data transmission chip with the high-voltage protection circuit constructed by the method of this application can support the data output common-mode voltage of 2.8 to 3.2V required by the HDMI 2.0 protocol. At the same time, it can meet the data transmission rate of 6 GSPS. And it can support two different working modes, choosing whether to use an external 3.3V analog power supply voltage to supply power to the data transmission chip. During use, all the short-channel transistors in the data transmission chip will not be broken down within the PVT fluctuation range and are effectively protected.

[0070] From the above text description and in combination with the attached drawings, it can be seen that after adopting the present invention, the following advantages are obtained:

[0071] 1. It can achieve effective hierarchical voltage protection, and two-stage PMOS transistor pairs can be connected in series to divide the voltage, reducing the drain voltage stress of the key transistors.

[0072] 2. It can achieve dynamic substrate biasing, and the maximum value circuit can automatically select the highest potential to provide a stable bias for the substrate of the low-threshold PMOS.

[0073] 3. It can achieve dual-mode compatibility. Depending on the output control signal V3SW, it can achieve seamless switching of the power supply mode to ensure reliability in different scenarios.

[0074] In addition, the orientation or positional relationship described in this invention is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this invention and simplifying the description, rather than indicating or implying that the device or structure referred to must have a specific orientation or be operated in a specific orientation structure. Therefore, it should not be construed as a limitation of this invention.

[0075] The above are only the preferred embodiments of this invention and are not used to limit this invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principles of this invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of this invention.

Claims

1. A high voltage protection circuit for a data transmission chip, characterized in that: Including output driver protection circuit and maximum value protection circuit, The output driver protection circuit includes a differential signal input transistor composed of transistors MP1 and MP2, a first-stage high-voltage protection pair composed of transistors MP3 and MP4, a second-stage high-voltage protection pair composed of transistors MP5 and MP6, and a tail current transistor composed of transistor MP7. The output terminal VNW of the maximum protection circuit is connected to the input terminal VB of the output driver protection circuit, and is used to protect and bias the substrates of the transistors MP1, MP2, and MP7 in the output driver protection circuit; The gate terminal of the transistor MP1 is connected to the differential input signal VIN, and the gate terminal of the transistor MP2 is connected to the differential input signal VIP; the gate terminals of the transistor MP3 and the transistor MP4 are connected to the protection bias voltage PBHV1; The maximum value protection circuit includes a transistor MN1, a transistor MN2, a transistor MP8, a transistor MP9, a transistor MP10, a transistor MP11, a transistor MP12, a transistor MP13, and a transistor MP14, wherein: The gate terminal and the source terminal of the transistor MN1 are both connected to the ground GND, and the drain terminal thereof is connected to the source terminal of the transistor MN2. The gate terminal of the transistor MN2 is connected to the protection bias voltage VN, the source terminal thereof is connected to the drain terminal of the transistor MN1, the drain terminal thereof is connected to the drain terminals of the transistors MP8 and MP10, and is also connected to the output control signal V3SW. The source terminal of the transistor MP8 is connected to the protection bias voltage VP, the gate terminal is connected to its own drain terminal and the drain terminals of the transistor MP10 and the transistor MN2, and the drain terminal is also connected to the output control signal V3SW. The gate terminal of the transistor MP9 is connected to the protection bias voltage VP, the source terminal is connected to the output common mode voltage VOUTCM, and the drain terminal is connected to the source terminal of the transistor MP10. The gate terminal of the transistor MP10 is connected to the analog power supply voltage AVDD, the source terminal thereof is connected to the drain terminal of the transistor MP9, the drain terminal thereof is connected to the drain terminals of the transistor MP8 and the transistor MN2, and the drain terminal is also connected to the output control signal V3SW. The gate terminal of the transistor MP11 is connected to the protection bias voltage VP, the source terminal is connected to the output common mode voltage VOUTCM, and the drain terminal is connected to the source terminal of the transistor MP12. The gate terminal of the transistor MP12 is connected to the analog power supply voltage AVDD, the source terminal thereof is connected to the drain terminal of the transistor MP11, the drain terminal thereof is connected to the drain terminals of the transistors MP13 and MP14, and the drain terminal thereof is also connected to the output voltage VNW; The gate terminal of the transistor MP13 is connected to the output control signal V3SW, the source terminal is connected to the analog power supply voltage AVDD and the source terminal of the transistor MP14, the drain terminal is connected to the drain terminals of the transistors MP12 and MP14, and the drain terminal is also connected to the output voltage VNW; The gate terminal of the transistor MP14 is connected to its own drain terminal and the drain terminals of the transistors MP12 and MP13, and the source terminal is connected to the analog power supply voltage AVDD and the source terminal of the transistor MP13; The transistors MP1, MP2, and MP7 are short-channel low-threshold-voltage transistors, and the transistors MP3, MP4, MP5, and MP6 are CMOS 0.18 μm standard-threshold-voltage transistors. The source terminal of the transistor MP3 is connected to the drain terminal of the transistor MP1, and the drain terminal of the transistor MP3 is connected to the source terminal of the transistor MP5. The source terminal of the transistor MP4 is connected to the drain terminal of the transistor MP2, and the drain terminal of the transistor MP4 is connected to the source terminal of the transistor MP6. The gate terminal of the transistor MP5 is connected to the protection bias voltage PBHV2, and the drain terminal thereof is connected to the differential output signal VOUTP. The gate terminal of the transistor MP6 is connected to the protection bias voltage PBHV2, and the drain terminal thereof is connected to the differential output signal VOUTN. The gate terminal of the transistor MP7 is connected to the bias voltage VBP, the source terminal is connected to the analog power supply AVDD, and the drain terminal is connected to the source terminals of the transistor MP1 and the transistor MP2; During the operation of the first-level high-voltage protection pair, the drain voltage of transistors MP1 and MP2 is: VD(MP1 / MP2)=VG(MP3 / MP4)+|VGS(MP3 / MP4)|=VPBHV1+|VGS(MP3 / MP4)|, By setting the value of the bias voltage PBHV1, the drain voltage of the transistor MP1 and the transistor MP2 is kept in an appropriate range so that they are not broken down and can operate normally in the saturation region; During the operation of the second-level high-voltage protection pair, the drain voltage of transistors MP3 and MP4 is: VD(MP3 / MP4)=VG(MP5 / MP6)+|VGS(MP5 / MP6)|=VPBHV2+|VGS(MP5 / MP6)|, By setting the value of the bias voltage PBHV2, the drain voltages of the transistors MP3 and MP4 are kept within an appropriate range, preventing them from breaking down and allowing them to operate normally in the saturation region. Furthermore, the transistors MP5 and MP6 are prevented from breaking down after being connected to the corresponding differential output signals VOUTP and VOUTN. The maximum protection circuit reasonably biases the substrate of the low-threshold voltage PMOS tube in the SerDes circuit when the data transmission chip is not powered by an analog power supply, thereby preventing the PMOS tube from malfunctioning in this working mode due to the substrate voltage being lower than the source voltage.

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