A circuit for implementing spread spectrum control in DCM mode of a buck converter

Abstract

The present invention discloses a circuit for implementing spread spectrum control in the DCM mode of a buck converter, relating to the field of power management technology. The circuit comprises a spread spectrum control module, an adaptive on-time module, a PWM module, a logic control circuit, and a zero-current detection module. The present invention utilizes simple control logic to determine load information, avoiding the high complexity of current or voltage feedback in traditional converters and providing higher detection accuracy under light or no-load conditions. The circuit determines the load state by detecting the time interval of the zero-current detection signal and the PWM signal. When the system enters a set load range, frequency expansion is performed to improve efficiency. The circuit can promptly exit the spread spectrum mode during load transients, ensuring system stability and efficiency. The circuit can adaptively adjust the spread spectrum control as the load changes, balancing efficiency and ripple under different load conditions, significantly improving system stability and performance.

Description

Technical Field

[0001] The present invention relates to the field of power management technology, and in particular to a control circuit for a buck converter (BUCK) and an adaptive spread spectrum control method thereof in DCM. The technology can be applied to the field of integrated circuits, and is particularly suitable for low-power, high-efficiency power management chips, portable battery-powered systems, and various power converters that require optimized efficiency and ripple under load conditions. Background Art

[0002] With the increasing demand for power management systems in modern electronic devices, buck converters (Buck Converters) have become a key component in power management. In these systems, DCM mode is widely adopted because it improves conversion efficiency at light or no load. However, existing DCM buck converters still face some key challenges in practical applications, particularly in spread spectrum control.

[0003] 1. Deficiencies of traditional spread spectrum control logic

[0004] Currently, traditional DCM step-down converters mostly use fixed spread-spectrum control logic. This causes spread-spectrum control to remain active even when the load is light, resulting in excessive output ripple and an inability to adaptively adjust efficiency and ripple control. Consequently, system efficiency decreases and ripple increases at low loads. However, when the load increases, spread-spectrum mode cannot be promptly exited, deteriorating system stability and efficiency. How to adaptively adjust spread-spectrum control to achieve higher efficiency and lower ripple under varying load conditions has become a key issue in power management design.

[0005] 2. Analysis of research status

[0006] Although existing technologies offer load detection modules or control circuit designs, most only address efficiency and ripple issues in certain specific modes and still fail to effectively address the adaptive switching of spread spectrum control in DCM mode. The following is an analysis of several related technologies:

[0007] The patented technology of "CN1111416505B A Switching Power Converter" contains key technical means such as a load detection module and a counter module, but only solves the switching control of the system between PWM mode and PFM mode. However, these solutions fail to effectively solve the spread spectrum control problem in DCM mode, especially the automatic switching problem under light load and heavy load conditions.

[0008] Patent application CN104753346A, "A Technology for Improving Buck Circuit Efficiency," controls the selection or non-selection of additional high-side and low-side transistors based on the duty cycle of the output node voltage signal. This dynamically reduces the overall on-resistance of the high-side and low-side transistors under different output conditions, improving the efficiency of the buck circuit. However, this efficiency improvement requires more power transistors, which consumes a larger overall area and places a burden on the overall power consumption of the system.

[0009] Patented technology, "Adaptive Peak Current Control Circuit and Electronic Device for Buck PSM Operation," CN117724563B linearly adjusts the peak current based on the on-time of the upper power transistor, addressing the issues of low buck circuit efficiency at high input voltages and high ripple at low input voltages. However, this patented solution only applies to the frequency-hopping PSM mode under peak current mode control. The complexity and instability of current sampling in DCM mode pose a bottleneck to its application.

[0010] The patented technology "CN105763051B: A Light-Load Frequency Reduction Mode Control System" measures the relative changes in charging and demagnetization times based on the inductor current through an output load current calculation circuit. The load current supplies a phase detection voltage signal. The variable frequency control circuit includes an adaptive clock unit that controls the clock frequency based on the voltage signal. However, this solution requires complex circuits such as a current sampling module and a comparator. Furthermore, it cannot guarantee that the spread spectrum mode adaptive mode is disabled under no-load or very light load conditions. Summary of the Invention

[0011] The present invention provides a spread spectrum control implementation circuit for a buck converter in DCM mode, which can solve the above problems.

[0012] In order to solve the above problems, the technical solutions adopted by the present invention are as follows:

[0013] A circuit for implementing spread spectrum control in a step-down converter under DCM mode includes a spread spectrum control module, an adaptive on-time module, a PWM module, a logic control circuit, and a zero current detection module. The zero current detection module is used to perform zero current detection after a low-side tube is turned on, and when the detected inductor current is zero, instructs the logic control circuit to turn off the low-side tube. The spread spectrum control module is used to detect the load state based on the zero current detection signal, so that the load outputs a high level when the load is within a set spread spectrum control range. The adaptive on-time module is used to extend the high-side tube on-time when the spread spectrum control module outputs a high level. The high-side tube on-time is adaptively adjusted by the adaptive on-time module according to the converter's input voltage V in non-spread spectrum mode. IN and the output voltage V OUTThe PWM module is used to obtain the output voltage V OUT Falling to the voltage threshold V ref When the PWM module outputs a high level, when the time when the high level is output is longer than the set filtering time, the spread spectrum control module outputs a low level to instruct the logic control circuit to turn on the high-side tube.

[0014] Specifically, the spread spectrum control module performs spread spectrum control based on the number of times the zero current detection signal is triggered, and includes an adaptive load detection unit and a load state confirmation unit; the adaptive load detection unit is used to dynamically detect the zero current detection signal, and output a high level when the trigger time interval of the zero current detection signal is less than the set filtering time, and the load state confirmation unit accumulates the number of times the zero current detection signal is triggered to perform spread spectrum control, otherwise the load state confirmation unit does not accumulate the number of times the zero current detection signal is triggered.

[0015] Optionally, when the zero current detection signal is triggered 16 times, it is confirmed that the spread spectrum mode has been entered.

[0016] Specifically, the adaptive load detection unit includes rising edge delays B1 to B3, inverters N1 to N5, a NAND gate NAND, an AND gate AND, and a D flip-flop D1; inverter N1, rising edge delay B1, and inverter N2 are connected in stages; the first input terminal of the NAND gate NAND is connected to the output terminal of inverter N2, the second input terminal is connected to the input terminal of the rising edge delay B1, and the output terminal is connected to the Set terminal of the D flip-flop D1; inverter N3, rising edge delay B2, and the CLK terminal of the D flip-flop D1 are connected in stages; the Q terminal of the D flip-flop D1, inverter N4, and the first input terminal of the AND gate AND are connected in stages; the output terminal of the rising edge delay B3 is connected to inverter N5; the input terminals of inverters N1 and N3, and the second input terminal of the AND gate AND are all connected to the output terminal of the zero current detection module; the input terminal of the rising edge delay B3 is connected to the output terminal of the PWM module; and the output terminals of inverter N5 and the AND gate AND are both connected to the load state confirmation unit.

[0017] Specifically, the load state confirmation unit includes D flip-flops D2 to D5, whose Set terminals are all connected to the output terminal of the inverter N5; the CLK terminal of the D flip-flop D5 is connected to the output terminal of the AND gate AND; the D terminal of the D flip-flop D3 is connected to the output terminal of the AND gate The D terminal of D flip-flop D4 is connected to the CLK terminal of D flip-flop D2; The D end of D flip-flop D5 is connected to the CLK end of D flip-flop D3; The Q end of the D flip-flop D2 is the output end of the adaptive load detection unit.

[0018] Specifically, the adaptive on-time module includes an adaptive on-time circuit, a dynamic power bias comparator and a D trigger connected in stages; the output end of the D trigger is the on-time output end of the adaptive on-time module; the input end of the adaptive on-time circuit is connected to the output end of the spread spectrum control module.

[0019] Furthermore, the above-mentioned spread spectrum control implementation circuit further includes an enable control module, which is used to connect the spread spectrum control implementation circuit to a power supply voltage.

[0020] Furthermore, the above-mentioned spread spectrum control implementation circuit also includes a driving circuit for providing current to drive the external power tube to turn on and off after receiving the high-side tube conduction signal HS and the low-side tube conduction signal LS sent by the logic control circuit.

[0021] Furthermore, the above-mentioned spread spectrum control implementation circuit includes a voltage divider network for outputting the voltage V OUT Adjust the circuit ratio and the voltage after voltage division is recorded as V FB , used to provide to the PWM module.

[0022] Furthermore, the PWM module includes a comparator, an error amplification circuit and a ripple injection module; the output end of the ripple injection module is connected to the inverting input end of the comparator, the output end of the error amplification circuit is connected to the non-inverting input end of the comparator, and the output end of the comparator is the output end of the PWM module; the input end of the ripple injection module and the first input end of the error amplification circuit are both connected to the voltage divider network; the second input end of the error amplification circuit is connected to the reference voltage.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1) Load information is determined through simple control logic, avoiding the high complexity of current or voltage feedback in traditional converters and providing higher detection accuracy under light load or no load.

[0025] 2) The load status is determined by detecting the time interval of the zero current detection signal and the PWM signal. When the system enters the set load range, frequency expansion is performed to improve efficiency. The spread spectrum mode can be exited in time during load transients to ensure system stability and efficiency.

[0026] 3) Ability to adaptively adjust spread spectrum control when load changes, balance efficiency and ripple under different load conditions, and significantly improve system stability and performance.

[0027] 4) By changing the resistor ratio, the on-time is extended with a lower area solution. At the same time, a comparator that can adaptively compensate the response time according to the power supply voltage is implemented, ensuring the designed on-time value.

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, embodiments of the present invention are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 It is a structural schematic block diagram of the spread spectrum control implementation circuit;

[0031] Figure 2 It is a circuit example of a spread spectrum control module;

[0032] Figure 3 It is a circuit example of the adaptive on-time module;

[0033] Figure 4 It is a synchronous BUCK topology;

[0034] Figure 5 The flowchart of the spread spectrum control implementation method is shown in FIG. 1 , wherein the left flowchart is the spread spectrum control execution process, and the right flowchart is the spread spectrum control release process;

[0035] Figure 6 This is the load current and inductor current waveform of the buck converter in DCM;

[0036] Figure 7 It is the load variation waveform;

[0037] Figure 8 It is the output waveform of the spread spectrum control circuit;

[0038] Figure 9 is the output voltage waveform;

[0039] Figure 10 It is the load & ripple curve graph;

[0040] Figure 11 This is the load & efficiency curve. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0042] The embodiment of the present invention provides a spread spectrum control implementation circuit in the DCM mode of a buck converter, including a spread spectrum control module, an adaptive on-time module, a PWM module, a logic control circuit, a zero current detection module, an enable control module, a voltage divider network and a drive circuit. The connection relationship between the modules is as follows: Figure 1 shown.

[0043] The PWM module includes a comparator, an error amplifier circuit, and a ripple injection module; the output of the ripple injection module is connected to the inverting input of the comparator, the output of the error amplifier circuit is connected to the non-inverting input of the comparator, and the output of the comparator is the output of the PWM module; the input of the ripple injection module and the first input of the error amplifier circuit are both connected to a voltage divider network; the second input of the error amplifier circuit is connected to a reference voltage. The voltage divider network is used to adjust the output voltage V OUT The drive circuit is used to provide current to drive the external power tube to turn on and off after receiving the high-side tube conduction signal HS and the low-side tube conduction signal LS from the logic control circuit.

[0044] The method of the present invention utilizes a zero current detection signal ZCD, a comparator signal PWM, and a simple filtering circuit and digital logic to implement adaptive spread spectrum control, significantly reducing the area and complexity of the required circuit while avoiding additional power consumption and ensuring low-power operation. Most importantly, the control scheme can adaptively adjust the spread spectrum within a controllable load range, which not only optimizes system efficiency but also effectively reduces output voltage ripple under no-load and light-load conditions.

[0045] In order to reasonably configure the various filtering times in the present invention, the relationship between the interval time between two ZCD signals and the load current is described here. Figure 6 It can be seen that in DCM, the ripple on the output capacitor is when the inductor current is higher than the load current. The inductor current supplies energy to the load and stores energy in the output capacitor, thus causing the output ripple to increase.

[0046] Figure 6 The T1 time is the time it takes for the inductor current to rise from zero to the load current when the high-side transistor is turned on. time, is the slope of the inductor current change, L is the inductor value, V IN is the input supply voltage, V OUT is the output voltage, the formula is:

[0047]

[0048] Figure 6 The T2 time is the time it takes for the inductor current to drop from the load current value to zero when the low-side transistor is turned on. The formula is:

[0049]

[0050] Figure 6 The T3 time is, the inductor current I L Greater than the load current I LOAD The time is also the source of the output capacitor ripple. Since the chip design will perform phase-locked loop processing on the high-side tube conduction time and the low-side tube conduction time, the default high-side tube conduction time is T HZ and low-side transistor conduction time T LS The total time T HS+LS Approximately fixed, the high-side tube conduction switching frequency F HS The switching frequency F of the low-side tube is LS The total switching frequency F HS+LS is also approximately fixed. The formula is:

[0051]

[0052] Figure 6 The area of the shaded triangle is the amount of charge transferred to the output capacitor. , the formula is:

[0053]

[0054] The amount of charge accumulated on the capacitor and the output capacitance , we can get the ripple voltage on the output capacitor The changes are:

[0055]

[0056] According to the Adaptive Constant On Time (ACOT) control method, when the output voltage drops to the reference value set by the chip in steady state, that is, when the next switching cycle begins, the time when both the high-side and low-side transistors are not conducting can be calculated, that is, the high-impedance time. N represents an unspecified ZCD signal trigger, N+1 is the next ZCD signal trigger, and the time between ZCD signals is

[0057]

[0058]

[0059] Where DVV is the duty cycle of the buck circuit voltage conversion, that is, the ratio of the output voltage to the input voltage.

[0060] The spread spectrum control module in the present invention performs spread spectrum control based on the triggering times of the zero current detection signal. It detects the load state and confirms that the load outputs a high level within the set spread spectrum control range to control the adaptive on-time module to extend the on-time. Figure 2 As shown, the spread spectrum control module includes an adaptive load detection unit and a load status confirmation unit.

[0061] The adaptive load detection unit includes rising edge delays B1 to B3, inverters N1 to N5, a NAND gate (NAND), an AND gate (AND), and a D flip-flop D1. Inverter N1, rising edge delay B1, and inverter N2 are connected in stages. The first input of the NAND gate (NAND) is connected to the output of inverter N2, the second input is connected to the input of the rising edge delay B1, and the output is connected to the Set terminal of the D flip-flop D1. Inverter N3, rising edge delay B2, and the CLK terminal of the D flip-flop D1 are connected in stages. The Q terminal of the D flip-flop D1, inverter N4, and the first input of the AND gate (AND) are connected in stages. The output of the rising edge delay B3 is connected to inverter N5. The inputs of inverters N1 and N3, as well as the second input of the AND gate (AND) are all connected to the output of the zero current detection module. The input of the rising edge delay B3 is connected to the output of the PWM module. The outputs of inverter N5 and the AND gate (AND) are both connected to the load status confirmation unit. The load status confirmation unit includes D flip-flops D2~D5, whose Set terminals are connected to the output terminal of inverter N5; the CLK terminal of D flip-flop D5 is connected to the output terminal of AND gate AND; the D terminal of D flip-flop D3 is connected to the output terminal of AND gate The D terminal of D flip-flop D4 is connected to the CLK terminal of D flip-flop D2; The D end of D flip-flop D5 is connected to the CLK end of D flip-flop D3; The Q end of the D flip-flop D2 is the output end of the adaptive load detection unit.

[0062] The specific circuit of the adaptive on-time module is as follows Figure 3 As shown, the circuit includes resistors R1, R2, R3, R4, R5, R6, R7, R8, and R9; capacitor C1; NMOS transistors NM1, NM2, NM3, NM4, NM5, NM6, NM7, NM8, NM9, and NM10; PMOS transistors PM1, PM2, PM3, PM4, PM5, PM6, PM7, and PM8; inverters INV1, INV2, and INV3; and D-type flip-flop Diff1. Resistors R1 through R5, inverter INV1, NMOS transistors NM1, NM2, and NM3, and capacitor C1 form an adaptive on-time circuit. Components other than D-type flip-flop Diff1 and the adaptive on-time circuit form a dynamic power supply bias comparator.

[0063] The working principle of the above spread spectrum control module implementation method is as follows: when the system is working in DCM mode, the load current is too low or completely unloaded, when the ZCD signal outputs a high level and is transmitted to the CLK terminal of the D1 trigger after the B2 rising edge delay, the D1 trigger Q terminal outputs a high level, and after being inverted by the N4 inverter, the output is a low level. The subsequent counter module cannot collect the ZCD signal for counting, so the system is prohibited from entering the spread spectrum mode. The design of the B2 rising edge delay time can be combined with the relationship between the high impedance time and the load T HS+LS 、T HZ The design is based on theoretical formulas such as [1]. To achieve dynamic load status detection, the Set terminal of the D1 flip-flop generates a reset signal on the falling edge of the ZCD signal, resetting the D1 flip-flop's Q output to a low level, allowing it to be detected again when the next ZCD signal arrives. As the system load current increases, the time interval between two ZCDs becomes less than the rising edge delay of R2. The D1 flip-flop's CLK signal is unable to detect the rising edge signal, and the D1 flip-flop's Q output remains low. The signal output by the N4 inverter remains high, allowing the AND gate to effectively collect and accumulate the ZCD signal. When the number of ZCD signals reaches 16, the output terminal Q of the D5 flip-flop goes high, and the adaptive control BUCK circuit enters frequency extension mode, extending the on-time of the high-side transistor HS. As the load current continues to change, the output voltage takes longer to reach the system's set output voltage. Therefore, the pulse width of the comparator's output signal, PWM, will also remain high for a correspondingly longer period of time. This high-level duration increases to a value greater than the B3 rising edge delay time. At this point, the N5 inverter outputs a low-level signal to reset the entire counter module. The output signal indicator becomes low, and the system automatically exits frequency expansion mode. The design of the B3 rising edge delay time requires comprehensive consideration of the PWM comparator's response time, drive time, dead time, and peripheral components.

[0064] The working principle of the above adaptive on-time module implementation method is as follows:

[0065] When the system high-side transistor conduction signal HS is high, the D flip-flop D1 is reset, the TON signal output is low, and the NM3 is disconnected. The system power supply VINH charges the capacitor C1 through the resistor R2. The VN voltage is the comparator inversion threshold point, and the voltage at this point can be obtained by the formula:

[0066]

[0067] From the capacitor current formula we can get:

[0068]

[0069] V gs,NM1is the voltage between the gate and source terminals of the NM1 tube. Substituting the VN formula into it, we can get:

[0070]

[0071] As can be seen from this formula, the TON time will be adaptively adjusted according to the duty cycle DVV. However, the time from the HS signal going high to the TON signal outputting a high level still needs to take into account the comparator response time Td. Therefore, the total TON time should be:

[0072]

[0073] When the ADDTON signal is high, the TON time becomes:

[0074]

[0075] It can be seen that resistor R4 intervenes at this point, increasing the VN voltage and thus extending the TON time, thereby prolonging the on-time of the system's high-side transistor HS. The extended TON time can be designed to optimize the output voltage ripple and load efficiency based on a trade-off. In this solution, increasing the VN voltage by changing the ratio saves a significant amount of chip area compared to simply changing capacitors C1 or R2.

[0076] As can be seen from the TON formula, when the VINH voltage increases to a certain extent, the denominator of the first term of the TON equation increases, so the first term will become smaller. At this time, the error caused by the comparator response time Td will increase. Therefore, in this circuit design, a comparator current offset related to VINH is specially designed for compensation. gs,NM5 is the voltage between the gate and source terminals of the NM5 tube, and the current formula is:

[0077]

[0078] It can be seen that VINH is positively correlated with the current bias. When the VINH voltage increases, making the first term in the TON formula smaller, the bias current will also increase accordingly, thereby improving the response time of the comparator and ensuring the designed value of the TON time.

[0079] Therefore, in this method, the spread spectrum control module is responsible for real-time load status detection and status confirmation. The ADDTON signal it outputs serves as a control signal for the adaptive on-time module, instructing it to enable or disable spread spectrum mode. The TON signal output by the adaptive on-time module instructs the logic control circuit and its driver circuit whether to execute spread spectrum operation.

[0080] Combine Figures 1 to 5As shown, the spread spectrum control implementation method of the spread spectrum control implementation circuit in the DCM mode of the buck converter according to the embodiment of the present invention includes a spread spectrum control execution process and a spread spectrum control release process.

[0081] like Figure 5 As shown in the left figure, the spread spectrum control execution process includes:

[0082] 1. The chip power supply voltage is established, the enable port is at a high level, the enable control module enables the spread spectrum control circuit to connect to the power supply voltage, and the enable control module controls the chip to start working.

[0083] 2. At this time, the chip works in the light-load DCM mode, and the zero current detection module will Figure 4 When the SN,ON control low-side tube is turned on, the inductor energy provides energy to the energy storage capacitor and the load end through the arrow indication. Figure 4 The current value of the inductor L shown is determined and judged. When the inductor current is zero, a high level is output to instruct the logic control circuit to turn off the low-side tube.

[0084] 3. The spread spectrum control module is used to detect the load state based on the zero current detection signal, so that the load outputs a high level when it is within the set spread spectrum control range. Specifically:

[0085] The adaptive load detection unit dynamically detects the ZCD (zero current detection) signal. When the filter time is greater than or equal to the set filter time Td, the output is low level. The load status confirmation unit cannot accumulate the number of triggering times of the zero current detection signal to perform spread spectrum control, and the adaptive load detection maintains real-time detection;

[0086] As the load current increases, when the time interval If the filter time is less than the set filtering time Td, the adaptive load detection unit shields the signal output to a high level, and the load status confirmation unit receives the ZCD signal. The load status confirmation unit ensures the accuracy of the control logic and avoids system malfunctions. This module is responsible for accumulating and counting the ZCD signal. When the ZCD signal is triggered 16 times, it confirms the entry into spread spectrum mode.

[0087] 4. When the spread spectrum control module outputs a high level, it controls the adaptive on-time module to expand the time and extend the high-side tube on-time. The high-side tube on-time is adaptively adjusted by the adaptive on-time module according to the input voltage V IN and the output voltage V OUT Get. Combine Figure 3 and Figure 5As shown, the ADDTON signal output by the spread spectrum control module is high, the NM2 tube is disconnected, and the R4 resistor is inserted to increase the TON conduction time (the R4 resistor is inserted to adjust the resistance ratio). The specific implementation method is described in the above Figure 3 The working principle has been explained.

[0088] 5. When the TON on-time of the adaptive on-time module is extended, the TON signal will be transmitted to the logic control circuit, such as Figure 1 When TON is at a high level, the logic control circuit will control the high-side tube (i.e., high-side power tube) to conduct and output a high-level signal HS, which is then provided to the drive circuit.

[0089] 6. If Figure 1 As shown, the high-side tube conduction signal HS of the logic control circuit is connected to the drive circuit. The HS signal is high, which indicates that the drive circuit PDR signal outputs a high level. Figure 4 As shown, PDR serves as the output signal of the driving circuit to drive the external high-side power tube to turn on, that is, the power passes through the high-side power tube SP, and the inductor L supplies energy to the energy storage capacitor and the load.

[0090] like Figure 5 As shown in the right figure, the spread spectrum control release process includes:

[0091] 1. At this time, the system is still working in DCM mode under spread spectrum control.

[0092] 2. As the load current increases, more energy needs to be provided to the load in each cycle, so the output voltage rises more slowly and the comparator maintains a high level for a longer time.

[0093] 3. The PWM module's comparator outputs a high level, prompting the logic control circuit to turn on the high-side tube to replenish energy. When the load increases to the time when the PWM module's comparator outputs a high level When it is higher than the set filtering time Td, the spread spectrum control module outputs a low level.

[0094] 4. The spread spectrum control module outputs a low level to control the adaptive on-time module to turn off the expansion of the on-time.

[0095] 5. The high-side tube in the logic control circuit is turned on, and the output high-side tube conduction signal HS, as well as the drive circuit output signal PDR, will also turn off the extension of the conduction time and exit the frequency extension mode.

[0096] Therefore, the present invention enables the system to perform frequency expansion only within the set load range. Figure 4 The conduction time of the high-side transistor SP of the synchronous buck circuit shown is prolonged, and the circuit will not enter this mode under light load, no load or heavy load conditions.

[0097] Figure 7 、 Figure 8 and Figure 9 The following is a schematic diagram of the effects of an embodiment of the present invention, which are respectively a load change waveform diagram, a spread spectrum control circuit output waveform diagram, and an output voltage waveform diagram. Comparing the load change waveform diagram and the spread spectrum control circuit output waveform, it can be seen that when the load current is extremely low or completely unloaded, the control circuit always outputs a level, and the system does not perform a spread spectrum operation. When the load current enters the design range, the control circuit output is a high level, and the adaptive on-time module is controlled to increase the TON time. The system starts to spread the spectrum and increase the high-side tube conduction time, thereby extending the high-resistance time to improve system efficiency. As the load current continues to increase, the adaptive spread spectrum control module will automatically output a low level to release the spread spectrum control. As shown in the output voltage waveform diagram, the circuit without the present invention does not perform a spread spectrum operation for the load. Under light load, the cycle is smaller, the switching loss is higher, and the equivalent time of the high-resistance and low-power consumption stage is shorter, which cannot effectively improve the system efficiency under light load.

[0098] The present invention is functionally verified by simulation:

[0099] The peripheral parameters of the buck circuit are: Ind_4R7_ETQP3M4R7KPV model: 2.2uH inductor, 22uF output capacitor, 30mohm equivalent output parasitic resistance, PMV27UPEA high-side power transistor model, and PMV65UNEA low-side power transistor model.

[0100] like Figure 10 and Figure 11 As shown, from the load, ripple and efficiency curves, it can be seen that the present invention can prohibit entering the spread spectrum mode under low load or complete no-load, so that the output voltage ripple is less than 10mv. And the frequency expansion operation is performed within the set load range, which will be greatly improved to more than 70%. The ripple amount after the spread spectrum operation can be designed in a compromise according to the formula and the actual circuit environment. As the load increases, the control circuit will also adaptively exit the spread spectrum mode according to the design and return to the normal control mode to avoid stability interference caused by large ripple. In summary, the scheme can adaptively control the opening and closing of the spread spectrum mode, and successfully achieve a good balance between efficiency and ripple under light load.

[0101] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A circuit for implementing spread spectrum control in a buck converter DCM mode, characterized in that: The invention comprises a spread spectrum control module, an adaptive on-time module, a PWM module, a logic control circuit and a zero current detection module; the zero current detection module is used to perform zero current detection after the low-side tube is turned on, and when the detected inductor current is zero, it instructs the logic control circuit to turn off the low-side tube; the spread spectrum control module is used to detect the load state based on the zero current detection signal, so that the load outputs a high level when the load is within the set spread spectrum control range; the adaptive on-time module is used to extend the high-side tube on-time when the spread spectrum control module outputs a high level, and the high-side tube on-time is adaptively adjusted by the adaptive on-time module according to the input voltage V of the converter in the non-spread spectrum mode. IN and the output voltage V OUT The PWM module is used to obtain the output voltage V OUT Falling to the voltage threshold V ref When the PWM module outputs a high level, when the time for which the PWM module outputs a high level is longer than the set filtering time, the spread spectrum control module outputs a low level, instructing the logic control circuit to turn on the high-side tube; The spread spectrum control module performs spread spectrum control based on the number of times the zero current detection signal is triggered, and includes an adaptive load detection unit and a load state confirmation unit; the adaptive load detection unit is used to dynamically detect the zero current detection signal and output a high level when the trigger time interval of the zero current detection signal is less than the set filtering time; the load state confirmation unit accumulates the number of times the zero current detection signal is triggered to perform spread spectrum control; otherwise, the load state confirmation unit does not accumulate the number of times the zero current detection signal is triggered.

2. The spread spectrum control implementation circuit according to claim 1, characterized in that: When the zero current detection signal is triggered 16 times, it is confirmed that the spread spectrum mode has been entered.

3. The spread spectrum control implementation circuit according to claim 1, characterized in that: The adaptive load detection unit includes rising edge delays B1-B3, inverters N1-N5, a NAND gate, an AND gate, and a D flip-flop D1; inverter N1, rising edge delay B1, and inverter N2 are connected in stages; the first input terminal of the NAND gate is connected to the output terminal of inverter N2, the second input terminal is connected to the input terminal of the rising edge delay B1, and the output terminal is connected to the Set terminal of the D flip-flop D1; inverter N3, rising edge delay B2, and the CLK terminal of the D flip-flop D1 are connected in stages; the Q terminal of the D flip-flop D1, inverter N4, and the first input terminal of the AND gate are connected in stages; the output terminal of the rising edge delay B3 is connected to inverter N5; the input terminals of inverters N1 and N3, and the second input terminal of the AND gate are all connected to the output terminal of the zero current detection module; the input terminal of the rising edge delay B3 is connected to the output terminal of the PWM module; the output terminals of inverter N5 and the AND gate are both connected to the load state confirmation unit.

4. The spread spectrum control implementation circuit according to claim 3, characterized in that: The load state confirmation unit includes D flip-flops D2 to D5, whose Set terminals are all connected to the output terminal of the inverter N5; the CLK terminal of the D flip-flop D5 is connected to the output terminal of the AND gate AND; the D terminal of the D flip-flop D3 is connected to the output terminal of the AND gate The D terminal of D flip-flop D4 is connected to the CLK terminal of D flip-flop D2; The D end of D flip-flop D5 is connected to the CLK end of D flip-flop D3; The Q end of the D flip-flop D2 is the output end of the adaptive load detection unit.

5. The spread spectrum control implementation circuit according to claim 1, characterized in that: The adaptive on-time module includes an adaptive on-time circuit, a dynamic power bias comparator and a D trigger connected in stages; the output end of the D trigger is the on-time output end of the adaptive on-time module; the input end of the adaptive on-time circuit is connected to the output end of the spread spectrum control module.

6. The spread spectrum control implementation circuit according to claim 1, characterized in that: It also includes an enabling control module, which is used to connect the spread spectrum control implementation circuit to the power supply voltage.

7. The spread spectrum control implementation circuit according to claim 1, characterized in that: It also includes a driving circuit for providing current to drive the external power tube to turn on and off after receiving the high-side tube conduction signal HS and the low-side tube conduction signal LS sent by the logic control circuit.

8. The spread spectrum control implementation circuit according to claim 1, characterized in that: Includes a voltage divider network for the output voltage V OUT Adjustment is done by circuit ratio.

9. The spread spectrum control implementation circuit according to claim 8, characterized in that: The PWM module includes a comparator, an error amplifier circuit and a ripple injection module; the output end of the ripple injection module is connected to the inverting input end of the comparator, the output end of the error amplifier circuit is connected to the non-inverting input end of the comparator, and the output end of the comparator is the output end of the PWM module; the input end of the ripple injection module and the first input end of the error amplifier circuit are both connected to the voltage divider network; the second input end of the error amplifier circuit is connected to the reference voltage.

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