Hardware design of novel picosecond-level digital delay pulse generator

Abstract

The invention discloses a novel picosecond-level digital delay pulse generator hardware design, relates to the technical field of signal measurement, and is applied to delay and generation of digital pulses. Comprising an external trigger interface circuit which is used for converting an external signal into a level signal which can be identified by SerDes of an FPGA; the FPGA master control module is used for receiving and sending pulses; the whole hardware design integration is high, the delay accuracy reaches 10ps when the pulse delay is set to be 1us, the jitter RMS value is 10.7 ps, the minimum delay time is not larger than 30ns, and the bandwidth for processing pulse signals can reach 29GHz.

Description

Technical Field

[0001] The invention relates to the technical field of signal measurement, in particular to a novel hardware design of a picosecond digital delayed pulse generator. Background Art

[0002] The digital delayed pulse generator is a high-precision, multifunctional device. It is mostly used in scientific research, laboratory testing, and precision measurements such as radar and sonar to provide reliable time delay and trigger signals. The digital delayed pulse generator usually generates a delayed output pulse signal based on the input pulse signal through a combination of a trigger and a delay circuit.

[0003] With the continuous development of measurement technology, the requirements for the delay of digital pulses are getting higher and higher. For example, dynamic shooting of plasma and nuclear reaction requires more precise delay to control the trigger shooting of each part of the camera.

[0004] Traditional digital delay pulse generators have certain limitations in communication distance, transmission delay, and communication stability.

[0005] Disadvantage 1: The accuracy of the delay time setting is limited by the hardware, and the accuracy of the delay value setting is at the ns level; Disadvantage 2: The jitter of the generated delayed pulse is large, and the RMS jitter is higher than 19ps; Disadvantage 3: The minimum delay value is higher than 70ns, and the maximum value is limited by hardware; Disadvantage 4: The jitter value between channels is large, and the jitter is the superposition of two items, that is, the jitter value of the time-base circuit + the jitter value of the delay circuit; Disadvantage 5: The bandwidth that can process pulse signals is low. Summary of the invention

[0006] The purpose of the present invention is to provide a novel hardware design of a picosecond digital delayed pulse generator to solve the problems raised in the above background technology.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions: a new hardware design of a picosecond digital delay pulse generator, comprising: An external trigger interface circuit is used to convert an external signal into a level signal recognizable by the SerDes of the FPGA; FPGA master control, pulse reception and transmission; Delay fine-tuning circuit, used to improve the resolution of delay setting; An output interface circuit, used for setting the amplitude of the output pulse; The Ethernet circuit is used to receive control instructions from the Ethernet and set the working parameters inside the logic, such as delay time, trigger type, etc.

[0008] Furthermore, the FPGA master control uses FPGA-based high-speed NRZ SerDes to perform coarse delay adjustment.

[0009] Furthermore, the delay fine-tuning circuit uses a programmable delay chip to perform delay fine-tuning.

[0010] Furthermore, the output interface circuit uses a programmable operational amplifier to adjust the amplitude.

[0011] Compared with the prior art, the beneficial effects achieved by the present invention are: 1. The accuracy of the delay setting in the prior art is (inherent error + (crystal oscillator time base error * delay)), and the inherent error is at the ns level; the entire design of the present invention has only one crystal oscillator, and the accuracy of the delay setting is (crystal oscillator time base error * delay); assuming that the prior art and this solution both use a 125MHz, ±0.01ppm crystal oscillator; when the delay is 1us, the actual delay value calculated is: 1000 / (125±125 / 100000000)*125us, which is about 999.99999~1000.00001us, and the error is 0.01ns; the accuracy is improved from 1.01ns to 0.01ns; 2. The jitter of the generated delay pulse in the existing technology is relatively large, and the RMS of the existing technology is not less than 19ps; the jitter in the current technology exists in two places, the jitter caused by high-speed SerDes acquisition and the jitter caused by the programmable delay chip. Assuming that the high-speed SerDes uses Intel's Agliex series FPGA to support the NRZ type with a maximum of 58Gbps, the delay error during acquisition will be evenly distributed between 0 and 17.24ps. When the 19 sampling errors are (0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718), the RMS value of the jitter is 10.5ps. Assuming that the programmable delay chip uses hmc856, the RMS of the jitter is 0.2ps. The total RMS value is 10.7ps; 3. The existing technology often uses TDC (Time digital converter) to compensate for the jitter of pulse output. The maximum value is subject to hardware constraints, and the minimum delay time is subject to hardware constraints, usually not less than 70ns. The current technology FPGA processing delay is up to 28ns, and the inherent delay of the programmable delay chip is 255ps. Assuming that the transmission delay of the hardware wiring interface circuit is 1ns, the minimum delay is 29.255ns; 4. The jitter value between channels in the prior art is large, and the jitter value is the jitter value of the crystal oscillator time base circuit + the jitter value of the delay circuit. The jitter between channels in the present invention is only the jitter value of the crystal oscillator time base circuit; 5. The prior art usually uses TDC (Time digital converter) for compensation calculation, which has a long calculation cycle and generally processes a maximum bandwidth of 125MHz. The present invention uses NRZ SerDes, and when using 58Gbps SerDes, the maximum bandwidth that can be processed is 29GHz. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings: Figure 1 This is a hardware composition diagram of a new type of picosecond digital delay pulse generator hardware design in the present invention; Figure 2 This is a schematic diagram of the FPGA main control part of the hardware design of a new type of picosecond digital delay pulse generator in the patent of this invention. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] See also Figure 1 The present invention provides a technical solution: a new hardware design of a picosecond digital delay pulse generator. The new picosecond digital delay pulse generator is based on FPGA as the main hardware platform. The hardware circuit is mainly composed of an external trigger interface circuit, an FPGA main control part, a delay fine-tuning circuit, an output interface circuit, and an Ethernet circuit. The clock of the entire hardware design adopts homologous processing to effectively eliminate the error of clock periodic jitter.

[0015] 1) External trigger interface circuit The external trigger interface circuit is used to convert the external signal into a level signal that can be recognized by the SerDes of the FPGA.

[0016] 2) FPGA master control part Figure 2The figure shows the FPGA main control part, which is composed of FPGA, configuration chip and crystal oscillator. The pulse reception and transmission adopt the high-speed SerDes transceiver circuit built in FPGA. In order to ensure low jitter between the transmission pulse and the reception pulse, the clock inside the receiving pulse channel SerDes is used as the reference clock for the transmission pulse. The selected FPGA has 16 channels of SerDes, each 4 in a group. One channel is selected as the pulse reception, and the remaining 3 groups of 12 channels are selected as the pulse output. The FPGA adopts 58Gbps NRZ SerDes with a jitter RMS of 10.7ps.

[0017] 3) Delay fine-tuning circuit Used to improve the resolution of delay setting, the programmable delay chip HMC856 can achieve a delay step resolution of 3ps.

[0018] 4) Output interface circuit The output interface circuit uses Analog devices' AD8370 digitally controlled programmable operational amplifier to set the amplitude of the output pulse. It can be controlled through a three-wire digital interface, allowing the user to obtain fine gain control; it supports adjusting the output peak-to-peak value to 8.4Vpp.

[0019] 5) Ethernet circuit Ethernet reception is used to receive control instructions from Ethernet and set the working parameters within the logic, such as delay time, trigger type, etc.

[0020] The external pulse first enters the external trigger interface circuit, which converts the external signal into a level signal recognizable by the FPGA's SerDes; the FPGA sets the pulse trigger mode according to the Ethernet instructions, roughly adjusts the delay time, and outputs instructions to the delay fine-tuning circuit and the output interface circuit; the pulse passes through the FPGA and is output to the delay fine-tuning circuit, which fine-tunes the pulse at the 3ps level; the pulse is finally output through the output interface circuit, which adjusts the pulse amplitude according to the FPGA's instructions.

[0021] The above is a detailed introduction to the hardware design of the new digital delayed pulse generator of the picosecond level of the present invention. It should be understood by those skilled in the art that the embodiments of the present invention can be provided as methods, designs, or FPGA logic products. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention can take the form of a relay scheme implemented on one or more FPGA hardware that includes a hardware design language. Those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these changes and variations.

[0022] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A new hardware design of picosecond digital delay pulse generator, characterized by: include: An external trigger interface circuit is used to convert an external signal into a level signal recognizable by the SerDes of the FPGA; FPGA master control, pulse reception and transmission; Delay fine-tuning circuit, used to improve the resolution of delay setting; An output interface circuit, used for setting the amplitude of the output pulse; The Ethernet circuit is used to receive control instructions from the Ethernet and set the working parameters inside the logic, such as delay time, trigger type, etc.

2. The hardware design of the novel picosecond digital delay pulse generator according to claim 1 is characterized in that: The FPGA master control uses FPGA-based high-speed NRZ SerDes for coarse delay adjustment.

3. According to the hardware design of the novel picosecond digital delay pulse generator of claim 1, it is characterized by: The delay fine-tuning circuit uses a programmable delay chip to perform delay fine-tuning.

4. The new picosecond digital delay pulse generator hardware design according to claim 1 is characterized by: The output interface circuit uses a programmable operational amplifier for amplitude adjustment.

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