Trigger structure for single event upset detection and self-recovery
By designing a flip-flop structure integrating multi-inverter circuit, latch structure and clock control signal transmission structure, detection and self-recovery of single-particle flips are realized, and the problem of improving the soft error rate of the integrated circuit in space radiation environment is solved, and the resistance to radiation reinforcement capability is improved.
Patent Information
- Application Number
- CN202411892767.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-05-16
AI Technical Summary
The prior art is difficult to effectively reduce the single-particle soft error rate of integrated circuits in space radiation environments, especially in high-frequency and three-dimensional multi-gate structures, the sensitivity and complexity of integrated circuits to single-particle radiation are significantly increased.
A single-particle flip-detection and self-recovery trigger structure is designed, including a multi-inverter circuit, a latch structure, a clock control signal transmission structure, a delay filter structure and an exclusive-OR gate. Through the coordinated work of these components, the detection and self-recovery of single-particle flip are achieved.
This design effectively reduces the soft error rate of single-particle, improves the tolerance of integrated circuits to single-particle radiation, and is suitable for integrated circuit designs at different process nodes, with good adaptability.
Smart Images
Figure CN120017022A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of radiation-resistant hardened circuits, and in particular to a trigger structure for single-particle upset detection and self-recovery. Background Art
[0002] The high-reliability application of integrated circuits in space radiation environments has attracted increasing attention. When charged particles in space pass through semiconductor materials, radiation-induced charges are generated in the materials. These charges are collected by the device and have a series of effects. Transient voltages are generated at key nodes. If they change the state of the circuit in some way, they may cause single-particle soft errors. Single-particle transients (SET) occur in combinational logic circuits. If this transient voltage has sufficient amplitude and the propagation process meets certain timing rules, it will generate an erroneous voltage value that propagates to the output of the trigger, causing the output state to flip. At the internal nodes of the storage unit, if the collected charge is sufficient to flip the stored logical state, it will cause a single-particle upset (SEU), which is another mechanism that causes single-particle soft errors. Single-particle soft errors are an important issue that affects the space application of integrated circuits. For advanced process integrated circuits, their characteristics include reduced transistor feature size, increased operating frequency, and the transition from planar transistor structure to three-dimensional (3D) multi-gate transistor structure, which significantly increases the sensitivity and complexity of integrated circuits to single-particle radiation.
[0003] Integrated circuits for space applications need to pay attention to the single-particle soft error rate. How to reduce the single-particle soft error rate is a current research hotspot. Relevant researchers have been facing the challenge of improving the single-particle radiation tolerance of integrated circuits through methods such as radiation hardening design. At the same time, as applications have higher and higher requirements for the conventional performance of integrated circuits, comprehensive radiation hardening design has become another challenge. Summary of the invention
[0004] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art and provide a trigger structure for single particle upset detection and self-recovery, which can be applied to a pipeline system to improve the pipeline system's ability to resist single particle upset.
[0005] The technical solution of the present invention is:
[0006] A trigger structure for single-particle upset detection and self-recovery, comprising a first inverter circuit, a second inverter circuit, a third inverter circuit, a fourth inverter circuit, a fifth inverter circuit, a sixth inverter circuit, a first clock-controlled signal transmission structure, a first latch structure, a second latch structure, a two-input data selector, a delay filter structure and a clock-controlled XOR gate;
[0007] The input end of the first inverter circuit is the data input end of the trigger structure, and the output end of the first inverter circuit is simultaneously connected to the data input end of the first clock-controlled signal transmission structure and the data input end of the first latch structure; the input end of the fifth inverter circuit is simultaneously connected to the output end of the first clock-controlled signal transmission structure and the output end of the sixth inverter circuit, the input end of the sixth inverter circuit is connected to the output end of the two-input data selector, and the output end of the fifth inverter circuit is simultaneously connected to the first input end of the two-input data selector and the data input end of the second latch structure; the data output end of the first latch structure is simultaneously connected to the input end of the second inverter circuit and the second input end of the two-input data selector; the output end of the second inverter circuit is connected to the second input end of the clock-controlled XOR gate; the data output end of the second latch structure is connected to the input end of the third inverter circuit, and the output end of the third inverter circuit is connected to the first input end of the clock-controlled XOR gate;
[0008] The input end of the fourth inverter circuit is the clock input end of the trigger structure, connected to the clock input end CP1 of the signal transmission structure controlled by the first clock, the clock input end CK2 of the second latch structure, and the input end of the delay filter structure; the output end of the fourth inverter circuit is connected to the clock input end CP2 of the signal transmission structure controlled by the first clock, and the clock input end CK1 of the second latch structure;
[0009] The clock input terminal CK2 of the first latch structure is connected to the second output terminal of the delay filter structure, and the clock input terminal CK1 of the first latch structure is connected to the first output terminal of the delay filter structure and the clock input terminal of the clock-controlled XOR gate; the output terminal of the clock-controlled XOR gate is connected to the data selection terminal of the two-input data selector.
[0010] Preferably, the first latch structure and the second latch structure are of the same structure, and both include a second clock-controlled signal transmission structure, a seventh inverter circuit and an eighth inverter circuit;
[0011] The data input end of the signal transmission structure controlled by the second clock is the data input end of the latch structure, the clock input end CP1 of the signal transmission structure controlled by the second clock is the clock input end CK1 of the latch structure, the clock input end CP2 of the signal transmission structure controlled by the second clock is the clock input end CK2 of the latch structure, and the output end of the signal transmission structure controlled by the second clock is connected to the input end of the seventh inverter circuit and the output end of the eighth inverter circuit;
[0012] The output end of the seventh inverter circuit is connected to the input end of the eighth inverter circuit to serve as the output end of the latch structure.
[0013] Preferably, the signal transmission structure controlled by the first clock and the signal transmission structure controlled by the second clock are of the same structure, and both include a first PMOS, a second PMOS, a first NMOS, and a second NMOS;
[0014] The gate of the first PMOS is connected to the gate of the second NMOS, serving as a data input terminal of a clock-controlled signal transmission structure; the source of the first PMOS is connected to a power supply VDD; the drain of the first PMOS is connected to a source of the second PMOS; the gate of the second PMOS serves as a clock input terminal CP1 of the clock-controlled signal transmission structure; the drain of the second PMOS is connected to the source of the first NMOS and serves as an output terminal of the clock-controlled signal transmission structure; the gate of the first NMOS serves as a clock input terminal CP2 of the clock-controlled signal transmission structure; the source of the first NMOS is connected to the drain of the second NMOS; and the source of the second NMOS is connected to a power ground GND.
[0015] Preferably, the clock-controlled XOR gate comprises a two-input XOR gate and a two-input AND gate;
[0016] The first input end of the two-input XOR gate is used as the first input end of the clock-controlled XOR gate, the second input end of the two-input XOR gate is used as the second input end of the clock-controlled XOR gate, and the output end of the two-input XOR gate is connected to the second input end of the two-input AND gate;
[0017] The first input terminal of the two-input AND gate serves as the clock input terminal CLK_RH of the clock-controlled XOR gate, and the output terminal of the two-input AND gate serves as the output terminal of the clock-controlled XOR gate.
[0018] Preferably, the delay filter structure includes a third PMOS, a fourth PMOS, a third NMOS, a fourth NMOS, a delay circuit and a ninth inverter circuit;
[0019] The gate of the third PMOS, the gate of the fourth NMOS and the input end of the delay circuit are connected together as the input end of the delay filter structure, the source of the third PMOS is connected to the power supply VDD, the drain of the third PMOS is connected to the source of the fourth PMOS, the gate of the fourth PMOS and the gate of the third NMOS are connected together and connected to the output end of the delay circuit, the drain of the fourth PMOS is connected to the drain of the third NMOS as the second output end of the delay filter structure, and is connected to the input end of the ninth inverter circuit, the source of the third NMOS is connected to the drain of the fourth NMOS, and the source of the fourth NMOS is connected to the power ground GND; the output end of the ninth inverter circuit serves as the first output end of the delay filter structure.
[0020] Preferably, the first inverter circuit, the second inverter circuit, and the third inverter circuit constitute a data transmission circuit; the first latch structure constitutes a detection latch structure; the second latch structure constitutes a slave latch structure; the first clock-controlled signal transmission structure, the fifth inverter circuit, the sixth inverter circuit, and the two-input data selector constitute a master latch structure; the fourth inverter circuit and the delay filter structure constitute a clock output circuit.
[0021] Preferably, the first inverter circuit is used to invert the input signal of the memory and input it into the signal transmission structure and the first latch structure controlled by the first clock; the second inverter circuit is used to invert the output signal of the first latch structure, and the third inverter circuit is used to invert the output signal of the second latch structure and output the signal Q;
[0022] The first latch structure is used as a detection latch structure to latch input data after a certain delay, and the latched data is used as recovery data after a single-particle upset is detected; the second latch structure is used as a slave latch structure of the trigger to realize the trigger function;
[0023] The first input end of the clock-controlled XOR gate is connected to the output Q of the third inverter circuit, and the second input end is connected to the output Q_R of the second inverter circuit. By comparing the two input signals, a single-particle upset detection signal is generated as the circuit output D_Error.
[0024] Preferably, when the clock signal CLK is 0, the data is latched in the main latch structure through the first inverter circuit and the first clock-controlled signal transmission structure from the input terminal D of the trigger structure, and after the clock delay, the data is latched in the first latch structure through the first inverter circuit from the input terminal D of the trigger;
[0025] When the clock signal CLK is 1, the data is latched in the second latch structure; the third inverter circuit inverts the signal in the flip-flop structure and sends it to the output signal Q of the flip-flop structure.
[0026] Compared with the prior art, the present invention has the following beneficial effects:
[0027] 1. The circuit structure proposed in the present invention adopts a design concept of integrated detection and self-recovery. It can self-recover and adapt to system-level pipeline error correction scenarios, which can effectively reduce the single-particle soft error rate and achieve anti-radiation reinforcement.
[0028] 2. The circuit structure proposed in the present invention generates a single-particle upset detection signal, which can be used as a control signal for the system-level pipeline to achieve system-level error correction
[0029] 3. The circuit structure provided by the present invention can be applied to the design of integrated circuits at different process nodes and has good adaptability. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 This is the schematic diagram of the trigger structure;
[0031] Figure 2 is a structural diagram of a latch structure;
[0032] Figure 3 It is a schematic diagram of the signal transmission structure of clock control;
[0033] Figure 4 This is the structure diagram of the clock-controlled XOR gate;
[0034] Figure 5 It is a schematic diagram of the delay filter structure; DETAILED DESCRIPTION
[0035] The present application is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0036] The present invention discloses a trigger structure for single-particle upset detection and self-recovery, comprising a time-delay filter structure, a two-input data selector, a clock-controlled XOR gate, an inverter, a clock-controlled signal transmission structure and a latch structure. The time-delay filter structure is used to perform single-particle transient reinforcement on the clock signal and generate a clock signal for a soft error detection structure. The two-input data selector is used to select an appropriate input signal to input into the latch structure. The clock-controlled XOR gate is used to detect whether a single-particle upset occurs in the output of the trigger. The inverter circuit is used to invert the clock signal and the data signal to ensure the logic function of the circuit. The clock-controlled signal transmission structure is used to control the propagation of the signal in the circuit. The latch structure is used to latch data. The circuit structure designed by the present invention can detect and recover data for single-particle upsets, can be applied to system-level overall design, and is easy to implement.
[0037] Figure 1 The figure shows a specific schematic diagram of a single-particle upset detection and self-recovery trigger structure provided by the present application, including a first inverter circuit 101, a second inverter circuit 103, a third inverter circuit 105, a fourth inverter circuit 107, a fifth inverter circuit 110, a sixth inverter circuit 111, a first clock-controlled signal transmission structure 109, a first latch structure 102, a second latch structure 104, a two-input data selector 112, a delay filter structure 108, and a clock-controlled XOR gate 106.
[0038] The purpose of the inverter circuit is to invert the input signal to ensure the correct logic function of the circuit. The purpose of the clock-controlled signal transmission structure is to control data transmission through the clock signal. The latch structure realizes the circuit data latch function. The purpose of the two-input data selector is to select the appropriate signal input to the latch structure. The purpose of the delay filter structure is to delay the clock signal to achieve anti-single-particle transient reinforcement. The purpose of the clock-controlled XOR gate is to generate a single-particle upset detection signal.
[0039] The first inverter circuit 101, the second inverter circuit 103, and the third inverter circuit 105 can constitute a data transmission circuit; the first latch structure 102 constitutes a detection latch structure; the second latch structure 104 constitutes a slave latch structure; the first clock-controlled signal transmission structure 109, the fifth inverter circuit 110, the sixth inverter circuit 111, and the two-input data selector 112 constitute a master latch structure; the fourth inverter circuit 107 and the delay filter structure 108 constitute a clock output circuit.
[0040] The input end of the first inverter circuit 101 is the data input end of the trigger structure, and the output end of the first inverter circuit 101 is connected to the data input end of the first clock-controlled signal transmission structure 109 and the data input end of the first latch structure 102 at the same time; the input end of the fifth inverter circuit 110 is connected to the output end of the first clock-controlled signal transmission structure 109 and the output end of the sixth inverter circuit 111 at the same time, and the input end of the sixth inverter circuit 111 is connected to the output end of the two-input data selector 112, and the output end of the fifth inverter circuit 110 is connected to the output end of the second input data selector 112. The output end of the first latch structure 102 is simultaneously connected to the first input end of the two-input data selector 112 and the data input end of the second latch structure 104; the data output end of the first latch structure 102 is simultaneously connected to the input end of the second inverter circuit 103 and the second input end of the two-input data selector 112; the output end of the second inverter circuit 103 is connected to the second input end of the clock-controlled XOR gate 106; the data output end of the second latch structure 104 is connected to the input end of the third inverter circuit 105, and the output end of the third inverter circuit 105 is connected to the first input end of the clock-controlled XOR gate 106;
[0041] The input end of the fourth inverter circuit 107 is the clock input end of the trigger structure, connected to the clock input end CP1 of the first clock-controlled signal transmission structure 109, the clock input end CK2 of the second latch structure 104, and the input end of the delay filter structure 108, and the output end of the fourth inverter circuit 107 is connected to the clock input end CP2 of the first clock-controlled signal transmission structure 109 and the clock input end CK1 of the second latch structure 104;
[0042] The clock input terminal CK2 of the first latch structure 102 is connected to the second output terminal of the delay filter structure 108, and the clock input terminal CK1 of the first latch structure 102 is connected to the first output terminal of the delay filter structure 108 and the clock input terminal of the clock-controlled XOR gate 106; the output terminal of the clock-controlled XOR gate 106 is connected to the data selection terminal of the two-input data selector 112.
[0043] The first latch structure 102 and the second latch structure 104 have the same structure. Figure 2 A schematic structural diagram of a latch structure (102 / 104) provided in an embodiment of the present application is shown.
[0044] The latch structure (102 / 104) may include a second clock-controlled signal transmission structure 201, a seventh inverter circuit 202, and an eighth inverter circuit 203. The data input terminal of the second clock-controlled signal transmission structure 201 is the data input terminal IN of the latch structure (102 / 104), the clock input terminal CP1 of the second clock-controlled signal transmission structure 201 is the clock input terminal CK1 of the latch structure (102 / 104), the clock input terminal CP2 of the second clock-controlled signal transmission structure 201 is the clock input terminal CK2 of the latch structure (102 / 104), and the output terminal of the second clock-controlled signal transmission structure 201 is connected to the input terminal of the seventh inverter circuit 202 and the output terminal of the eighth inverter circuit 203. The output terminal of the seventh inverter circuit 202 is connected to the input terminal of the eighth inverter circuit 203 to form the output terminal OUT of the latch structure (102 / 104).
[0045] The signal transmission structure 109 controlled by the first clock and the signal transmission structure 201 controlled by the second clock have the same structure. Figure 3The schematic diagram of the clock-controlled signal transmission structure (109 / 201) of the present application is shown. The clock-controlled signal transmission structure (109 / 201) may include a first PMOS 301, a second PMOS 302, a first NMOS 303, and a second NMOS 304. The gate of PMOS301 and the gate of NMOS304 are connected together as the input terminal IN of the clock-controlled signal transmission structure (109 / 201); the source of PMOS301 is connected to the power supply VDD; the drain of PMOS301 is connected to the source of PMOS302; the gate of PMOS302 is connected to the clock input terminal CP1 of the clock-controlled signal transmission structure (109 / 201); the drain of PMOS302 is connected to the drain of NMOS303 and serves as the output terminal OUT of the clock-controlled signal transmission structure (109 / 201); the gate of NMOS303 is connected to the clock input terminal CP2 of the clock-controlled signal transmission structure (109 / 201); the source of NMOS303 is connected to the drain of NMOS304; the source of NMOS304 is connected to the power ground GND.
[0046] like Figure 4 As shown, the clock-controlled XOR gate includes a two-input XOR gate 401 and a two-input AND gate 402. The first input end of the two-input XOR gate 401 serves as the first input end of the clock-controlled XOR gate, the second input end of the two-input XOR gate 401 serves as the second input end of the clock-controlled XOR gate, and the output end of the two-input XOR gate 401 is connected to the second input end of the two-input AND gate 402; the first input end of the two-input AND gate 402 serves as the clock input end CLK_RH of the clock-controlled XOR gate, and the output end of the two-input AND gate 402 serves as the output end of the clock-controlled XOR gate.
[0047] like Figure 5 As shown, the delay filter structure includes a third PMOS 501, a fourth PMOS 502, a third NMOS 503, a fourth NMOS 504, a delay circuit 505 and a ninth inverter circuit 506. Among them, the gate of the PMOS 501, the gate of the NMOS 504 and the input end of the delay circuit 505 are connected together as the input end IN of the filter circuit, the source of the PMOS 501 is connected to the power supply VDD, the drain of the PMOS 501 is connected to the source of the PMOS 502, the gate of the PMOS 502 and the gate of the NMOS 503 are connected to the output end of the delay circuit 505, the drain of the PMOS 502 is connected to the drain of the NMOS 503 and serves as the second output end OUT2 of the filter circuit, the source of the NMOS 503 is connected to the drain of the NMOS 504, the source of the NMOS 504 is connected to the power supply ground GND, the input end of the inverter circuit 506 serves as the second output end OUT2 of the filter circuit, and the output end of the inverter circuit 506 serves as the first output end OUT1 of the filter circuit.
[0048] In the present invention, the first inverter circuit 101 is used to invert the input signal of the memory and input it into the first clock-controlled signal transmission structure 109 and the first latch structure 102. The second inverter circuit 103 is used to invert the output signal of the first latch structure 102, and the third inverter circuit 105 is used to invert the output signal of the second latch structure 104, and is used to output the signal Q. Ensure that the circuit logic is correct. The first latch structure 102 is connected to the second input end of the two-input data selector 112 as the output end of the detection latch structure, the output end of the first clock-controlled signal transmission structure 109 is connected to the input end of the fifth inverter circuit 110 and the output end of the sixth inverter circuit 111, the output end of the fifth inverter circuit 110 is connected to the first input end of the two-input data selector 112, and the output end of the two-input data selector 112 is connected to the input end of the sixth inverter circuit 111. The first clock-controlled signal transmission structure 109, the fifth inverter circuit 110, the sixth inverter circuit 111, and the two-input data selector 112 realize the main latch structure function.
[0049] The first latch structure 102 is used as a detection latch structure to latch input data after a certain delay, and the latched data is used as recovery data after a single event upset is detected. The second latch structure 104 is used as a slave latch structure of a trigger to implement a trigger function.
[0050] The first input terminal of the clock-controlled XOR gate 106 is connected to the circuit output Q, and the second input terminal is connected to the inverter circuit 103 output Q_R. By comparing the two input signals, a single event upset detection signal is generated as the circuit output D_Error.
[0051] When the clock signal CLK is 0, the data is latched in the main latch through the first inverter circuit 101 and the first clock-controlled signal transmission structure 109 from the input terminal D of the trigger. After the clock delay, the data is latched in the detection latch structure 102 through the first inverter circuit 101 from the input terminal D of the trigger. When the clock signal CLK is 1, the data is latched in the second latch structure 104; the third inverter circuit 105 inverts the signal in the trigger structure and sends it to the output signal Q of the trigger structure.
[0052] use Figure 4 , Figure 5 The structure shown can detect the flip caused by SEU in the circuit data input terminal SET and the master-slave latch unit, and generate a detection signal.
[0053] Figure 5In the embodiment, the delay filter structure filters the clock end signal to filter out the single particle transient pulse from the clock end, and the clock signals CLK_RH and CLKN_RH output by the delay filter structure are used as the clock signals of the detection latch structure and the XOR gate structure of the clock control.
[0054] Figure 4 In the embodiment, when the clock input signal CLK_RH in the clock-controlled XOR gate is 1, when the input signals IN1 and IN2 are the same, the clock-controlled XOR gate output signal OUT is 0, and when the input signals IN1 and IN2 are different, the clock-controlled XOR gate output signal OUT is 1; when the clock input signal CLK_RH in the clock-controlled XOR gate is 0, the clock-controlled XOR gate circuit is reset, and at this time, regardless of whether the input signals IN1 and IN2 are the same, the circuit output signal OUT is 0. In actual application, when the clock is at a high level, the output signal Q_R of the latch structure 102 after being inverted by 103 is compared with the output signal Q of the latch structure 104 after being inverted by 105. If the two are the same, the output D_Error signal is 0, indicating that no single particle upset occurs in the circuit; if the two are different, the output D_Error signal is 1, indicating that a single particle upset occurs in the circuit. The D_Error signal can be used as a control and enable signal for the clock signal in the system-level pipeline. When D_Error is 0, the required clock is generated normally. When D_Error is 1, the clock signal is reset to zero to prevent the single-particle upset from being transmitted to the next stage of the pipeline.
[0055] The circuit structure proposed in the present invention can realize the detection and self-recovery effect of the trigger structure on the single particle upset.
[0056] The input of the circuit is D, which passes through a main latch structure composed of a clock-controlled signal transmission structure, an inverter circuit, and a two-input data selector circuit. The selection signal of the two-input data selector circuit is a single-particle upset detection signal D_Error. The clock signals required for normal transmission of the trigger are CLK and CLKN. The clock signals after CLK is delayed and filtered are CLK_RH and CLKN_RH, which are used as clock signals for detecting the latch structure to realize the flip detection function of the trigger structure. The detection and self-recovery effect of the single-particle upset realized by the structure proposed by the present invention are described in three cases A, B and C.
[0057] A. Detection and data recovery of single event upset caused by single event transient (SET) at the data end of the trigger
[0058] (1) When the data terminal D of the trigger has SET and can be sampled by the clock CLK, the output node Q in the trigger will flip, and a single-particle flip will occur. In this example, the data latched in the main latch structure is not only determined by the data sampled by the clock CLK, but also by the data sampled by the clock CLK_RH of the detection latch structure. Since the clocks CLK_RH and CLKN_RH connected to the detection latch structure are delayed and filtered, if the pulse width of the SET at the data terminal does not exceed the delay, the SET will not be stored by the detection latch structure. At this time, the output Q_R is error-free.
[0059] (2) The clock-controlled XOR gate circuit compares the output data Q and the output data Q_R. When CLK_RH=1, if Q_R is the same as Q, the detection signal D_Error is 0, indicating that no single-particle upset occurs in the circuit. If Q_R is different from Q, the detection signal D_Error is 1, indicating that a single-particle upset occurs in the circuit, thus realizing the detection of a single-particle upset. When CLK_RH=0, D_Error is reset to 0.
[0060] (3) The D_Error signal is used as the latch data selection signal of the main latch structure. When D_Error is 1, the data stored in the detection latch structure is selected as the input of the main latch structure. At this time, Q_R has no error. Therefore, the correct data is normally transmitted to the trigger output in the next clock cycle.
[0061] B. Detection and data recovery of single-particle upset caused by SET on clock CLK
[0062] (1) When the clock input CLK of the trigger is SET and the data is switched, the wrong data is sampled and a single-particle upset occurs at the output Q. Since the clock CLK_RH of the detection latch structure is delayed and filtered, the clock SET pulse width is less than the delay, and the SET cannot be transmitted to the CLK_RH signal end. At this time, the detection latch structure does not perform erroneous sampling, still stores the original data, and the output Q_R does not change, maintaining the correct data.
[0063] (2) The XOR gate circuit controlled by the clock CLK_RH compares the output data Q and the output data Q_R. If error data is sampled, the detection signal D_Error is 1, indicating that a single-particle upset is detected. The detection signal D_Error is reset to 0 when CLK_RH=0.
[0064] (3) Same as A(3), the D_Error signal is used as the latch data selection signal of the main latch structure. When D_Error=1, the data stored in the detection latch structure is selected as the input of the trigger main latch structure to realize data recovery.
[0065] C. Detection and data recovery of output flip caused by SEU in the master-slave latch structure
[0066] (1) SEU occurs in the master latch structure or the slave latch structure, causing the trigger output Q to flip, but Q_R still holds the correct data.
[0067] (2) At this time, Q_R and Q are XORed, and the detection signal D_Error is 1, realizing the detection of single event upset caused by SEU. When CLK_RH=0, D_Error is reset.
[0068] (3) Same as A(3), D_Error is used as a data two-choice control signal. When D_Error=1, the data stored in the detection latch structure is selected as the input of the trigger main latch structure to realize data recovery.
[0069] Although the present application is disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field may make possible changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims of the present application.
Claims
1. A trigger structure for single event upset detection and self-recovery, characterized in that: The invention comprises a first inverter circuit (101), a second inverter circuit (103), a third inverter circuit (105), a fourth inverter circuit (107), a fifth inverter circuit (110), a sixth inverter circuit (111), a first clock-controlled signal transmission structure (109), a first latch structure (102), a second latch structure (104), a two-input data selector (112), a delay filter structure (108) and a clock-controlled XOR gate (106); The input end of the first inverter circuit (101) is the data input end of the trigger structure, and the output end of the first inverter circuit (101) is simultaneously connected to the data input end of the first clock-controlled signal transmission structure (109) and the data input end of the first latch structure (102); the input end of the fifth inverter circuit (110) is simultaneously connected to the output end of the first clock-controlled signal transmission structure (109) and the output end of the sixth inverter circuit (111), the input end of the sixth inverter circuit (111) is connected to the output end of the two-input data selector (112), and the output end of the fifth inverter circuit (110) is simultaneously connected to the output end of the first clock-controlled signal transmission structure (109) and the output end of the sixth inverter circuit (111). The first latch structure (102) is connected to the first input end of the two-input data selector (112) and the data input end of the second latch structure (104); the data output end of the first latch structure (102) is connected to the input end of the second inverter circuit (103) and the second input end of the two-input data selector (112); the output end of the second inverter circuit (103) is connected to the second input end of the clock-controlled XOR gate (106); the data output end of the second latch structure (104) is connected to the input end of the third inverter circuit (105), and the output end of the third inverter circuit (105) is connected to the first input end of the clock-controlled XOR gate (106); The input end of the fourth inverter circuit (107) is the clock input end of the trigger structure, connected to the clock input end CP1 of the first clock-controlled signal transmission structure (109), the clock input end CK2 of the second latch structure (104), and the input end of the delay filter structure (108); the output end of the fourth inverter circuit (107) is connected to the clock input end CP2 of the first clock-controlled signal transmission structure (109) and the clock input end CK1 of the second latch structure (104); The clock input terminal CK2 of the first latch structure (102) is connected to the second output terminal of the delay filter structure (108); the clock input terminal CK1 of the first latch structure (102) is connected to the first output terminal of the delay filter structure (108) and the clock input terminal of the clock-controlled XOR gate (106); the output terminal of the clock-controlled XOR gate (106) is connected to the data selection terminal of the two-input data selector (112).
2. A trigger structure for single event upset detection and self-recovery according to claim 1, characterized in that: The first latch structure (102) and the second latch structure (104) have the same structure, and both include a second clock-controlled signal transmission structure (201), a seventh inverter circuit (202), and an eighth inverter circuit (203); The data input end of the second clock-controlled signal transmission structure (201) is the data input end of the latch structure, the clock input end CP1 of the second clock-controlled signal transmission structure (201) is the clock input end CK1 of the latch structure, the clock input end CP2 of the second clock-controlled signal transmission structure (201) is the clock input end CK2 of the latch structure, and the output end of the second clock-controlled signal transmission structure (201) is connected to the input end of the seventh inverter circuit (202) and the output end of the eighth inverter circuit (203); The output end of the seventh inverter circuit (202) is connected to the input end of the eighth inverter circuit (203) to serve as the output end of the latch structure.
3. A trigger structure for single event upset detection and self-recovery according to claim 2, characterized in that: The first clock-controlled signal transmission structure (109) and the second clock-controlled signal transmission structure (201) have the same structure, and both include a first PMOS (301), a second PMOS (302), a first NMOS (303), and a second NMOS (304); The gate of the first PMOS (301) is connected to the gate of the second NMOS (304) and serves as a data input terminal of a clock-controlled signal transmission structure; the source of the first PMOS (301) is connected to a power supply VDD; the drain of the first PMOS (301) is connected to a source of the second PMOS (302); the gate of the second PMOS (302) serves as a clock input terminal CP1 of the clock-controlled signal transmission structure; the drain of the second PMOS (302) is connected to the source of the first NMOS (303) and serves as an output terminal of the clock-controlled signal transmission structure; the gate of the first NMOS (303) serves as a clock input terminal CP2 of the clock-controlled signal transmission structure; the source of the first NMOS (303) is connected to the drain of the second NMOS (304); and the source of the second NMOS (304) is connected to a power supply ground GND.
4. A trigger structure for single event upset detection and self-recovery according to claim 1, characterized in that: The clock-controlled XOR gate includes a two-input XOR gate (401) and a two-input AND gate (402); The first input end of the two-input XOR gate (401) serves as the first input end of the clock-controlled XOR gate, the second input end of the two-input XOR gate (401) serves as the second input end of the clock-controlled XOR gate, and the output end of the two-input XOR gate (401) is connected to the second input end of the two-input AND gate (402); The first input terminal of the two-input AND gate (402) serves as the clock input terminal CLK_RH of the clock-controlled XOR gate, and the output terminal of the two-input AND gate (402) serves as the output terminal of the clock-controlled XOR gate.
5. The trigger structure for single event upset detection and self-recovery according to claim 1, characterized in that: The delay filter structure includes a third PMOS (501), a fourth PMOS (502), a third NMOS (503), a fourth NMOS (504), a delay circuit (505) and a ninth inverter circuit (506); The gate of the third PMOS (501), the gate of the fourth NMOS (504) and the input end of the delay circuit (505) are connected together as the input end of the delay filter structure; the source of the third PMOS (501) is connected to the power supply VDD; the drain of the third PMOS (501) is connected to the source of the fourth PMOS (502); the gate of the fourth PMOS (502) and the gate of the third NMOS (503) are connected together and connected to the output end of the delay circuit (505); the drain of the fourth PMOS (502) and the drain of the third NMOS (503) are connected to serve as the second output end of the delay filter structure and are connected to the input end of a ninth inverter circuit (506); the source of the third NMOS (503) is connected to the drain of the fourth NMOS (504); the source of the fourth NMOS (504) is connected to the power supply ground GND; and the output end of the ninth inverter circuit (506) serves as the first output end of the delay filter structure.
6. A trigger structure for single event upset detection and self-recovery according to claim 1, characterized in that: The first inverter circuit (101), the second inverter circuit (103), and the third inverter circuit (105) constitute a data transmission circuit; the first latch structure (102) constitutes a detection latch structure; the second latch structure (104) constitutes a slave latch structure; the first clock-controlled signal transmission structure (109), the fifth inverter circuit (110), the sixth inverter circuit (111), and the two-input data selector (112) constitute a master latch structure; the fourth inverter circuit 107 and the delay filter structure 108 constitute a clock output circuit.
7. A trigger structure for single event upset detection and self-recovery according to claim 6, characterized in that: The first inverter circuit (101) is used to invert the input signal of the memory and input it into the first clock-controlled signal transmission structure (109) and the first latch structure (102); the second inverter circuit (103) is used to invert the output signal of the first latch structure (102); the third inverter circuit (105) is used to invert the output signal of the second latch structure (104) and output a signal Q; The first latch structure (102) is used as a detection latch structure to latch input data after a certain delay, and the latched data is used as recovery data after a single particle upset is detected; the second latch structure (104) is used as a slave latch structure of a trigger to realize a trigger function; The first input end of the clock-controlled XOR gate (106) is connected to the output Q of the third inverter circuit (105), and the second input end is connected to the output Q_R of the second inverter circuit (103). By comparing the two input signals, a single-particle upset detection signal is generated as a circuit output D_Error.
8. A trigger structure for single event upset detection and self-recovery according to claim 7, characterized in that: When the clock signal CLK is 0, data is transmitted from the input end D of the trigger structure through the first inverter circuit (101) and the first clock-controlled signal transmission structure (109) and is latched in the main latch structure. After the clock is delayed, data is transmitted from the input end D of the trigger structure through the first inverter circuit (101) and is latched in the first latch structure (102). When the clock signal CLK is 1, data is latched in the second latch structure (104); the third inverter circuit (105) inverts the signal in the flip-flop structure and sends it to the output signal Q of the flip-flop structure.